Lecture 5
Fault Modeling




Why model faults?
Some real defects in VLSI and PCB
Common fault models
Stuck-at faults






Single stuck-at faults
Fault equivalence
Fault dominance and checkpoint theorem
Classes of stuck-at faults and multiple faults
Transistor faults
Summary
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
1
Why Model Faults?


I/O function tests inadequate for
manufacturing (functionality versus
component and interconnect testing)
Real defects (often mechanical) too
numerous and often not analyzable

A fault model identifies targets for testing

A fault model makes analysis possible

Effectiveness measurable by experiments
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
2
Some Real Defects in Chips




Processing defects
 Missing contact windows
 Parasitic transistors
 Oxide breakdown
 . . .
Material defects
 Bulk defects (cracks, crystal imperfections)
 Surface impurities (ion migration)
 . . .
Time-dependent failures
 Dielectric breakdown
 Electromigration
 . . .
Packaging failures
 Contact degradation
 Seal leaks
 . . .
Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation Semiconductor Devices and Circuits, Wiley, 1981.
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
3
Observed PCB Defects
Occurrence frequency (%)
Defect classes
Shorts
Opens
Missing components
Wrong components
Reversed components
Bent leads
Analog specifications
Digital logic
Performance (timing)
51
1
6
13
6
8
5
5
5
Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
4
Common Fault Models








Single stuck-at faults
Transistor open and short faults
Memory faults
PLA faults (stuck-at, cross-point, bridging)
Functional faults (processors)
Delay faults (transition, path)
Analog faults
For more examples, see Section 4.4 (p. 6070) of the book.
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
5
5week
Fault Tolerant Digital System Desgin
6
x
5week
Fault Tolerant Digital System Desgin
7
5week
Fault Tolerant Digital System Desgin
8
1
0/1
1
1
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
9
5week
Fault Tolerant Digital System Desgin
10
AND
Z(0 1) = Z(1 0) =0
Z(0 1) = Z(1 0) =1
5week
Fault Tolerant Digital System Desgin
OR
11
x
x
( NFBF)
x
x
( FBF)
5week
Fault Tolerant Digital System Desgin
12
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
13
5week
Fault Tolerant Digital System Desgin
14
1
5week
1
Fault Tolerant Digital System Desgin
15
Single Stuck-at Fault

Three properties define a single stuck-at fault




Only one line is faulty
The faulty line is permanently set to 0 or 1
The fault can be at an input or output of a gate
Example: XOR circuit has 12 fault sites ( ) and
24 single stuck-at faults
c
1
0
a
d
b
e
Faulty circuit value
Good circuit value
s-a-0
j
g
1
0(1)
1(0)
h
i
z
1
k
f
Test vector for h s-a-0 fault
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
16
001,011,100,110
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
17
Fault Equivalence




Number of fault sites in a Boolean gate circuit
= #PI + #gates + # (fanout branches).
Fault equivalence: Two faults f1 and f2 are
equivalent if all tests that detect f1 also
detect f2.
If faults f1 and f2 are equivalent then the
corresponding faulty functions are identical.
Fault collapsing: All single faults of a logic
circuit can be divided into disjoint equivalence
subsets, where all faults in a subset are
mutually equivalent. A collapsed fault set
contains one fault from each equivalence
subset.
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
18
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
19
5week
Fault Tolerant Digital System Desgin
20
Equivalence Rules
sa0 sa1
sa0
sa0
sa1
sa1
sa0 sa1
AND
sa0 sa1
sa0 sa1
OR
WIRE
sa0 sa1
sa0 sa1
sa0
sa1
sa0 sa1
NOT
sa1
sa0
sa0 sa1
NAND
sa0 sa1
sa0 sa1
NOR
sa0 sa1
sa0 sa1
sa0
sa1
FANOUT
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
sa0
sa1
sa0
sa1
21
5week
Fault Tolerant Digital System Desgin
22
Equivalence Example
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
Faults in red
removed by
equivalence
collapsing
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20
Collapse ratio = ----- = 0.625
32
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
23
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
24
5week
Fault Tolerant Digital System Desgin
25
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
26
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
27
α
5week
β
Fault Tolerant Digital System Desgin
28
{ 00, 01, 10}
{ 11, 01, 10}
5week
Fault Tolerant Digital System Desgin
01, 10
01, 10
29
Dominance Example
All tests of F2
F1
s-a-1
F2
s-a-1
110
101
001
000
100
010
011
Only test of F1
s-a-1
s-a-1
s-a-1
s-a-0
A dominance collapsed fault set
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
30
Checkpoints


Primary inputs and fanout branches of a
combinational circuit are called checkpoints.
Checkpoint theorem: A test set that detects
all single (multiple) stuck-at faults on all
checkpoints of a combinational circuit, also
detects all single (multiple) stuck-at faults in
that circuit.
Total fault sites = 16
Checkpoints ( ) = 10
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
31
Classes of Stuck-at Faults

Following classes of single stuck-at faults are
identified by fault simulators:





Potentially-detectable fault -- Test produces an
unknown (X) state at primary output (PO);
detection is probabilistic, usually with 50%
probability.
Initialization fault -- Fault prevents initialization of
the faulty circuit; can be detected as a potentiallydetectable fault.
Hyperactive fault -- Fault induces much internal
signal activity without reaching PO.
Redundant fault -- No test exists for the fault.
Untestable fault -- Test generator is unable to find
a test.
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
32
Example: Initialization
fault
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
33
Multiple Stuck-at Faults




A multiple stuck-at fault means that any set
of lines is stuck-at some combination of (0,1)
values.
The total number of single and multiple
stuck-at faults in a circuit with k single fault
sites is 3k-1.
A single fault test can fail to detect the
target fault if another fault is also present,
however, such masking of one fault by
another is rare.
Statistically, single fault tests cover a very
large number of multiple faults.
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
34
Models of fault in PLA-s and PAL-s
1.
2.
3.
Permanent constant faults;
Short-circuits;
Crosspoint Faults ;
appearance of CP-s in the AND
array;;
disappearance of CP-s from the AND
array;
appearence of CP-s in the OR array;
disappearance of CP-s from the OR
array.
Classical model of fault: constant 1 and 0 (Stuck-at-0, Stuck-at-1, s-a-0, s-a-1)
s-a-0
s-a-1
X
f
X
f
Short
X
f1
X
X
X
f2
f1
Example.
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y2 = x1 x2 x3 + x1 x2
x1
+V
x2
1
0
x3
1
1
y
1
y
2
Permanent constant faults in PLA/PAL-s
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y2 = x1 x2 x3 + x1 x2
x1
+V
X3 s-a-1fault
x2
1
y1 = x1 x2 + x1 x2 x3 + x1 x2
y2 = x1 x2 + x1 x2
0
x3
1
1
s-a-1
y
1
y
2
Crosspoint Faults
Appearance of CP-s to in the AND array
Unnecessary
variable
Shrinkage fault
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
Unnecessary CP
y2 = x1 x2 x3 + x1 x2
x1
x2
1
+V
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 x3
y2 = x1 x2 x3 + x1 x2 x3
0
x3
1
1
Carnaugh Map
Faultless
y2
x1
0
1
00
1
0
x 2x3
01
11
0
0
0
1
10
0
1
y
Faulty
y2
x1
0
1
00
1
0
y
1
x2x3
01
11
0
0
0
1
2
10
0
0
Disappearance of CP-s from the AND array
Growth fault
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y2 = x1 x2 x3 + x1 x2
CP does not exist x 1
x2
1
+V
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y2 = x1 x2 x3 + x1
CP does not exist
0
x3
1
1
Carnaugh Map
Faultless
y2
x1
0
1
00
1
0
x 2x3
01
11
0
0
0
1
10
0
1
y
Faulty
y2
x1
0
1
00
1
1
y
1
x2x3
01
11
0
0
1
1
2
10
0
1
Appearance of a new CP to the OR-array
Appearance fault
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y2 = x1 x2 x3 + x1 x2
x1
x2
1
+V
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y2 = x1 x2 x3 + x1 x2 + x1 x2 x3
Unnecessary CP
0
x3
1
1
Carnaugh Map
Faultless
y2
x1
0
1
00
1
0
x 2x3
01
11
0
0
0
1
10
0
1
y
Faulty
y2
x1
0
1
00
1
0
y
1
x2x3
01
11
0
0
1
1
2
10
0
1
Disapperance of the CP from the OR-array
Disappearance fault
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y2 = x1 x2 x3 + x1 x2
x1
CP does not exist
x2
1
+V
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y2 = x1 x2 x3
0
x3
1
CP
does not
exist
1
Carnaugh Map
Faultless
y2
x1
0
1
00
1
0
y
x 2x3
01
11
0
0
0
1
10
0
1
Faulty
y2
x1
0
1
00
1
0
y
1
x2x3
01
11
0
0
0
0
2
10
0
0
Transistor (Switch) Faults

MOS transistor is considered an ideal switch
and two types of faults are modeled:




Stuck-open -- a single transistor is permanently
stuck in the open state.
Stuck-short -- a single transistor is permanently
shorted irrespective of its gate voltage.
Detection of a stuck-open fault requires two
vectors.
Detection of a stuck-short fault requires the
measurement of quiescent current (IDDQ).
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
42
Stuck-Open Example
Vector 1: test for A s-a-0
(Initialization vector)
pMOS
FETs
1
0
0
0
A
B
nMOS
FETs
Copyright 2001, Agrawal & Bushnell
Vector 2 (test for A s-a-1)
VDD
Stuckopen
C
0
Two-vector s-op test
can be constructed by
ordering two s-at tests
1(Z)
Good circuit states
Faulty circuit states
VLSI Test: Lecture 5
43
Stuck-Short Example
Test vector for A s-a-0
pMOS
FETs
1
0
A
VDD
IDDQ path in
faulty circuit
Stuckshort
B
nMOS
FETs
Copyright 2001, Agrawal & Bushnell
C
Good circuit state
0 (X)
Faulty circuit state
VLSI Test: Lecture 5
44
Transistor Faults
 Any
transistor can be
 Stuck-short
– Also known as stuck-on
 Stuck-open
– Also known as stuck-off
# fault types: k=2
 Example
circuit
 # fault sites: n=4
 # single faults =2×4=8
EE141
VLSI
Test Principles and Architectures
VDD
A
2-input
CMOS
NOR
gate
P1
B
P2
Z
N1
N2
Open
VSS
Truth table for fault-free circuit
and all possible transistor faults
AB
00
01
10 11
Z
1
0
0
0
N1 stuck-open 1
0 last Z 0
N1 stuck-short IDDQ 0
0
0
N2 stuck-open 1 last Z 0
0
N2 stuck-short IDDQ 0
0
0
P1 stuck-open last Z 0
0
0
P1 stuck-short
1
0 IDDQ 0
P2 stuck-open last Z 0
0
0
P2 stuck-short
1 IDDQ 0
0
45
Ch. 1 - Introduction - P. 45
Transistor Faults
 Stuck-short
faults cause
conducting path from VDD
to VSS
 Can be detect by monitoring
steady-state power supply
current IDDQ
 Stuck-open
faults cause
output node to store last
voltage level
 Requires sequence of 2
vectors for detection
– 0010 detects N1 stuck-open
EE141
VLSI
Test Principles and Architectures
VDD
A
2-input
CMOS
NOR
gate
P1
B
P2
Z
N1
N2
VSS
Truth table for fault-free circuit
and all possible transistor faults
AB
00
01
10 11
Z
1
0
0
0
N1 stuck-open 1
0 last Z 0
N1 stuck-short IDDQ 0
0
0
N2 stuck-open 1 last Z 0
0
N2 stuck-short IDDQ 0
0
0
P1 stuck-open last Z 0
0
0
P1 stuck-short
1
0 IDDQ 0
P2 stuck-open last Z 0
0
0
P2 stuck-short
1 IDDQ 0
0
46
Ch. 1 - Introduction - P. 46
Transistor Faults
#





collapsed faults = 2×T -TS+GS -TP+GP
T = number of transistors
TS= number of series transistors
GS= number of groups of series transistors
TP= number of parallel transistors
GP= number of groups of parallel transistors
 For
example circuit, # collapsed faults = 6
 T=4, TS= 2, GS= 1, TP= 2, & GP= 1
 Fault
collapsing typically reduces number
of transistor faults by 25% to 35%
EE141
VLSI
Test Principles and Architectures
47
Ch. 1 - Introduction - P. 47
Summary





Fault models are analyzable approximations of
defects and are essential for a test
methodology.
For digital logic single stuck-at fault model
offers best advantage of tools and experience.
Many other faults (bridging, stuck-open and
multiple stuck-at) are largely covered by
stuck-at fault tests.
Stuck-short and delay faults and technologydependent faults require special tests.
Memory and analog circuits need other
specialized fault models and tests.
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 5
48