Dual VP Classes
Eric Allender
Rutgers University
Joint work with
Anna Gál (U. Texas) and Ian Mertz (Rutgers)
MFCS, Milan, August 27, 2015
Our Contributions

New characterizations of ACC1 and TC1.

New examples of fan-in reduction.

Highlight connections between ACC1 and VP.

Revisit the Immerman-Landau Conjecture, and
offer some new conjectures about circuit
complexity classes.

But first …let’s review the relevant complexity
classes.
Eric Allender: Dual VP Classes
<2>
NP
P
Fan-in is
Important!
AC1
Log-Depth
NL
Poly-size
L
NC1
Eric Allender: Dual VP Classes
AC0
Unbounded
Fan-in
Fan-in 2
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NP
Fan-in is
Important!
P
AC1
Log-Depth
Poly-size
SAC1=LogCFL
NL
L
NC1
Semi-unbounded
fan-in
Λ fan-in 2
V fan-in nk
Eric Allender: Dual VP Classes
AC0
<4>
NP
P
TC1
Log
depth
Components are
Important!
AC1
SAC1=LogCFL
NL
Majority gates
L
NC1
O(1)
TC0
depth
Eric Allender: Dual VP Classes
AC0
<5>
P#P
NP
P
TC1
AC1
SAC1=LogCFL
L#L = LDet(Q)
NL
L
NC1
TC0
Eric Allender: Dual VP Classes
AC0
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P#P =PVNP(Q)
NP
P
TC1
AC1
SAC1=LogCFL
L#LogCFL = LVP(Q)
L#L = LDet(Q)
NL
L
NC1
TC0
Eric Allender: Dual VP Classes
AC0
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Valiant’s Class VP

VP(R) is the class of families (fn) of
multivariate polynomials over R such that
– fn has degree nO(1).
– There is a family of arithmetic circuits (Cn) of
size poly(n) such that Cn computes fn.

Furthermore, Cn can be assumed to have
depth O(log n) with fan-in 2 x and unbounded
fan-in +. (Semiunbounded fan-in arithmetic
circuits.)

#SAC1 = the functions in VP(N).
Eric Allender: Dual VP Classes
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P#P =PVNP(Q)
NP
P
TC1
AC1
SAC1=LogCFL
L#LogCFL = LVP(Q)
L#L = LDet(Q)
NL
L
NC1
TC0
Eric Allender: Dual VP Classes
AC0
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# AC1(Q)
P#P =PVNP(Q)
NP
P
TC1
Not contained in
1
AC
P for a trivial reason:
1=LogCFL
SAC
The output has more
L#LogCFL = LVP(Q) =L#SAC1
L#L = LDet(Q)
than poly-many bits. NL
L
#NC1(Q)
NC1
TC0
Eric Allender: Dual VP Classes
AC0
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P#P =PVNP(Q)
NP
P
The meaning of
Fpn is: Circuit
Cn is interpreted
modulo the
nth prime.
TC1 = # AC1(Fpn)
AC1
LVP(Fpn) = L#LogCFL = LVP(Q) =L#SAC1
SAC1=LogCFL
L#L = LDet(Q)
NL
L
#NC1(Q) ≈ # NC1(Fpn)
NC1
TC0 = # AC0(Fpn) ≈ # AC0(Q)
Eric Allender: Dual VP Classes
AC0
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P#P =PVNP(Q)
NP
P
TC1 = # AC1(Fpn)
ACC1 = Uq # AC1(Fq)
AC1
ACCi =
Um ACi[m]
LVP(Fpn) = L#LogCFL = LVP(Q) =L#SAC1
SAC1=LogCFL
L#L = LDet(Q)
NL
L
#NC1(Q)
NC1
TC0
ACC0 = Uq # AC0(Fq)
Eric Allender: Dual VP Classes
AC0
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P#P =PVNP(Q)
NP
P
TC1 = # AC1(Fpn)
ACC1
AC1
Our focus
lies here.
LVP(Fpn) = L#LogCFL = LVP(Q) =L#SAC1
SAC1=LogCFL
L#L = LDet(Q)
NL
L
#NC1(Q)
NC1
TC0
ACC0
Eric Allender: Dual VP Classes
AC0
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Dual VP Classes
SAC1=LogCFL =
VP(R): Unbounded +
VP(B2): Unbounded V
Bounded x
Bounded Λ
But LogCFL is closed under complement!
[BCDRT]
Eric Allender: Dual VP Classes
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Dual VP Classes
SAC1=LogCFL =
VP(R): Unbounded +
Bounded x
VP(B2): Unbounded V
Bounded Λ
=
Unbounded Λ
Bounded V
Eric Allender: Dual VP Classes
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Dual VP Classes
SAC1=LogCFL =
VP(R): Unbounded +
VP(B2): Unbounded V
Bounded Λ
Bounded x
=
ΛP(R): Unbounded x
ΛP(B2): Unbounded Λ
Bounded +
Bounded V
Is this interesting??
Eric Allender: Dual VP Classes
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New Characterizations of ACC1
ACC1= Uq #AC1(Fq)

= Uq ΛP(Fq)
 Fan-in Reduction
(from unbounded to semiunbounded)
 #AC1(Fq) = AC1[q(q-1)]
 ΛP(Fq) = AC1[q-1]

Eric Allender: Dual VP Classes
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…and TC1
ACC1= Uq #AC1(Fq)

= Uq ΛP(Fq)
 Fan-in Reduction
(from unbounded to semiunbounded)
 #AC1(Fq) = AC1[q(q-1)]
 ΛP(Fq) = AC1[q-1]

 TC1 =
Eric Allender: Dual VP Classes
# AC1(Fpn) = LΛP(Fpn)
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Boolean Fan-In Reduction

By definition, AC1[m] has poly size, log depth,
with unbounded fan-in MODm, V and Λ gates.

Theorem: The fan-in of the V and Λ gates can
be reduced to log n, with no loss of
computational power.
– In symbols: AC1[m] = log-AC1[m].

Theorem: If m is not a prime power, then the
fan-in can be reduced to 2, with no loss of
power. AC1[m] = 2-AC1[m].

…and to ZERO! AC1[m] = 0-AC1[m].
Eric Allender: Dual VP Classes
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ACC1 and VP
That is: ACC1 corresponds to uniform families
of MODm gates (with no other hardware).
 Compare the circuit characterization of ACC1
with the circuit characterization of VP(Fq):
– For any odd prime q, VP(Fq) is the class of
languages accepted by uniform families of
MODq gates (with no other hardware).

Eric Allender: Dual VP Classes
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ACC1 and VP
That is: ACC1 corresponds to uniform families
of MODm gates (with no other hardware).
 Compare the circuit characterization of ACC1
with the circuit characterization of VP(Fq):
– For any odd prime q, VP(Fq) is the class of
languages accepted by uniform families of
MODq gates (with no other hardware).
 Thus, over finite fields, the difference between
VP and ΛP (=ACC1) boils down to the
difference between primes and composites.

Eric Allender: Dual VP Classes
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Degree Reduction

We have seen examples of fan-in reduction for
Boolean circuits (such as AC1[5] = log-AC1[5]).
 And we have seen examples of fan-in
reduction for arithmetic circuits
(such as Uq #AC1(Fq) = Uq ΛP(Fq))…
 …which only reduced the fan-in of + gates –
and hence did not result in a reduction of the
degree of the polynomial represented.
 Should we expect any reduction of the fan-in
of x gates to be possible?
Eric Allender: Dual VP Classes
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Degree Reduction

Should we expect any reduction of the fan-in
of x gates to be possible?

Consider the Immerman-Landau conjecture:
– TC1= LDet(Q)
– Equivalently:
# AC1(Fpn) = LDet(Q) = LVP(Q) = LVP(Fpn)
 [Buhrman
et al] argued that it would be
unlikely for a high-degree arithmetic class
to coincide with a polynomial-degree
arithmetic class.
Eric Allender: Dual VP Classes
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Degree Reduction

We present examples where degree reduction
is possible.
Define #WSAC1 to be circuits with a “weak”
form of the semiunbounded fan-in restriction:
poly-size, log depth circuits with unbounded
fan-in + gates, and logarithmic-fan-in x gates.
 Theorem: For any prime q,
AC1[q] = #WSAC1(Fq).
 Corollary: #AC1(F2) = #WSAC1(F2).

Eric Allender: Dual VP Classes
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Degree Reduction

Consider #AC1(F2) = #WSAC1(F2).

Polynomials in #AC1(F2) have degree nO(log n).

Polynomials in #WSAC1(F2) have degree
nO(log log n).

This is proved using off-the-shelf techniques
(isolation lemma, derandomization using walks
on expanders). We see no reason why
degree nO(log log n) should be optimal.

If it can be reduced to nO(1), then
#AC1(F2) = VP(F2).
Eric Allender: Dual VP Classes
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Degree Reduction

Consider #AC1(F2) = #WSAC1(F2).

Polynomials in #AC1(F2) have degree nO(log n).

Polynomials in #WSAC1(F2) have degree
nO(log log n).

This is proved using off-the-shelf techniques
(isolation lemma, derandomization using walks
on expanders). We see no reason why
degree nO(log log n) should be optimal.

If it can be reduced to nO(1), then
#AC1(F2) = VP(F2) = ΛP(F3).
Eric Allender: Dual VP Classes
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Open Questions

We believe that the arguments presented
against the Immerman-Landau conjecture –
which are based on degree-reduction being
unlikely – are weakened by examples of
degree-reduction. Can one improve the
degree reduction?

Can the connection between ACC1 and VP be
strengthened?

Is Um LVP(Zm) equal to Um AC1[m] (= ACC1)?

This would imply AC1 is contained in LVP[Zm] for
some m.
Eric Allender: Dual VP Classes
< 27 >
Open Questions

We believe that the arguments presented
against the Immerman-Landau conjecture –
which are based on degree-reduction being
unlikely – are weakened by examples of
degree-reduction. Can one improve the
degree reduction?

Can the connection between ACC1 and VP be
strengthened?

Is Um LVP(Zm) equal to Um AC1[m] (= ACC1)?

This would imply AC1 is contained in LVP[Zm] for
some m. (SAC1 is there, nonuniformly.)
Eric Allender: Dual VP Classes
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Thank you!
Eric Allender: Dual VP Classes
< 29 >
#P
NP
P
TC1
ACC1
AC1
SAC1=LogCFL
NL
L
#NC1
NC1
TC0
ACC0
Eric Allender: Dual VP Classes
AC0
< 30 >