1
Experiment no.1
Aim: - Introduction to digital electronics lab- nomenclature of digital ICs, specifications, study of the
data sheet, concept of Vcc and ground, verification of the truth tables of logic gates using TTL ICs.
Apparatus required: - Ic (7508, 7432, 7404, 7400, 7402 and 7486), 5 volt d.c supply, bread board,
connecting wires, patch cord, main cord, digital lab trainer kit etc.
Theory:
Digital electronics is a branch of electronics in which each component, devices and circuitry operate
only at two predefined level of voltage and current or any other quantity like frequency.
These levels are represented by ‘1’ or ‘0’ and are usually HIGH and LOW.
Digital electronics and analog electronics both are based on transistor but in digital electronics,
transistor operates in their cut-off and saturation region. So digital is over taking the analog in race
because of its better flexibility possibility and noise immunization.
Digital electronics building block:
Logic gates--------Flip-flop------------
NOT, AND, OR, NAND, NOR and EX-OR gate
S-R, J-K, T, D and MASTER SLAVE flip-flop
These blocks combine to from certain complex digital circuits, registers, mux, de-mux, adder and subtractor which perform basic arithmetic and logic operations like addition, subtraction.
Nomenclature of digital ICs, specifications, study of the data sheet, concept of Vcc and
ground, verification of the truth tables of logic gates using TTL ICs.
a) Basic gate, AND, OR, and NOT
b) Universal gate, NAND and NOR
c) Derived gate, EX-OR and EX-NOR
Ic (7508, 7432, 7404, 7400, 7402 and 7486)
AND gate:
The AND gate performs logical multiplication commonly known as AND function. The AND gate has
two or more inputs and only one output. The output of an AND gate is HIGH ‘1’ only when all the
inputs are HIGH ‘1’. Even if any one of the inputs is LOW ‘0’, the output will be LOW ‘0’. Its logical
expression can be given as
Y=A.B=AB
2
Logical symbol AND gate and pin configuration of IC 7408
A
0
0
1
1
B
0
1
0
1
Y  A.B
0
0
0
1
Truth table
OR gate:
The OR gate performs logical addition, commonly known as OR function. The OR gate has two or
more inputs and only one output. The operation of OR gate is such that a HIGH ‘1’ on the output is
produced when any one of the inputs is HIGH ‘1’. The output is LOW ‘0’ only when all the inputs are
LOW ‘0’. Its logical expression can be given as
(Y=A+B)
Logical symbol OR gate and pin configuration of IC 7432
A
0
0
1
1
B Y  A B
0
0
1
1
0
1
1
1
Truth table
3
Procedure:
1. Mount IC of any gate on breadboard.
2. Connect pin no. 7 of IC of any gate to GND and pin no. 14 to Vcc (+5V).
3. Connect pin no. 1 & 2 of IC to logical input states and connect a LED and a resistance of
appropriate value b\w pin no. 3 & GND for output.
4. For initialize experiment according to truth table, input terminal of IC connects to ground for ‘0’
(LOW) state input, and to Vcc (+5V) for ‘1’ (HIGH) state input.
NOT gate:
The working of NOT gate is like inverter it has only one input and only output. Its working is such
that. If input is high ‘1’ then output is low ‘0’. Input is low ‘0’ then output is high ‘1’. Its logical
expression can be give as
Y  A
Logical symbol NOT gate and pin configuration of IC 7404
0
YA
1
1
0
A
Truth table
Procedure:
1. Mount IC 7404on the breadboard.
2. Connect pin no. 7 of IC 7404 to GND and pin no. 14 to Vcc (+5V).
3. Connect pin no. 1 of IC 7404 to logical input states and connect a resistance of appropriate value
and a LED between pin no. 2 and ground (GND) for output.
4. For initialize experiment according to truth table, input terminal of IC connects to ground for ‘0’
(LOW) state input, and to Vcc (+5V) for ‘1’ (HIGH) state input.
NAND gate:
NAND is the contraction of NOT-AND gates, in other words the NAND gate is the complement of
AND gate, it has two or more than two input and only one output. The operation of NAND gate is such
that, when all the inputs are HIGH ‘1’ the output is LOW ‘0’. If any one or both the inputs are LOW
‘0’ then the output is HIGH ‘1’.
Its logical expression can be given as.
4
Y  A.B  AB
Logical symbol NAND gate and pin configuration of IC 7400
A
B
0
0
1
1
0
1
0
1
Truth table
Y  A.B
1
1
1
0
NOR gate:
NOR is the contraction of NOT-OR gates, in other words the NOR gate is the complement of OR gate,
it has two or more inputs and only one output. The operation of NOR gate is such that, the output is
HIGH ‘1’, only when all the inputs are LOW ‘0’. If any one or both the inputs are HIGH ‘1’, then the
output is LOW ‘0’.
Its logical expression can be given as.
Y  A B
Logical symbol NOR gate and pin configuration of IC 7402
A
B
0
0
1
0
1
0
Y  A B
1
0
0
5
1
1
0
Truth table
EX-OR:
An EX-OR gate is a gate with two or more inputs and only one output. The output of a two input EXOR gate assumes a HIGH ‘1’ state if one and only one input assumes a HIGH ‘1’ state. this is
equivalent to saying that the output is HIGH ‘1’ if either input ‘A’ or input ‘B’ is HIGH ‘1’
exclusively, and LOW ‘0’ when both same HIGH ‘1’ or LOW ‘0’ simultaneously.
Its logical expression can be given as
Y  AB  AB  A  B
Logical symbol X-OR gate and pin configuration of IC 7486
A
0
0
1
1
B
Y  A B
0
0
1
1
0
1
1
0
Truth table
Procedure:
1. Mount IC of any gate on breadboard.
2. Connect pin no. 7 of IC of any gate to GND and pin no. 14 to Vcc (+5V).
3. Connect pin no. 1 & 2 of IC to logical input states and connect a LED and a resistance of
appropriate value b\w pin no. 3 & GND for output.
4. For initialize experiment according to truth table, input terminal of IC connects to ground for ‘0’
(LOW) state input, and to Vcc (+5V) for ‘1’ (HIGH) state input.
6
Experiment no.2
Aim:
To implement the Boolean function using logic gates in both SOP & POS forms.
Apparatus require:
Basic gate trainer kit, power supply, patches cord, main cord, etc.
Theory:
One of the primary requirements when dealing with digital circuits is to find ways to make them as
simple as possible. This constantly requires that complex logical expressions be reduced to simpler
expressions that nevertheless produce the same results under all possible conditions. The simpler
expression can then be implemented with a smaller, simpler circuit, which in turn saves the price of
the unnecessary gates, reduces the number of gates needed, and reduces the power and the amount of
space required by those gates.
One tool to reduce logical expressions is the mathematics of logical expressions, introduced by George
Boole in 1854 and known today as Boolean algebra. The rules of Boolean algebra are simple and
straight-forward, and can be applied to any logical expression. The resulting reduced expression can
then be readily tested with a Truth Table, to verify that the reduction was valid.
Implement given POS form Boolean expression by the basic gates and verify the truth table
A
0
0
0
0
1
1
1
1
Truth table
B
C
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Out put
0
0
1
1
1
0
1
1
7
Implement given SOP form Boolean expression by the basic gates and verify the truth table
A
0
0
0
0
1
1
1
1
Truth table
B
C
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Procedure:
1. Make the connection as per diagram on the trainer kit
2. Verify the truth table
Precaution:
1. Handle the trainer kit care fully
2. Use the dc 5vol. supply only
Result:
Boolean expression in both SOP & POS form to be studied.
Out put
0
0
1
1
0
0
0
1
8
Experiment no.3
Aim:
To study of flip-flop (S-R Flip flop, J-K Flip flop, T Flip flop and D Flip flop)
Apparatus required:
Flip flop trainer kit, d.c power supply, connecting leads etc.
S-R Flip flop: It is required to set or reset the memory cell in synchronism with a trainer of pulses
known as clock. When control inputs are low, no change can occur in the output and the circuit
remains latched in its last state. When R is low and S is high, the circuit sets the Q output to a high. On
the other hand, if R is high and S is low, Q output reset to a low. The Q output is the inverse of the Q
output.
Truth table S-R flip-flop
Input
Output Qn+1
S
R
Q
Q
0
0
-----NC----1
0
1
0
0
1
0
1
1
1
-----?---J-K Flip flop: Fig shows a one way to build a J-K flip flop. As before, an RC circuit with a short
time constant converts the regular CLK pulse to narrow spikes. The J & K are control inputs; they
determine what the circuit will do on the positive clock edge. When J & K are low, both inputs are
disabled and the circuit is inactive. When J is low and K is high, the flip flop is reset. On the other
hand, when J is high and K is low, the flip flop is driven into the set state on the next positive CLK
edge. The final possibility is both J and K are high; means the flip flop will toggle on the next positive
CLK edge. When J is high and K is low, rising CLK edge sets Q to high. When J is low and K is high,
rising CLK edge resets Q to low. Finally, if both J and K are high, the output toggles once each rising
CLK edge.
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Inputs
J K
0 0
1 0
0 1
1 1
Output
Qn+1
Qn
1
0
Qn
D-flip flop: If we use only the middle two rows of the truth table of the S-R or J-K flip flop, we
obtain a D-type flip flop. It has only one input referred to as D-input or data input. It is clear from
truth table, that the output Qn+1 at the end of the clock pulse equal the input Dn before the clock
pulse. This is equivalent to saying that the input data appears at the output at the end of the clock
pulse. Thus, the transfer of data from the input to the output is delayed and hence the name delay (Dflip flop).
Truth table D flip-flop
Input
Output
Dn
Qn+1
0
0
1
1
T-flip-flop: In a J-K flip-flop, if J=K, the resulting flip-flop is referred to as T-flip-flop. It has only
one input, referred to as T-input. It is clear from the truth table that if T=1 it acts as a toggle switch.
For every clock pulse. The output Q changes with the change of clock pulse.
10
Truth table for T-flip-flop
Input
Output
Tn
Qn+1
0
Qn
1
Qn
Procedure:
Do your self
Precautions:
Do your self
Result:
Do your self
11
Experiment no.4
Aim:
To study and verify the Truth Table Encoder & Decoder.
Apparatus required:
Encoder & decoder trainer kit, patch cord, power supply, dc 5 vol. adaptor etc.
Encoder:
An encoder has 2n (or less) input lines and n output lines. The output lines generate the binary code for the
2n input variables. An example of an encoder is shown in Fig.1. The 8-to-3 Line Encoder or octal-to-binary
consists of eight inputs, one for each of the eight digits and three outputs that generate the corresponding
binary number. It is constructed with OR gates whose inputs can be determined from the truth table given
in Table-1. The low-order output bit Z is 1 if the input octal digit is odd. Output Y is 1 for octal digits 2, 3,
6 or 7. Output X is a 1 for octal digits 4, 5, 6 or 7. Note that D0 is not connected to any OR gate; the binary
output must be all 0’s in this case. This discrepancy can be resolved by providing one more output to
indicate the fact that all inputs are not 0’s.
Table 1
The encoder in Fig.1 assumes that only one input line can be equal to1 at any time; otherwise the circuit
has no meaning. Note that the circuit has eight inputs and could have 28 = 256 possible input combinations.
Only eight of these combinations have any meaning. The other inputs combinations are don’t care
conditions. Encoders of this type (Fig.1) are not available in IC packages, since they can be easily
constructed with OR gates. The type of encoder available in IC form is called a priority encoder. These
encoders establish an input priority to ensure that only the highest-priority input line is encoded. Thus, in
Table-1, if priority is given to an input with a higher subscript number over one with a lower subscript
number, then if both D2 and D5 are logic-1 simultaneously, the output will be 101 because D5. Of course, the
truth table of a priority encoder is different from the one in Table-1.
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Decoder:
A decoder is a digital function that produces a reverse operation from that of an encoder. It is a
combinational circuit that converts binary information from n input lines to a maximum of 2n unique
output lines. If the n-bit decoded information has unused or don’t-care combinations, the decoder
output will have less than 2n outputs.
The decoders presented here are called n-to-m line decoders where m ≤ 2n. Their purpose is to
generate the 2n (or less) minterms of n input variables. As an example, consider the 3-to-8-line decoder
circuit ofFig.2. The three inputs are decoded into eight outputs, each output representing one of the
minterms of the 3-input variables. The three inverters provide the complement of the inputs, and each
one of the eight AND gates generate one of the minterms. A particular application of this decoder
would be a binary-to-octal conversion. The input variables may represent a binary number, and the
outputs will then represent the eight digits in the octal number system. However, a 3-to-8-line decoder
can be used for decoding any 3-bit code to provide eight outputs, one for each element of the code.
The operation of the decoder may be further clarified from its input-output relationships, listed
inTable-2. Observe that the output variables are mutually exclusive because only one output can be
equal to 1 at any one time. The output line whose value is equal to 1 represents the minterm equivalent
of the binary number presently available in the input lines.
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Procedure encoder:
1. First make sure that toggle switches of input section are ‘Off’ (i.e. in downward direction).
2. Connect bits I0, I1, I2, I3, I4, I5, I6 and I7 of Input Section to the inputs D0, D1, D2, D3, D4, D5,
D6 and D7 of 8-to-3 Line Encoder respectively.
3. Connect outputs of the Encoder X, Y and Z to O1, O2 and O3 of the Output Section.
4. Connect +5 V adaptors on the DC socket provided on the trainer.
5. Switch ‘On’ the power supply.
6. Now using toggle switches of Input Section provide input to the Encoder as per its truth table
(Table
Procedure decoder:
1. First make sure that toggle switches of input section are ‘Off’ (i.e. in downward direction).
2. Connect bits I0, I1 and I2 of Input Section to the inputs X, Y and Z of 3-to-8 Line Decoder
respectively.
3. Connect outputs of the Decoder D0, D1, D2, D3, D4, D5, D6 and D7 to O1, O2, O3 O4, O5, and O6
of the Output Section.
4. Connect +5 V adaptor on the DC socket provided on the trainer.
5. Switch ‘On’ the power supply.
6. Now using toggle switches of Input Section provide input to the Decoder as per the truth table.
Precautions:
Do your self
Result:
Do your self
14
Experiment no.5
Aim:
To study the multiplexer & demultiplexer
Apparatus:
Mux, demux trainer kit, patch cord, power supply, main cord etc.
MUX
A mux is a special combinational circuit that is one of the most widely used standard ckt in digital
design. The mux is a logic circuit that comes out of several inputs to a single output. The input selected
is controlled by set of selected inputs. The fig. shows below a mux with 4 inputs and single output .For
selecting one out on 4 inputs for connection to the output, a set of m inputs is required. Where 2m = n
depends upon on the digital code applied at the selected input one out of n data sources is selected and
transmitted to a single output channel.
S.no
1
2
3
4
Select
lines
S1 S0
D0
D1
D2
D3
0
0
1
1
1
*
*
*
*
1
*
*
*
*
1
*
*
*
*
1
0
1
0
1
Data input
Output
Y
1
1
1
1
DEMUX
The opposite of the multiplexer circuit is called de-multiplexer. A de-multiplexer transmits data or
information from of a source to various sources. Thus in a de-multiplexer from the input line is
connected to one of the N output lines by providing appropriate address on the address line or
select lines. The fig. shows below, a de-mux with 2 for 1 to 4 (1:4). One of the application of mux
& de-mux is in communication system. In this case a number of transmitters are multiplexed at
the transmitting end. The multiplexed signals are transmitted over a single channel. At the
receiving end the channel is de-multiplexed and 2n receivers can be connected at the receiving end.
15
S.no
1
2
3
4
Procedure:
Do your self
Precautions:
Do your self
Result:
Do your self
Select
lines
S1 S0
0
0
1
1
0
1
0
1
Enable
Data outputs
E
D0
D1
D2
D3
0
0
0
0
1
*
*
*
*
1
*
*
*
*
1
*
*
*
*
1
16
Experiment no.6
Aim:
To study 4-bit binary Addition and Subtraction operation
Apparatus:
4-bit parallel adder trainer kit, patch cord, power supply, main cord etc.
Theory:
A key requirement of digital computers is the ability to use logical functions to perform arithmetic
operations. The basis of this is addition; if we can add two binary numbers, we can just as easily
subtract them, or get a little fancier and perform multiplication and division. How, then, do we add
two binary numbers? Adding binary numbers is a very simple task, and very similar to the longhand
addition of decimal numbers. As with decimal numbers, you start by adding the bits (digits) one
column, or place weight, at a time, from right to left. Unlike decimal addition, there is little to
memorize in the way of rules for the addition of binary bits:
0+0=0
1+0=1
0+1=1
1 + 1 = 10
1 + 1 + 1 = 11
The fourth and fifth lines indicates that we also have to account for two output bits when we add two
input bits- the sum and a possible carry Just as with decimal addition, when the sum in one column is
a two-bit (two-digit) number, the least significant figure is written as part of the total sum and the
most significant figure is carried to the next left column. Consider the following examples:
11 1 <--- Carry bits -----> 11
1001101 1001001 1000111
+ 0010010 + 0011001 + 0010110
----------- ------------ ----------. 1011111 1100010 1011101
Before going into the architecture of a binary adder/subtractor, it is necessary at this point to
understand how positive and negative numbers are represented in binary notation.
2’s Complement Representation
2's complement is the most popular method of signifying negative integers in computer science. It is
also an operation of negation (converting positive to negative numbers or vice versa) in computers
which represent negative numbers using 2's complement. Its use is ubiquitous today because it doesn't
require the addition and subtraction circuitry to examine the signs of the operands to determine
whether to add or subtract, making it both simpler to implement and capable of easily handling higher
precision arithmetic. As well, 0 has only a single representation, obviating the subtleties associated
with negative zero. In an n-bit binary number, the most significant bit is usually the 2n-1s place. But in
the 2's complement representation, its place value is negated; it becomes the -2n-1s place and is called
the sign bit. If the sign bit is zero, the value is non-negative, the same as an ordinary binary number.
But if the sign bit is 1, the value is negative. To negate a 2's complement number, invert all the bits
then add 1 to the result. If all bits are 1, the value is -1. If the sign bit is 1 but the rest of the bits are 0,
the value is the most negative number, -2n-1 for an n-bit number. The absolute value of the most
negative number cannot be represented with the same number of bits. A two's complement 8-bit
binary numeral can represent every integer in the range -128 to +127. If the sign bit is 0, then the
largest value that can be stored in the remaining seven bits is 27 - 1, or 127. Using 2's complement to
17
represent negative numbers allows only one representation of zero, and to have effective addition and
subtraction while still having the most significant bit as the sign bit.
Calculating 2's complement
In finding the 2's complement of a binary number, the bits are inverted, or "flipped", by using the
bitwise NOT operation; the value of 1 is then added to the resulting value. Bit overflow is ignored,
which is the normal case with zero. For example, beginning with the signed 8-bit binary representation
of the decimal value 5:
0000 0101 (5)
The first bit is 0, so the value represented is indeed a positive 5. To convert to -5 in 2's complement
notation, the bits are inverted; 0 becomes 1, and 1 becomes 0: 1111 1010
At this point, the numeral is the 1's complement of the decimal value 5. To obtain the 2's complement,
1 is added to the result, giving: 1111 1011 (-5)
The result is a signed binary numeral representing the decimal value -5 in 2's complement form. The
most significant bit is 1, so the value is negative. The 2's complement of a negative number is the
corresponding positive value. For example, inverting the bits of -5 (above) gives:
0000 0100 And adding one gives the final value: 0000 0101 (5)
The decimal value of a 2's complement binary number is calculated by taking the value of the most
significant bit, where the value is negative when the bit is one, and adding to it the values for each
power of two where there is a one. Example:
1111 1011 (-5) = -128 + 64 + 32 + 16 + 8 + 0 + 2 + 1 = (-2^7 + 2^6 + ...) = -5.
Note that the 2's complement of zero is zero: inverting gives all ones, and adding one changes the ones
back to zeros (the overflow is ignored). Also the 2's complement of the most negative number
representable (e.g. a one as the sign bit and all other bits zero) is itself. This happens because the most
negative number's "positive counterpart" is occupied by "0", which gets classed as a positive number
in this argument. Hence, there appears to be an 'extra' negative number. A more formal definition of
2's complement negative number (denoted by N* in this example) is derived from the equation N * =
2n - N, where N is the corresponding positive number and n is the number of bits in the
representation. For example, to find the 4 bit representation of -5:
N (base 10) = 5, therefore N (base 2) = 0101
n=4
Hence,
N * = 2n - N = [24] base2 - 0101
= 10000 - 0101 = 1011
You can also think of the equation as being entirely in base 10, converting to base 2 at the end, e.g.:
N * = 2n - N = 24 - 5
= [11] base10
= [1011] base2
Obviously, "N* ... = 11" isn't strictly true but as long as you interpret the equals sign as "is
represented by", it is perfectly acceptable to think of 2's complements in this fashion.
2’s Complement Addition
Addition of 2's complement of numbers requires no special processing if the operands have opposite
signs: the sign of the result is determined automatically. For example, adding 15 and -5:
11111 111 (carry)
0000 1111 (15)
+ 1111 1011 (-5)
===========
0000 1010 (10)
18
This process depends upon restricting to 8 bits of precision; a carry to the (nonexistent) 9th most
significant bit is ignored, resulting in the arithmetically correct result of 10. The last two bits of the
carry row (reading right-to-left) contain vital information: whether the calculation resulted in an
arithmetic overflow, a number too large for the binary system to represent (in this case greater than 8
bits). An overflow condition exists when a carry (an extra 1) is generated into but not out of the far left
sign bit, or out of but not into the sign bit. As mentioned above, the sign bit is the leftmost bit of the
result. In other terms, if the last two carry bits (the ones on the far left of the top row in these
examples) are both 1's or 0's, the result is valid; if the last two carry bits are "1 0" or "0 1", a sign
overflow has occurred. Conveniently, an X-OR operation on these two bits can quickly determine if an
overflow condition exists. As an example, consider the 4-bit addition of 7 and 3:
0111 (carry)
0111 (7)
+ 0011 (3)
=============
1010 (-6) invalid!
In this case, the far left two (MSB) carry bits are "01", which means there was a two's complement
addition overflow. That is, ten is outside the permitted range of -8 to 7.
2’s Complement Subtraction
Computers usually use the method of complements to implement subtraction. But although using
complements for subtraction is related to using complements for representing signed numbers, they
are independent; direct subtraction works with 2's complement numbers as well. Like addition, the
advantage of using 2's complement is the elimination of examining the signs of the operators to
determine if addition or subtraction is needed. For example, subtracting -5 from 15 is really adding 5
to 15, but this is hidden by the 2's complement representation:
1111 0000 (borrow)
0000 1111 (15)
- 1111 1011 (-5)
===========
0001 0100 (20)
Overflow is detected the same way as for addition, by examining the two leftmost (most significant)
bits for borrow; overflow occurred if they are different. Another example is a subtraction operation
where the result is negative: 15 - 35 = -20:
1110 0000 (borrow)
0000 1111 (15)
- 0010 0011(35)
===========
1110 1100 (-20)
19
S.no
-----
S0
Input
S1 S2 S3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Output
Sum Cout
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Procedure:
1. Connect the +5V adaptor at the indicated position but do not switch on the Power Supply initially.
2. Connect A0-A3 and B0-B3 from “4-Bit Binary Adder” block to A0-A3 and B0-B3 of the “Input
Section 1” and “Input Section 2” respectively.
3. Also connect S0-S3 from “4-Bit Binary Adder” block to S0-S3 at the “Output Section”.
4. Now connect Cout1 from “4-Bit Binary Adder” block to S4 at the “Output Section” to observe the
carry or borrow at Cout1.
5. Now connect the pin from “4-Bit Binary Adder” block to pin of “Input Section 2”.
6. For Addition Operation, keep the switch to logic ‘0’ level. Note: In case of addition if both the
operands are positive numbers, all Bn bits pass unchanged through the controlled inverters and
thus providing the correct sum output.
7. Now switch on the Power Supply.
20
8. Enter any data (with the help of toggle switches) whose sum is to be calculated, glowing of
corresponding LEDs will indicate whether the entered data is “1” or “0”
Note:
In case of generation of a carry, the LED at S4 will glow. If we want to enter two negative inputs for
addition, we will first calculate their 2’s complement and then enter the negative numbers in this 2’s
complement form only. The output will display the result of such addition in 2’s complement form
only. In this case, the LED at carry out S4 will glow as the sum of actual numbers is negative.
9. Observe the result at the output section.
10. Verify the result by performing the operation manually on paper by yourself.
11. Now switch off the Power Supply.
12. For Subtraction of Bn from An, keep “ ” switch at logic ‘1’ level
Note: By doing this, we are negating the Bn bits in 2’s complement form and then finally adding it to
An to get the desired result which is equal to [(An-Bn) = Sn] when result is negative, Sn is in 2’s
complement form.
13. Now switch on the Power Supply.
14. Enter any data (with the help of toggle switches) whose difference is to be calculated, glowing of
corresponding LEDs will indicate whether the entered data is “1” or “0”.
15. Observe the result at the output section. Glowing of LED will indicate output “1” and LED OFF
will indicate output “0”, read the whole output from S4-S0 for knowing the result.
16. The LED for Cout1/S4 will glow if any borrow is generated.
17. Verify the result by performing the operation manually on paper by yourself.
18. Now switch off the Power Supply.
Precautions:
Do your self
Result:
Do your self
21
Experiment no.7
Aim:
To verify operation of half adder and full adder.
Apparatus:Digital trainer kit, bread board, connecting leads, main cord, IC (7408, 7486, 7432)
Half adder:Half adder is a logic circuit that accepts two inputs (binary digits) on its inputs and produces the
binary digits on its output i.e. a sum bit & carry bit. Half adder adds two one-bit binary numbers.
sum, S  A  B
carry, C  A  B
Truth table for half adder
Inputs
Output
A
B
Sum Car
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Full adder:Full adder is a logic circuit that accepts three inputs on and produces the binary digits (output) on its
output i.e. a sum bit & carry bit. Full adders add three one-bit binary numbers and carry inputs from
previous stage.
sum, S  A  B  CI
carry, Cout  AB  ( A  B)CI
Truth table for full adder
22
A
0
0
0
0
1
1
1
1
Inputs
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Outputs
Sum
Car
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
Procedure:
1.
2.
3.
4.
Make the circuit as per ckt. diagram
Mount IC of any gate on breadboard.
Connect pin no. 7 of IC of any gate to GND and pin no. 14 to Vcc (+5V).
Connect pin no. 1 & 2 of IC to logical input states and connect a LED and a resistance of
appropriate value b\w pin no. 3 & GND for output.
5. For initialize experiment according to truth table, input terminal of IC connects to ground for ‘0’
(LOW) state input, and to Vcc (+5V) for ‘1’ (HIGH) state input.
Precaution:
1.
2.
3.
4.
Insert Ic on the bread board with out damaging the pin.
Take care while supplying the voltage to the Ic.
Give Vcc & Gnd to all Ics.
Verify the truth table as shown.
Result:
Do your self
23
Experiment no.8
Aim:
To study the synchronous up counter
Apparatus
Counter trainer kit, patch cord, power supply, dc 5 vol. adaptor etc.
Theory:
Observe the diagram of 4-bit synchronous binary up counter as shown in the figure below. The flipflop in the lowest order position is complemented with every pulse so J and K inputs must be
maintained at logic 1. A flip flop in any other position is complemented with a pulse, provided all the
bits in lower order mode are equal to1, because the lower order bits (when all ones) will change to 0s
on next clock pulse. The clock terminal CP of all flip-flops is connected to a common clock pulse
source CLK. The first stage Q0 has its J and K inputs high or 1. The other J and K inputs are equal to
1 if all previous low order bits are equal to 1 and the count is enabled. The chain of AND gates
generate the required logic for the J and K inputs in each stage. In the figure, MSD is master set input
which when connected to logic 0, sets the output of flip flops to logic 1. MCD is master reset input
which when connected to logic 0, resets or clears output.Q3, Q2, Q1, Q0 are outputs of flip flops where
Q0 is LSB and Q3 is MSB. The clock pulse CLK triggers the flip flops on negative edge i.e. +5 V to 0 V
(or 1→0) transitions.
Synchronous Counters
24
Procedure:
1. Connect MSD input of 4-bit synchronous binary up counter to ‘D0’. Set it to logic 1 position.
2. Connect MCD input of the 4–bit synchronous binary up counter to ‘D1’. Set it to logic 0 levels.
3. Connect CLK of 4–bit synchronous binary up counter to ‘A’ of CLK IN of input section. Set the
corresponding switch to ‘A’ position.
4. Connect Q0-Q3 of 4 –bit synchronous binary up counter to Q0-Q3 of output section, respectively.
5. Connect Logic High of 4 –bit synchronous binary up counter to Logic High/Vcc of input section.
6. Set it to ‘On’ level to switch ON the circuit.
7. Give logic 1 to 0 transition at CLK IN (i.e. toggle the switch to ‘/A’ from ‘A’).
8. Observe the output of all the four flip-flops on the corresponding Q0-Q3 LED displays on the
output section. It will be 0000 i.e. all the LEDs will be off.
9. Now toggle MCD to logic 1 position.
10. Give logic 1 to 0 transition at CLK IN.
11. Observe the output of all the four flip flops on the corresponding Q0-Q3 LED display on the
output section. It will still be 0001.
12. Repeat steps 10-11 to verify the truth table ‘5’ until last state 1111 appear on the output section i.e.
all of the four LEDs are glowing.
Precautions:
Do your self
Result:
Do your self
25
Experiment no.9
Aim:
To study the 4-bit asynchronous (up/down counter)
Apparatus
Counter trainer kit, patch cord, power supply, dc 5 vol. adaptor etc.
Theory:
Below is the diagram of a 4-bit asynchronous up counter. The J and K inputs of all the flip-flops are
tied to '1', so that every time they are clocked, they will toggle between the states. Also, the output of
each flip-flop in the counter is connected to clock CP of the next flip-flop. As a result, the succeeding
flip-flop toggles between '1' and '0' at only half the frequency as the flip-flop before it. Figure 3 Thus,
in Figure 3, the last flip-flop will only toggle after the first flip-flop has already toggled 8 times. This
type of binary counter is known as a 'serial', 'ripple', or 'asynchronous' counter. Usually, all the clear
inputs CD are connected together, so that a single pulse can clear all the flip-flops before counting
starts. The CD input of all flip-flops is set to logic 1 during count enabling. Similarly, the SD input is
set to logic 1 always. An asynchronous counter has a serious drawback - its speed is limited by the
cumulative propagation times of the cascaded flip-flops. A counter that has N flip-flops, each of which
has a propagation time t, must therefore wait for duration equal to N x t before it can undergo another
transition clocking. A better counter, therefore, is one whose flip-flops are clocked at the same time i.e.
synchronous counter which was explained earlier. Similar to an asynchronous up counter is the
operation of synchronous down counter as shown in figure 4. The only difference is that the down
counter, unlike up counter, carries input from Q’ (not Q) or the complemented output. Besides this,
the down counter has a preset control to preset the counter to 1111 to start the downward count.
The name 'asynchronous' comes from the fact that this counter's flip-flops are not being clocked at the
same time. Practically such counters are of two types
1. Up counter – in which there is an increase in the count value (i.e. from decimal 0 to 2n -1 where n
is equal to number of flip flops used).
3. Down counter - in which there is a decrease in the count value (i.e. from decimal 2n -1 to 0
where n is equal to number of flip flops used).
26
27
Procedure:
Up Counter:
1. Connect the normal outputs Q0-Q2 of the flip-flops to CP inputs of next flip-flops.
2. Connect MSD to D0. Set it to logic 1 position.
3. Connect MCD to D1. Set it to logic 0 positions.
4. Connect the normal output Q0-Q3 of the flip-flops to Q0-Q3 of the output section as well.
5. Connect CLK input of 4-bit asynchronous binary up / down counter to socket ‘A’ of CLK IN. Set it
to logic 1 position or upwards.
6. Connect Logic High of 4–bit asynchronous binary up / down counter to Logic High/Vcc of input
section.
7. Set it to ‘On’ level to switch ON the circuit.
8. Observe the output of all the four flip flops on the corresponding Q0-Q3 LED displays on the
output section. It will be 0000 i.e. all the LEDs will be off.
9. Give logic 1 to 0 transition at CLK IN (i.e. toggle the switch to ‘/A’ from ‘A’).
10. Now again observe the outputs of flip flops on the corresponding Q0-Q3 LED displays in the
output section. It will still be 0000.
11. Now toggle D1 i.e. MCD to logic 1 position.
12. Give logic 1 to 0 transition at CLK IN.
13. Observe the outputs on LED display. It will be 0001.
14. Give logic 1 to 0 transitions at the CLK IN input to verify the truth table ‘6’ for asynchronous
binary up counter and observe output until last state 1111 appears on the output section i.e. all of
the four LEDs are glowing.
Down Counter:
1. Connect the complemented output Q’ of the flip-flops to CP input of next flip-flop.
2. Connect MSD to D0. Set it to logic 0 positions.
3. Connect MCD’ to ‘D1’. Set it to logic1 position.
4. Repeat steps 4-7 from up counter.
5. Observe the output of all the four flip flops on the corresponding Q0-Q3 LED displays on the
output section. It will be 1111 i.e. all the LEDs will be on.
6. Now give logic 1 to 0 transition at CLK IN input (by moving the toggle switch from ‘A’ to ‘/A’.
There will be no change.
7. Now toggle D0 i.e. MSD to logic 1 position.
8. Now again give logic 1 to 0 transition at CLK IN input by moving the toggle switch
9. Observe the outputs on LED display. It will be 1110.
10. Give logic 1 to 0 transitions at the CLK IN input to verify the truth table ‘7’ for asynchronous
binary down counter and observe output until last state 0000 appears on the output section i.e. all
of the four LEDs are off.
Precautions:
Do your self
Result:
Do your self
28
Experiment no.10
Aim:
To realize basic gate using universal gate (NAND, NOR)
Apparatus required:Digital trainer kit, bread board, Ic 7400, 7402, patch cord, power supply, main cord etc.
Theory:A universal gate is a gate which have two or more input only and only single output. The universal
gates are two, namely NAND and NOR. We can build all the basic gates by using universal gate. The
NAND gate is a contraction of NOT-AND gates, similarly NOR gate is a contraction of NOT-OR gates.
NOT gate using NAND gate.
Y  A. A  A
0
YA
1
1
0
A
AND gate using NAND gate.
Y  AB  AB
OR gate using NAND gate.
A
0
0
1
1
B
0
1
0
1
Y  A.B
0
0
0
1
Y  A.B  A  B  A  B
A
0
0
1
1
B
0
1
0
1
Y  A B
0
1
1
1
29
NOT gate using NOR gate.
Y  A A  A
0
YA
1
1
0
A
AND gate using NOR gate.
Y  A  B  A.B  AB
OR gate using NOR gate.
A
0
0
1
1
B
0
1
0
1
Y  A.B
0
0
0
1
Y  A B  A B
A
0
0
1
1
B Y  A B
0
0
1
1
0
1
1
1
Procedure:
1.
2.
3.
4.
Mount IC of NOR and NAND gate on breadboard.
Connect pin no. 7 of IC of any gate to GND and pin no. 14 to Vcc (+5V).
Make the connection as per ckt diagram as shown in fig.
For initialize experiment according to truth table, input terminal of IC connects to ground for ‘0’
(LOW) state input, and to Vcc (+5V) for ‘1’ (HIGH) state input.
Precaution:
Do your self
Result:
Do your self
30
Experiment no.11
Aim: - To verify the operation of BCD – 7 segment decoder and drive a 7 segment display
Apparatus: - Bread board, 7 segment driver (LT 542), driver ic 7447, connecting wire, power supply.
Theory: - Seven segments is the most popular display device used in digital system. For displaying
data using this device, the data has to be converted from BCD to 7 segment code. No. MSI ICs are
available for performing this function. The decoder/driver circuit has four input lines for BCD data &
7 output lines to drive a 7 segment display. Output terminals ‘a’ to ‘g’ of the decoder/driver are to be
connected to ‘a’ to ‘g’ terminals of the display respectively. In the driver ic the function of LT, RBI, BI
are given below.
LT: this is used to check the segment of LED. If it connected to logic ‘0’ level, all the segment of the
display connected to the decoder will be ON. For normal decoding operation, this terminal is to be
connected to logic ‘1’ level.
RBI: It is to be connected to logic ‘1’ level for normal decoding operation. If it is connected to ‘0’ level.
The segment output will generate data for 7-segment decoding for all BCD inputs except ‘0’.
Whenever the BCD inputs correspond to ‘0’ the 7-segment display switches off. This is used for
blanking out leading ‘0s’ in multi-digit display.
BI: If it is connected to logic ‘0’ level, the display is switched off irrespectively of BCD inputs. This is
used for conserving power in multiplexed displays.
Procedure:
1. Mount the IC on the bread board
2. Connect the pins ‘a’ to ‘g’ of IC 7447 to pins ‘a’ to ‘g’ of LT 452
3. Connect the power supply to both component (IC & decoder)
4. Give logic high voltage at pin no. 16 of ic 7447 & pin no. 8 of decoder LT 542.
5. Give logic high voltage at pins LT, BI, RBI of IC 7447.
6. Change inputs ABCD of the decoder IC from ‘0’ to ‘9’ and observe the output in the seven
segments.
Precaution:
Do your self
Result:
Do your self
31
Experiment no.12
Aim:
To study of digital comparator
Apparatus:
Bread board, digital trainer kit, patch cord, connecting wire, power supply and Ic 7485 etc.
Theory:
Comparator can be design for comparing multiple numbers. Fig. shows a block diagram of 4-bit
comparator. It receives two 4-bit numbers A & B as input and output are A>B, A=B, and A<B.
depending upon relative magnitude of the two 4-bit numbers of the output will be high.
However 4-bit comparator is available in Ic 7485, which can compare straight binary nature BCD
codes. These Ic can be cascade to compare words of greater length without external gates.
Input Input Input Input Input Input Input Input Output Output Output
A0
A1
A2
A3
B0
B1
B2
B3
A>B
A=B
A<B
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
Procedure:
1.
2.
3.
4.
Mount the Ic on the bread board
Connect the pin no. 16 of Ic to the +5 vol Vcc
Connect pin no. 8 of Ic to the ground.
Check the given inputs A3=B3, A2=B2, A1=B1 and A0=B0 and any of the connections as A3>B3,
A2>B2, A1>B1 and A0>B0
5. See the output through LED across pin no. 5, 6 and 7
Precaution:
1. Voltage should not be more than 5 vol.
2. Never interchange the connection of Vcc and ground.
3. Never connect the input to the output side.
Result:
Do your self
32
Experiment no.13
Aim:-To minimize given Boolean function and implement it using universal gate.
Apparatus:-digital trainer kit, bread board, Ic 7400, 7402, patch cord, main cord, power supply etc.
Theory:f ( A, B, C , D )  A BC D  A BC D  A BC D  A BCD  ABC D  ABC D  ABC D  ABCD  A BC D  ABC D  A BCD  ABCD
 A BC ( D  D )  A BC ( D  D )  ABC ( D  D )  ABC ( D  D )  AC D ( B  B )  ACD( B  B )
 A BC  A BC  ABC  ABC  AC D  ACD
 A B (C  C )  AB (C  C )  AD(C  C )
 A B  AB  AD
 A( B  B )  AD
 A  AD
 ( A  A)( A  D )
 A D
Using NAND gate
Y  AD  A  D  A  D
Y  A D
Using NOR gate
A  D  A.D  A.D
Y  A.D  A  D  A  D
Y  A D
A
D
0
0
1
1
0
1
0
1
Truth table
D
Y  A D
A
1
1
0
0
0
1
0
1
1
1
0
1
Procedure:
1.
2.
3.
4.
Mount the Ic on breadboard.
Connect pin no. 7 of IC of any gate to GND and pin no. 14 to Vcc (+5V).
Make the connection as per ckt diagram as shown in fig.
For initialize experiment according to truth table, input terminal of IC connects to ground for ‘0’
(LOW) state input, and to Vcc (+5V) for ‘1’ (HIGH) state input.
33
Precaution:
4. Voltage should not be more than 5 vol.
5. Never interchange the connection of Vcc and ground.
6. Never connect the input to the output side.
Result:
Do your self
34
Experiment no.14
Aim:To minimize given Boolean function using K-map
Apparatus:Digital trainer kit, Ic 7404, 7408, power supply, main cord, bread board, patch cord, etc.
Theory:The given function is:F (A, B, C, D) =∑ m (0, 2, 8, 10,)
The given function is written in two ways also which are following.
F (A, B, C, D) = m0+m1+m2+m3
B
0
0
1
1
D
0
1
0
1
Y  B.D
1
0
0
0
Procedure:
5. Mount IC of any gate on breadboard.
6. Connect pin no. 7 of IC of any gate to GND and pin no. 14 to Vcc (+5V).
7. Connect pin no. 1 & 2 of IC to logical input states and connect a LED and a resistance of
appropriate value b\w pin no. 3 & GND for output.
8. For initialize experiment according to truth table, input terminal of IC connects to ground for ‘0’
(LOW) state input, and to Vcc (+5V) for ‘1’ (HIGH) state input.
Precautions:
Do your self
Result:
Do your self
35
Experiment no.15
Aim:
To study ALU for performing logic operations
Apparatus required:
ALU trainer kit, patch cord, power supply, main cord.
Theory:
The basic blocks of a computer are central processing unit (CPU), memory unit, and input/output
unit. CPU of the computer is basically the same as the brain of a human being. It contains all the
registers, control unit and the arithmetic logic unit (ALU). The ALU is the most important and
fundamental building block of the central processing unit (CPU) of a computer, and even the simplest
microprocessors contain one for purposes such as maintaining timers. The processors found inside
modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex
ALUs in which a single component may contain a number of ALUs. In computing, an arithmetic logic
unit (ALU) is a digital circuit that performs arithmetic and logical operations. It is a multioperational, combinational-logic function that performs 2n logic and arithmetic micro-operations each,
on a pair of n-bit operands. The specific operation that is performed by an ALU is determined by a
specific binary code applied to its function-select inputs. These combinations of binary codes are
interpreted within the ALU and the final output of the operation is obtained at output of ALU. Amore
simpler diagrammatic representation of ALU is given below. Here, A and B are the inputs (or
operands) to the ALU R is the output or result F is the code or instruction (or op-code) from the
Control Unit D is output status; it indicates cases such as carry-in, carry-out, overflow, division-byzero an ALU can be divided up into three circuits: the arithmetic circuit, the logic circuit and the shift
circuit.
36
Objective:
Performing logic ‘NOT’ operation
1. Connect sockets
of ‘Input Section’ to sockets
of ‘Arithmetic and Logic Unit’
section respectively.
2. Connect sockets
of ‘Input Section’ to sockets
of ‘Arithmetic and Logic Unit’
section respectively.
3. Connect sockets ‘S0–S3’ of ‘Function and Mode Select Input’ section to sockets ‘S0- S3’ of
‘Arithmetic and Logic Unit’ section respectively.
4. Connect socket ‘M’ of ‘Function and Mode Select Input’ section to socket ‘M’ of ‘Arithmetic and
Logic Unit’ section.
5. Connect sockets
of ‘Output Section’ to sockets
of ‘Arithmetic and Logic Unit’
section respectively.
6. Now give any combination of inputs at sockets
and
of Input section.
7. Toggle the mode control input ‘M’ to logic ‘1’ level for logic operation mode.
8. Now toggle all the function select inputs ‘S0-S3’ to logic ‘0’ level.
9. Switch on the supply.
37
10. You will observe that the output is logical 1’s complement of input at
is logical ‘NOT’ function of
(refer to step1 of table 1).
11. Switch off the power supply.
Hence our output
Result:
Output Fn =
Objective:
Performing logic ‘AND’ operation
1. Repeat steps 1-7 of experiment 1.
2. Now toggle the function select inputs ‘S0’, ‘S1’ and ‘S3’ to logic ‘1’ level.
3. Now toggle the function select input ‘S2’ to logic ‘0’ level.
4. Switch on the supply.
5. You will observe that the output is logical ‘AND’ function of inputs at
(refer to step 12 of table 1).
6. Switch off the power supply.
and
Result:
Output Fn = An.Bn
Objective:
Performing logic ‘OR’ operation
1. Repeat steps 1-7 of experiment 1.
2. Now toggle the function select inputs ‘S1’, ‘S2’ and ‘S3’ to logic ‘1’ level.
3. Now toggle the function select input ‘S0’ to logic ‘0’ level.
4. Switch on the supply.
5. You will observe that the output is logical ‘OR’ function of inputs at
(refer to step 15 of table 1).
6. Switch off the power supply.
and
Result:
Output Fn = An + Bn.
Objective:
Performing logic ‘NOR’ operation
1. Repeat steps 1-7 of experiment 1.
2. Now toggle the function select inputs ‘S1’, ‘S2’ and ‘S3’ to logic ‘0’ level.
3. Now toggle the function select input ‘S0’ to logic ‘1’ level.
4. Switch on the supply.
5. You will observe that the output neither is logical ‘NOR’ function of inputs at
(refer to step 2 of table 1).
6. Switch off the power supply.
Result:
Output Fn =
Objective:
Performing logic ‘NAND’ operation
1. Repeat steps 1-7 of experiment 1.
2. Now toggle the function select inputs ‘S0’, ‘S1’ and ‘S3’ to logic ‘0’ level.
and
38
3. Now toggle the function select input ‘S2’ to logic ‘1’ level.
4. Switch on the supply.
5. You will observe that the output is logical ‘NAND’ function of inputs at
(refer to step 5 of table 1).
6. Switch off the power supply.
and
Result:
Output Fn =
Objective:
Performing logic ‘Ex-OR’ operation
1. Repeat steps 1-7 of experiment 1.
2. Now toggle the function select inputs ‘S1’ and ‘S2’ to logic ‘1’ level.
3. Now toggle the function select inputs ‘S0’ and ‘S3’ to logic ‘0’ level.
4. Switch on the supply.
5. You will observe that the output is logical ‘Ex-OR’ function of inputs at
(refer to step 7 of table 1).
6. Switch off the power supply.
and
Result:
Output Fn =
Objective:
Performing logic ‘Ex-NOR’ operation
1. Repeat steps 1-7 of experiment 1.
2. Now toggle the function select inputs ‘S1’ and ‘S2’ to logic ‘0’ level.
3. Now toggle the function select inputs ‘S0’ and ‘S3’ to logic ‘1’ level.
4. Switch on the supply.
5. You will observe that the output is logical ‘Ex-NOR’ function of inputs at
(refer to step10 of table 1).
6. Switch off the power supply.
and
Result:
Output Fn =
Objective:
Performing bit transfer operation
1. Repeat steps 1-7 of experiment 1.
2. Now give any combination of inputs at sockets
and
of Input section.
3. Now toggle all the function select inputs from ‘S0’ to ‘S3’ to logic ‘1’ level.
4. Switch on the supply.
5. You will observe that the output is equal to inputs at
(refer to step16 of table 1). Hence,
all the bits at
have been transferred to the output.
6. Switch off the power supply.
Result:
Output Fn = An.
Objective:
39
Solving various equations
1. Repeat steps 1-5 of experiment 1.
2. Now give any combination of inputs at sockets
and
of Input section.
3. Toggle the Mode Control Input ‘M’ to logic ‘1’ level for logic operation mode.
Solving
1. Toggle the function select inputs ‘S0’, ‘S2’ and ‘S3’ to logic ‘0’ level.
2. Toggle the function select input ‘S1’ to logic ‘1’ level.
3. Switch on the supply.
4. You will observe that the output is equal to
(refer to step 3 of table 1).
5. Switch off the power supply.
Result:
Output Fn =
Solving
1. Now toggle the function select inputs ‘S0’, ‘S1’ and ‘S2’ to logic ‘1’ level.
2. Now toggle the function select input ‘S3’ to logic ‘0’ level.
3. Switch on the supply. You will observe that the output is equal to
(refer to step 8 of table 1).
4. Switch off the power supply.
Result:
Output Fn =
Solving
1. Now toggle the function select inputs ‘S0’, ‘S1’ and ‘S2’ to logic ‘0’ level.
2. Now toggle the function select input ‘S3’ to logic ‘1’ level.
3. Switch on the supply. You will observe that the output is equal to
4. Switch off the power supply.
(refer to step 9 of table 1).
Result:
Output Fn =
Solving
1. Now toggle the function select inputs ‘S0’, ‘S2’ and ‘S3’ to logic ‘1’ level.
2. Now toggle the function select input ‘S1’ to logic ‘0’ level.
3. Switch on the supply. You will observe that the output is equal to
4. Switch off the power supply.
(refer to step 14 of table 1).
Result:
Output Fn =
Objective:
Giving logic ‘0’ or ‘1’ at the output
1. Repeat steps 1-5 of experiment 1.
2. Now give any combination of inputs at sockets
and
of Input section.
4. Toggle the Mode Control Input ‘M’ to logic ‘1’ level for logic operation mode.
5. Toggle the function select inputs ‘S0’ and ‘S1’ to logic ‘1’ level.
40
6. Toggle the function select inputs ‘S2’ and ‘S3’ to logic ‘0’ level.
7. Switch on the supply.
8. You will observe that the output Fn will be equal to Logical 0 or 0000(refer to step 4 of table 1).
9. Switch off the power supply.
10. Output will be Fn = logical 0 = 0000.
11. Toggle the function select inputs ‘S0’ and ‘S1’ to logic ‘0’ level.
12. Toggle the function select inputs ‘S2’ and ‘S3’ to logic ‘1’ level.
13. Switch on the supply.
14. You will observe that the output Fn will be equal to Logical 1 or 1111 (refer to step 13 of table 1).
15. Switch off the power supply.
Result:
Output Fn = logical 1 = 1111
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Experiment no.16
Aim:
To study ALU for performing Arithmetic operations
Apparatus required:
ALU trainer kit, patch cord, power supply, main cord.
Theory:
The basic blocks of a computer are central processing unit (CPU), memory unit, and input/output
unit. CPU of the computer is basically the same as the brain of a human being. It contains all the
registers, control unit and the arithmetic logic unit (ALU). The ALU is the most important and
fundamental building block of the central processing unit (CPU) of a computer, and even the simplest
microprocessors contain one for purposes such as maintaining timers. The processors found inside
modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex
ALUs in which a single component may contain a number of ALUs. In computing, an arithmetic logic
unit (ALU) is a digital circuit that performs arithmetic and logical operations. It is a multioperational, combinational-logic function that performs 2n logic and arithmetic micro-operations each,
on a pair of n-bit operands. The specific operation that is performed by an ALU is determined by a
specific binary code applied to its function-select inputs. These combinations of binary codes are
interpreted within the ALU and the final output of the operation is obtained at output of ALU. Amore
simpler diagrammatic representation of ALU is given below. Here, A and B are the inputs (or
operands) to the ALU R is the output or result F is the code or instruction (or op-code) from the
Control Unit D is output status; it indicates cases such as carry-in, carry-out, overflow, division-byzero an ALU can be divided up into three circuits: the arithmetic circuit, the logic circuit and the shift
circuit.
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Objective:
To study ALU for performing binary addition operation
Procedure:
1. Connect sockets
of ‘Input Section’ to sockets
of ‘Arithmetic and Logic Unit’
section respectively.
2. Connect socket ‘Cn’ of ‘Input Section’ to socket ‘Cn’ of ‘Arithmetic and Logic Unit’ section.
3. Connect sockets
of ‘Input Section’ to sockets
of ‘Arithmetic and Logic Unit’
section respectively.
4. Connect sockets ‘S0–S3’ of ‘Function and Mode Select Input’ section to sockets ‘S0-S3’ of
‘Arithmetic and Logic Unit’ section respectively.
5. Connect socket ‘M’ of ‘Function and Mode Select Input’ section to socket ‘M’ of ‘Arithmetic and
Logic Unit’ section.
6. Connect sockets
of ‘Output Section’ to sockets
of ‘Arithmetic and Logic Unit’
section respectively.
43
7. Connect sockets ‘Cn+4’, ‘A=B’,
and
of ‘Arithmetic and Logic Unit’ section.
of ‘Output Section’ to sockets ‘Cn+4’, ‘A=B’,
and
8. Now give any combination of inputs at sockets
and
of Input section.
9. Toggle the mode control input ‘M’ to logic ‘0’ level for arithmetic operation mode.
10. Now toggle ‘Cn’ to logic 1 level.
11. Toggle the function select inputs ‘S0’ and ‘S3’ to logic ‘1’ level.
12. Now toggle the function select inputs ‘S1’ and ‘S2’ to logic ‘0’ level.
13. Switch on the supply.
14. You will observe that the output is equal to binary addition of the inputs An and Bn (refer to step
no. 10 of table 2).
Result:
Output Fn =A plus B.
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 0 level.
2. Switch on the supply.
3. You will observe that the output is equal to output obtained in step 14 (of this procedure)
incremented by 1.
Result:
Output Fn = A plus B plus 1.
Switch off the power supply.
Objective:
Performing binary subtraction operation
1. Repeat all steps from 1 to 7 of experiment 1
2.
3.
4.
5.
6.
7.
8.
Now give any combination of inputs at sockets
and
of Input section.
Toggle the mode control input ‘M’ to logic ‘0’ level for arithmetic operation mode.
Now toggle ‘Cn’ to logic 0 level.
Toggle the function select inputs ‘S0’ and ‘S3’ to logic ‘0’ level.
Now toggle the function select inputs ‘S1’ and ‘S2’ to logic ‘1’ level.
Switch on the supply.
You will observe that the output is equal to binary subtraction of the inputs An and Bn (refer to
step 7 of table 2).
Result:
Output Fn =A minus B.
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 1 level.
2. Switch on the supply.
3. You will observe that the output is equal to output obtained in step 8 (of this procedure)
decremented by 1.
Result:
Output Fn = A minus B minus 1.
Objective:
Performing increment and decrement operation
1. Repeat all steps from 1 to 7 of experiment 1.
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9. Now give any combination of inputs at sockets
and
of Input section.
10. Toggle the mode control input ‘M’ to logic ‘0’ level for arithmetic operation mode.
11. Now toggle ‘Cn’ to logic 0 level.
12. Toggle all the function select inputs from ‘S0’ to ‘S3’ to logic ‘0’ level.
13. Switch on the supply.
14. You will observe that the output is equal to input An incremented by 1 (refer to step 1 of table 2).
Result:
Output Fn = A plus 1.
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 1 level.
2. Switch on the supply.
3. You will observe that the output is equal to input An, which means the input is simply transferred
to the output.
Result:
Output Fn = A.
Switch off the power supply.
2.
3.
4.
5.
Now toggle ‘Cn’ to logic 1 level.
Toggle all the function select inputs from ‘S0’ to ‘S3’ to logic ‘1’ level.
Switch on the supply.
You will observe that the output is equal to input An decremented by 1 (refer to step 16 of table 1).
Result:
Output Fn = A minus 1.
Switch off the power supply.
4.
5.
6.
7.
Now toggle ‘Cn’ to logic 0 level.
Toggle all the function select inputs from ‘S0’ to ‘S3’ to logic ‘1’ level.
Switch on the supply.
You will observe that the output is equal to input An, which means the input is simply transferred
to the output.
Result:
Output Fn = A.
Objective:
Performing logical OR-increment operation
1. Repeat all steps from 1 to 7 of experiment 2.
2.
3.
4.
5.
6.
7.
8.
Now give any combination of inputs at sockets
and
of Input section.
Toggle the mode control input ‘M’ to logic ‘0’ level for arithmetic operation mode.
Now toggle ‘Cn’ to logic 1 level.
Toggle all the function select inputs from ‘S1’ to ‘S3’ to logic ‘0’ level.
Toggle the function select input ‘S0’ to logic ‘1’ level.
Switch on the supply.
You will observe that the output is equal to input logic - OR output of An and Bn inputs (refer to
step 2 of table 2).
Result:
45
Output Fn =A + B.
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 0 level.
2. Switch on the supply.
3. You will observe that the output is equal to output of step 8 (of this experiment) incremented by 1.
Result:
Output Fn = (A+B) plus 1.
Switch off the power supply.
Objective:
Performing logical AND-decrement operation
4. Repeat all steps from 1 to 7 of experiment 2.
5. Now give any combination of inputs at sockets
and
of Input section.
6. Toggle the mode control input ‘M’ to logic ‘0’ level for arithmetic operation mode.
7. Now toggle ‘Cn’ to logic 0 level.
8. Toggle the function select inputs from ‘S0’, ‘S1’ and ‘S3’ to logic ‘1’ level.
9. Toggle the function select input ‘S2’ to logic ‘0’ level.
10. Switch on the supply.
11. You will observe that the output is equal to logic-AND operation of the inputs An and Bn (refer to
step 12 of table 2).
Result:
Output Fn = A.B .
Switch off the power supply
1. Now toggle ‘Cn’ to logic 1 level.
2. Switch on the supply.
3. You will observe that the output is equal to output of step 11 (of this procedure) decremented by 1.
Result:
Output Fn = (A.B) minus 1.
Switch off the power supply.
Objective:
Performing left shift operation
1. Repeat all steps from 1 to 7 of experiment 2.
2.
3.
4.
5.
6.
7.
8.
Now give any combination of inputs at sockets
and
of Input section.
Toggle the mode control input ‘M’ to logic ‘0’ level for arithmetic operation mode.
Now toggle ‘Cn’ to logic 1 level.
Toggle the function select inputs ‘S2’ and ‘S3’ to logic ‘1’ level.
Toggle the function select inputs ‘S0’ and ‘S1’ to logic ‘0’ level.
Switch on the supply.
You will observe that the output is equal to input An with each of its bit shifted to left or MSB
position (refer to step 13 of table 2).
Result:
Output Fn = A plus A.
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 0 level.
46
2. Switch on the supply.
3. You will observe that the output is equal to output of step 8 (of this procedure) incremented by 1.
Result:
Output Fn = A plus A plus 1.
Switch off the power supply.
Objective:
Solving various equations and incrementing/decrementing their value
1. Repeat all steps from 1 to 7 of experiment 2.
2. Now give any combination of inputs at sockets
and
of Input section.
3. Toggle the mode control input ‘M’ to logic ‘0’ level for arithmetic operation mode.
· Solving A+
1. Now toggle ‘Cn’ to logic 1 level.
2. Toggle the function select inputs ‘S0’, ‘S2’ and ‘S3’ to logic ‘0’ level.
3. Toggle the function select input ‘S1’ to logic ‘1’ level.
4. Switch on the supply.
5. You will observe that the output is equal to A+ (refer to step 3 of table 2).
Result:
Output Fn = A +
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 0 level.
2. Switch on the supply.
3. You will observe that the output is equal to output of step 5 incremented by 1.
Result:
Output Fn = (A+ ) plus 1.
Switch off the power supply.
· Solving (A plus A• )
1. Now toggle ‘Cn’ to logic 1 level.
2. Toggle the function select inputs ‘S0’, ‘S1’ and ‘S3’ to logic ‘0’ level.
3. Toggle the function select input ‘S2’ to logic ‘1’ level.
4. Switch on the supply.
5. You will observe that the output is equal to A plus A• (refer to step 5 of table 2).
Result:
Output Fn = A plus A•
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 0 level.
2. Switch on the supply.
3. You will observe that the output is equal to output of step 5 incremented by 1.
Result:
Output Fn = A plus A• plus 1.
Switch off the power supply
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· Solving [(A+B) plus A• ]
1. Now toggle ‘Cn’ to logic 1 level.
2. Toggle the function select inputs ‘S1’ and ‘S3’ to logic ‘0’ level.
3. Toggle the function select input ‘S0’ and ‘S2’ to logic ‘1’ level.
4. Switch on the supply.
5. You will observe that the output is equal to (A+B) plus A• (refer to step 6 of table 2).
Result:
Output Fn = (A+B) plus A•
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 0 level.
2. Switch on the supply.
3. You will observe that the output is equal to output of step 5 incremented by 1.
Result:
Output Fn = (A+B) plus A• plus 1.
Switch off the power supply.
· Solving [ A plus AB]
1. Now toggle ‘Cn’ to logic 1 level.
2. Toggle all the function select inputs from ‘S0’ and ‘S2’ to logic ‘0’ level.
3. Toggle the function select input ‘S3’ to logic ‘1’ level.
4. Switch on the supply.
5. You will observe that the output is equal to A plus AB (refer to step 9 of table 2).
Result:
Output Fn = A plus AB
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 0 level.
2. Switch on the supply.
3. You will observe that the output is equal to output of step 5 incremented by 1.
Result:
Output Fn = A plus AB plus 1.
Switch off the power supply.
· Solving [(A+ ) plus A•B]
1. Now toggle ‘Cn’ to logic 1 level.
2. Toggle the function select inputs ‘S0’ and ‘S2’ to logic ‘0’ level.
3. Toggle the function select inputs ‘S1’ and‘S3’ to logic ‘1’ level.
4. Switch on the supply.
5. You will observe that the output is equal to [(A+ ) plus A•B] (refer to step 11 of table 2).
Result:
Output Fn = (A+ ) plus A•B
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 0 level.
2. Switch on the supply.
3. You will observe that the output is equal to output of step 5 incremented by 1.
Result:
48
Output Fn = (A+ ) plus A•B plus 1
Switch off the power supply.
· Solving [(A+B) plus A]
1. Now toggle ‘Cn’ to logic 1 level.
2. Toggle the function select inputs ‘S0’, ‘S2’ and ‘S3’ to logic ‘1’ level.
3. Toggle the function select inputs ‘S1’ to logic ‘0’ level.
4. Switch on the supply.
5. You will observe that the output is equal to [(A+B) plus A] (refer to step 14 of table 2).
Result:
Output Fn = (A+B) plus A.
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 0 level.
2. Switch on the supply.
3. You will observe that the output is equal to output of step 5 incremented by 1.
Result:
Output Fn = (A+B) plus A plus 1.
Switch off the power supply.
· Solving (A+ ) plus A
1. Now toggle ‘Cn’ to logic 1 level.
2. Toggle the function select inputs from ‘S1’to ‘S3’ to logic ‘1’ level.
3. Toggle the function select inputs ‘S0’ to logic ‘0’ level.
4. Switch on the supply.
5. You will observe that the output is equal to [(A+ ) plus A] (refer to step 15 of table 2).
Result:
Output Fn = (A+ ) plus A.
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 0 level.
2. Switch on the supply.
3. You will observe that the output is equal to output of step 5 incremented by 1.
Result:
Output Fn = (A+ ) plus A plus 1.
Switch off the power supply.
· Solving A•
1.
2.
3.
4.
5.
Now toggle ‘Cn’ to logic 0 level.
Toggle the function select inputs from ‘S0’ to ‘S2’ to logic ‘1’ level.
Toggle the function select input ‘S3’ to logic ‘0’ level.
Switch on the supply.
You will observe that the output is equal to A• (refer to step 8 of table 2).
Result:
Output will be Fn = A•
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 1 level.
49
2. Switch on the supply.
3. You will observe that the output is equal to output of step 5 decremented by 1.
Result:
Output Fn = A• minus 1.
Switch off the power supply.
Objective:
To study ALU for giving logic ‘0’ or ‘minus 1’ at the output
Procedure:
1. Repeat steps 1-7 of experiment 1.
2.
3.
4.
5.
6.
7.
8.
Now give any combination of inputs at sockets
and
of Input section.
Toggle the mode control input ‘M’ to logic ‘0’ level for arithmetic operation mode.
Now toggle ‘Cn’ to logic 0 level.
Toggle the function select inputs ‘S0’ and ‘S1’ to logic ‘1’ level.
Toggle the function select inputs ‘S2’ and ‘S3’ to logic ‘0’ level.
Switch on the supply.
You will observe that the output is equal to logic 0 (refer to step 4 of table 2).
Result:
Output will be Fn = logic 0 = 0000 (in 2’s complement notation with Cn+4 output high).
Switch off the power supply.
1. Now toggle ‘Cn’ to logic 1 level.
2. Switch on the supply.
3. You will observe that the output is equal to 2’s complement of logic 1 (refer to step 4 of table 2).
Result:
Output will be Fn = minus 1 = 1111 (in 2’s complement notation with Cn+4 output high).
Switch off the power supply.
Objective:
To study ALU for performing comparison of two 4-bit binary numbers
50
Procedure:
1. Connect sockets
of ‘Input Section’ to sockets
of ‘Arithmetic and Logic Unit’
section respectively.
2. Connect socket ‘Cn’ of ‘Input Section’ to socket ‘Cn’ of ‘Arithmetic and Logic Unit’ section.
3. Connect sockets
of ‘Input Section’ to sockets
of ‘Arithmetic and Logic Unit’
section respectively.
4. Connect sockets ‘S0–S3’ of ‘Function and Mode Select Input’ section to sockets ‘S0-S3’ of
‘Arithmetic and Logic Unit’ section respectively.
5. Connect socket ‘M’ of ‘Function and Mode Select Input’ section to socket ‘M’ of ‘Arithmetic and
Logic Unit’ section.
6. Connect sockets
of ‘Output Section’ to sockets
of ‘Arithmetic and Logic Unit’
section respectively.
7. Connect sockets ‘C n+4’, ‘A=B’,
and
of ‘Output Section’ to sockets ‘Cn+4’, ‘A=B’,
and
of ‘Arithmetic and Logic Unit’ section.
8. Now give any combination of inputs at sockets
and
of Input section.
9. Toggle the mode control input ‘M’ to logic ‘0’ level for arithmetic operation mode.
10. Now toggle ‘Cn’ to logic 1 level.
11. Toggle the function select inputs ‘S0’ and ‘S3’ to logic ‘0’ level.
12. Toggle the function select inputs ‘S1’ and ‘S2’ to logic ‘1’ level.
13. Switch on the supply.
14. You will observe that the ‘C n+4’ and ‘A=B’ outputs display the relative magnitude information as
per the table 3.
15. Switch off the power supply.