4-Bit Universal Shift Register
Behavioral Vs. Structural
Description
• Behavioral Description
– Behavior model of a shift register
• Describe the operation of the register without
a preconceived structure.
– Random number generator
• Binary values of msb_in, lsb_in, i_par
• Structural Description
– Models the circuits in terms of a collection
of components such as gates, flip-flops…
Behavioral Model of Shift
Regsiter
Test Bench
1. Generate random number
With matlab
2. Read random number
at the neg edge of the clock
[s1,s0=[1,1], Load
i_par=0111
a_par=0111
[s1,s0]=[0,0], No Change
i_par=0111
a_par=0011
[s1,s0]=[1,0], Shift Left
[s1,s0]=[0,1], Shift Right
4-Bit Universal Shift Register
Q
clr
clk
select
i3 i1
i2 i0
Waveform
Load
No Change
Shift Right
Shift Left
4-bit Universal Shift Register
Verilog Code of Each Stage