Modulo-N Counters
Module M10.4
Section 7.2
Counters
• Modulo-5 Counter
• 3-Bit Down Counter with Load and Timeout
• Modulo-N Down Counter
Modulo-5 Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
X
X
X
0
1
1
0
0
X
X
X
1
0
1
0
0
X
X
X
Q0.D
D
CLK
Q1.D
D
CLK
Q2.D
D
CLK
Q
Q0
!Q
Q
Q1
!Q
Q
!Q
Q2
Modulo-5 Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
X
X
X
0
1
1
0
0
X
X
X
1
0
1
0
0
X
X
X
Q1 Q0
00
Q2
01
11
1
0
1
10
X
X
X
Q2.D
Q2.D = Q1 & Q0
Modulo-5 Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
X
X
X
0
1
1
0
0
X
X
X
1
0
1
0
0
X
X
X
Q1 Q0
00
Q2
01
0
1
1
X
11
10
1
X
Q1.D
Q1.D = !Q1 & Q0
# Q1 & !Q0
X
Modulo-5 Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
X
X
X
0
1
1
0
0
X
X
X
1
0
1
0
0
X
X
X
Q1 Q0
00
Q2
0
1
01
11
1
10
1
X
X
X
Q0.D
Q0.D = !Q2 & ! Q0
Note: On reset output pins are all high.
Therefore, we need to include a clear input.
mod5cnt.pld
Listing 7.7
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
Format
mod5cnt.pld
mod5cnt;
OU0026;
01;
8/06/91;
R. E. Haskell;
Oakland University;
Rochester, MI;
CSE 171;
G16V8;
j;
/********************************************************/
/* This example demonstrates the use of D-type
*/
/* flip-flops to design a modulo-5 counter
*/
/********************************************************/
/*
Target Device: G16V8
*/
/********************************************************/
mod5cnt.abl
MODULE Mod5Cnt
TITLE ‘Modulo-5 Counter, A. Student, 7/20/02'
DECLARATIONS
“ INPUT PINS “
PB PIN 10;
" push-button switch (clock)
Clear PIN 7;
" Switch 2
" OUTPUT PINS "
Q2..Q0 PIN 37,36,35 ISTYPE 'reg buffer';
Q = [Q2..Q0];
" LED 6..8
" 3-bit output vector
[A,B,C,D,E,F,G,DP] PIN 15,18,23,21,19,14,17,24 ISTYPE 'com';
Segments = [A,B,C,D,E,F,G];
" 7-segment LED display
mod5cnt.abl (cont’d)
EQUATIONS
Q.c = PB;
Q0.d =
!Clear & !Q2 & !Q0;
Q1.d =
!Clear & !Q1 & Q0
Note !Clear
# !Clear & Q1 & !Q0;
Q2.d =
!Clear & Q1 & Q0;
DP = PB;
" decimal point
@radix 16;
truth_table ( Q -> Segments )
…
" 7-segment display
mod5cnt.abl (cont’d)
@radix 16;
truth_table ( Q -> Segments )
0 -> 7E;
1 -> 30;
2 -> 6D;
3 -> 79;
4 -> 33;
5 -> 5B;
6 -> 5F;
7 -> 70;
" 7-segment display
mod5cnt.abl (cont’d)
test_vectors([PB,Clear] -> Q)
[.c.,1] -> 0;
[.c.,0] -> 1;
[.c.,0] -> 2;
[.c.,0] -> 3;
[.c.,0] -> 4;
[.c.,0] -> 0;
[.c.,0] -> 1;
[.c.,0] -> 2;
[.c.,0] -> 3;
[.c.,0] -> 4;
[.c.,0] -> 0;
[.c.,0] -> 1;
[.c.,0] -> 2;
END
Simulation File, mod5cnt.si
Listing 7.8
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
Format
mod5cnt.si
mod5cnt;
OU0026;
01;
8/06/91;
R. E. Haskell;
Oakland University;
Rochester, MI;
CSE 171;
G16V8;
j;
CUPL Simulation
File
/********************************************************/
/* This example demonstrates the use of D-type
*/
/* flip-flops to design a modulo-5 counter
*/
/********************************************************/
/*
Target Device: G16V8
*/
/********************************************************/
mod5cnt.si
ORDER:
VECTORS:
C1 LLL
C0 HLL
C0 LHL
C0 HHL
C0 LLH
C0 LLL
C0 HLL
C0 LHL
C0 HHL
C0 LLH
C0 LLL
C0 HLL
C0 LHL
C0 HHL
C0 LLH
CUPL Simulation
File
clock,%2,clear,%2,q0,%2,q1,%2,q2;
Note: first test vector clears output
Back to LLL after 5 states
CUPL Simulation
Output File
Counters
• Modulo-5 Counter
• 3-Bit Down Counter with Load and Timeout
• Modulo-N Down Counter
3-Bit Down Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Q0.D
D
CLK
Q1.D
D
CLK
Q2.D
D
CLK
Q
Q0
!Q
Q
Q1
!Q
Q
!Q
Q2
3-Bit Down Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Q1 Q0
00
Q2
0
1
01
11
10
1
1
1
1
Q2.D
Q2.D = !Q2 & !Q1 & !Q0
# Q2 & Q1
# Q2 & Q0
3-Bit Down Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Q1 Q0
00
Q2
01
11
0
1
1
1
1
1
Q1.D
Q1.D = !Q1 & !Q0
# Q1 & Q0
10
3-Bit Down Counter
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Q1 Q0
00
Q2
01
11
10
0
1
1
1
1
1
Q0.D
Q0.D = ! Q0
dncnt3ld.abl
MODULE DnCnt3LD
TITLE '3-bit Down Counter with Clear and Load'
If load = 1,
DECLARATIONS
" INPUT PINS "
Load Data to
PB PIN 10;
Clear PIN 7;
Load PIN 11;
X2..X0 PIN 71,66,70;
Data = [X2..X0];
"
"
"
"
"
[q0..2]
push-button switch (clock)
Switch 2
Switch 3
Switch 6..8
3-bit input vector
" OUTPUT PINS "
LED1..LED2 PIN 44,43 ISTYPE 'com';
" LED 1..2
timeout PIN 41 ISTYPE 'com';
3 [q0..2]
timeout "= 1LED
when
Q2..Q0 PIN 37,36,35 ISTYPE 'reg buffer'; " LED 6..8
= [0,0,0]
Q = [Q2..Q0];
" 3-bit output vector
[A,B,C,D,E,F,G,DP] PIN 15,18,23,21,19,14,17,24 ISTYPE 'com';
Segments = [A,B,C,D,E,F,G];
" 7-segment LED display
dncnt3ld.abl (cont’d)
EQUATIONS
LED1 = Clear;
LED2 = Load;
Q.c = PB;
WHEN Clear THEN Q.d = 0;
ELSE
{
WHEN Load THEN
Q.d = Data;
ELSE
{
Q2.d = !Clear & !Q2 & !Q1 & !Q0
# !Clear & Q2 & Q1
# !Clear & Q2 & Q0;
Q1.d = !Clear & !Q1 & !Q0
# !Clear & Q1 & Q0;
Q0.d = !Clear & !Q0;
}
}
timeout = !Q0 & !Q1 & !Q2;
…
Simulation File, dncnt3ld.si
Listing 7.10
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
Format
dncnt3ld.si
dncnt3ld;
OU0029;
01;
8/07/91;
R. E. Haskell;
Oakland University;
Rochester, MI;
CSE 171;
G16V8;
j;
CUPL Simulation
File
/********************************************************/
/* This is a 3-bit down counter
*/
/* with clear and parallel load
*/
/********************************************************/
/*
Target Device: G16V8
*/
/********************************************************/
dncnt3ld.si
CUPL Simulation
File
ORDER:
clock,%2,clear,load,%3,I2..0,%3,q0,%2,q1,%2,q2,%2,timeout;
VECTORS:
C10 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C01 101
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
C00 XXX
LLL
HHH
LHH
HLH
LLH
HHL
HLH
LLH
HHL
LHL
HLL
LLL
HHH
LHH
HLH
LLH
HHL
LHL
HLL
LLL
HHH
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
/* clear counter */
/* load 101 into counter */
/* timeout */
/* timeout */
CUPL Simulation
Output File
Counters
• Modulo-5 Counter
• 3-Bit Down Counter with Load and Timeout
• Modulo-N Down Counter
3-Bit Down Counter with
Load and Timeout
clock
clear
load
I0
I1
I2
GND
______________
|
dncnt3ld
|
x---|1
20|---x
x---|2
19|---x
x---|3
18|---x
x---|4
17|---x
x---|5
16|---x
x---|6
15|---x
x---|7
14|---x
x---|8
13|---x
x---|9
12|---x
x---|10
11|---x
|______________|
Vcc
q0
q1
q2
timeout
To make a Modulo-5 counter, connect [I2..0] to 100
and connect timeout to load.
CUPL Simulation
Output File