Lecture 2:
Limiting Models of
Instruction Obeying Machine
虞台文
大同大學資工所
智慧型多媒體研究室
Content


Machine Simulation and Equivalence
Unlimited-Register Machine
Lecture 2:
Limiting Models of
Instruction Obeying Machine
Machine Simulation
and Equivalence
大同大學資工所
智慧型多媒體研究室
Computer as a Partial Function
M  a machine
  an M-program
M  an encoding function
Y  a decoding function
e: X
d :M
e
input
M
d
output
Computer as a Partial Function
d M e
A partial function
e
input
M
d
output
Machine Equivalence
f :X
Y  d M1 e
e
M1
Input
(X)
d
Output
(Y)
M1  h M 2  g
Machine Equivalence
f :X
Y  d M1 e
e
d
M1
Input
(X)
g
h
M 2 
f :X
Y d
h
M2  g  e
Output
(Y)
M1  h M 2  g
Machine Equivalence
f :X
Y  d M1 e
e
d
M1
Input
(X)
f :X
g
e
Y d
h
M 2 
h
d
M2  g  e
Output
(Y)
 d  M2  e
M1  h M 2  g
Machine Equivalence
f :X
Input
(X)
Y  d  M2  e
e
g
e
e  g e
d
h
M 2 
d
Output
(Y)
d  d h
M1  h M 2  g
Machine Equivalence
f :X
Input
(X)
Y  d  M2  e
e
e  g e
M 2 
d
Output
(Y)
d  d h
Machine Equivalence Defined
M1 , M2 :
M1 , M 2 :
:
:
two machines
Memory sets of M1 and M2.
M1-program
M2-program
M1 : M1
g
M 2  : M 2
M1
h
M2
g, h such that
M1  h M 2  g
f  d M1 e
f  d  M 2  e
Machine Equivalence Defined
Let
Y can be computed on M1 using , i.e., f  d M1 e
f :X
f  (d h) M 2  ( g e)
encoding function
f can be computed on M2 using ’, with
M1 : M1
g
M 2  : M 2
M1
h
M2
e  g e : X
M2
decoding function
d  d h : M2
g, h such that
M1  h M 2  g
Y
Machine Simulation Defined
A machine M2 simulates M1 if

g : M1
M2
h : M2
M1
such that
we can specify an algorithm which given any program
 produces ’ satisfying
M1  h M 2  g
Problems:
1. What is the algorithm?
2. How to find g and h?
Machine Simulation Defined
A machine M2 simulates M1 if

g : M1
M2
h : M2
M1
such that
we can specify an algorithm which given any program
 produces ’ satisfying
M1  h M 2  g
M2 simulates M1
The memory encoder g
has to be one to one.
Theorem
A machine M2 simulates M1 if

g : M1
M2
h : M2
M1
such that
we can specify an algorithm which given any program
 produces ’ satisfying
M1  h M 2  g
M2 simulates M1
The memory encoder g
has to be one to one.
Theorem
Pf)
M2 simulates M1
Consider
:
START
M1  h M 2  g
HALT
Identity
M1 (m)  I(m)  m
m1  m2 , M1 (m1 )  M1 (m2 )
Suppose that g is not one to one.
Then, g(m1) = g(m2) = M for some m1m2.
M1 (m1 )  h M2  g (m1 )  h M2  (M )
M1 (m2 )  h M2  g (m2 )  h M2  (M )
F: the set of operation functions of M1.
P: the set of predicates of M1.
Stepwise Simulation
M2 stepwise simulates M1 if
 1-to-1 encoding function g:M1M2 such that
1) For each FF,
 a program F g M  M
1F
2 F
in M2 such that
g
2) For each PP,
true M1P  m   true

 a program P M 2  g (m)    false M1P  m   false
P
in M2 such that

M1P  m   

and P doesn’t change M2.
F: the set of operation functions of M1.
P: the set of predicates of M1.
Stepwise Simulation
M2 stepwise simulates M1 if
 1-to-1 encoding function g:M1M2 such that
1) For each FF,
 a program F g M  M
1F
2 F
in M2 such that
F 
2) For eachF PP,
 a programm
P
g
g M1F  M 2 F g
true M1P  m   true
g 
M 2 P  g (m)    false M1Pm
 m   false
in M2 such that

M1P  m
F


F
M1F (m)
and P doesn’t
.
g change M2M
2 F
( m)
F: the set of operation functions of M1.
P: the set of predicates of M1.
Stepwise Simulation
M2 stepwise simulates M1 if
 1-to-1 encoding function g:M1M2 such that
1) For eachmFF,
false
 a program Ftrue
m
P
P
g ( m)
false
g M1F  M 2 F g
P
in M2 such that
g ( m)
m
P
2) For each PP,
true
g ( m)
true M1P  m   true

 a program P M 2  g (m)    false M1P  m   false
P
in M2 such that

M1P  m   

and P doesn’t change M2.
Stepwise Simulation
M2 stepwise simulates M1
M2 simulates M1
SR4
Memory set M SR  4 registers (x1, x2, x3, x4)
4
M SR4  N  N  N  N
Operations
FSR4
xi  xi  1
for i = 1, 2, 3, 4.
xi  xi  1
Predicates
PSR4
xi  0?
for i = 1, 2, 3, 4.
Dose PC Simulates SR4?
Review PC
Memory set
Dose SR4 Simulates PC?
M PC  2 registers (x, y)
M PC  N  N
Operations
Predicates
FPC
PPC
x  x 1 y  y  1
x  x 1 y  y  1
x  0?
y  0?
x  y?
y x y
y  x y
Prove PC Simulates SR4
Step 1: Define a 1-to-1 encoding function g : M SR4
g : i, j , k , l
M PC
2i  3 j  5 k  7 l , 0
Step 2: For each FFSR4, find a F on PC such that …
To be shown
Step 3: For each PPSR4, find a P on PC such that …
Exercise
F
F
SR4
PC
F
F
xi  xi  1
 x  x 1
xi  xi  1
 x  x 1
i
i
i
i
F
F
xi  xi  1
x1  x1  1
 x  x 1
i
i
 x  x 1
1
1
START
y  2x
x  0?
true
x0
x  x 1
x y
false
0 y
y  0?
false
true
y  y 1
y  y 1
y  y 1
x  x 1
HALT
F
F
xi  xi  1
 x  x 1
x1  x1  1
 x  x 1
x2  x2  1
 x  x 1
x3  x3  1
 x  x 1 Exercise
x4  x4  1
 x  x 1
1
2
3
4
1
2
3
4
i
i
F
F
x1  x1  1
xi  xi  1
 x  x 1
1
1
START
x  0?
true
START
 x  x 1
i
i
2 | x?
false
x  x 1
true
2 | x?
yx
x0
false
x y
0 y
x  y/2
y  y 1
x  0?
true
x  x 1
y  y 1
HALT
false
FALSE
HALT
TRUE
HALT
In fact, SR2 also simulates SR4.
Prove PC Simulates SR4
Step 1: Define a 1-to-1 encoding function g : M SR4
g : i, j , k , l
M PC
2i  3 j  5 k  7 l , 0
Step 2: For each FFSR4, find a F on PC such that …
To be shown
Step 3: For each PPSR4, find a P on PC such that …
Exercise
Is SR more powerful than SR2? No.
Is SR more powerful than PC?
Not sure, now.
Discussion
PC
SR2
SR4
SR
Lecture 2:
Limiting Models of
Instruction Obeying Machine
Unlimited-Register
Machine
大同大學資工所
智慧型多媒體研究室
The Unlimited-Register Machine

Unlimited number of registers.

Unbounded capacity of every register.

Powerful instructions
The Machine R
Memory set


M R   ni i 1 ni  0, ni  0 except finite many

That is, for some, k  1, ni = 0 for all i  k
(finite memory are used).
Operations
FR
xi  m
xi  x j
xi  x j  m
xi  x j  xk
xi  x j  m
xi  x j  xk
xi  x j  m
xi  x j  xk
xi  x j  m
xi  x j  xk
Predicates
PR
xi  m ?
xi  x j ?
xi  m ?
xi  x j ?
Input & Output Registers of R
MR 
, u1 , u2 ,
, uk , w1 , w2 ,
k input
registers
, wl ,
l output
registers
Other registers can be working registers if necessary.
MR 
, u1 , u2 ,
, uk , w1 , w2 ,
, wl ,
Running R
 : a program in R
e : encoder
e : x1 ,
, xk
0,
,0, u1  x1,
, uk  xk ,0,
d : decoder
d:
, w1  y1 ,
, wl  yl ,
d R e : k -tuple
y1,
l -tuple
, yl
SR
Memory set
M SR  The same as R
Operations & Predicates
xi  xi  1
xi  xi  1
xi  0?
i = 1, 2, …
Machine Simulations
Simulates?
R
SR
Simulates?
Prove SR Simulates R
Step 1: g  ?
g : x1 ,
, xk
y1  0,
, yw  0, x1,
, xk ,0,
w working registers
Step 2: F
F
xi  m
xi  x j
xi  x j  m
xi  x j  xk
xi  x j  m
xi  x j  xk
xi  x j  m
xi  x j  xk
xi  x j  m
xi  x j  xk
Step 3: P
P
xi  m ?
xi  x j ?
xi  m ?
xi  x j ?
Prove SR Simulates R
Step 1: g  ?
g : x1 ,
, xk
Converted to register-mode
y1  0, by, using
yw a0,working
x1, , xk ,0,
operation
register.
w working registers
Step 2: F
F
xi  m
xi  x j
xi  x j  m
xi  x j  xk
xi  x j  m
xi  x j  xk
xi  x j  m
xi  x j  xk
xi  x j  m
xi  x j  xk
Step 3: P
P
xi  m ?
xi  x j ?
xi  m ?
xi  x j ?
Prove SR Simulates R
xi  x j




m
 x x
i
j
m
xi  m ?
>
=
 x m ?
i
START
ym
START
true
ym
xi  x j
xi  y ?
false
y
y0
y0
y0
HALT
TRUE
HALT
FALSE
HALT
Prove SR Simulates R
 x x x
i
j
 x x  x
k
i
j
k
START
START
y  xk
y  xj
xi  0
xi  0
y>0 ?
true
xi  xi + xj
false
xk>0 ?
true
xk>y ?
false
true
false
y y  1
y  y  xk
xi  xi + 1
HALT
HALT
y 0
Prove SR Simulates R
 x x  x
i
j
 x x  x
k
i
j
k
START
START
y  xk
y  xk
xi  xj
xi  xj
y>0 ?
true
false
y>0 ?
true
xi  xi + 1
xi  xi  1
y y  1
y y  1
HALT
HALT
false
Prove SR Simulates R
 x x
i
 x x  x
j
i
START
y0
y xi + xj
false
xi  y
true
xj  xj  1
y>0?
true
xi  xi + 1
xj  xj + 1
y y + 1
y y  1
HALT
j
START
xi  0
xj>0?
i
false
y0
HALT
Prove SR Simulates R
 x x ?
i
 x x ?
j
i
j
START
START
false
y  x i x j
true
y>0 ?
false
x j > x i?
true
false
x i > x j?
TRUE
HALT
FALSE
HALT
TRUE
HALT
FALSE
HALT
Exercise
Using SR to Simulate R, at least how
many working registers are required?
Discussion
PC
SR2
SR4
SR
R
Discussion

Machine equivalence is reflexive, symmetric, and
transitive, i.e., an equivalence relation.

SR2 is the same powerful as R.

To study computation, considering PC, SR2, SR4,
SR or R is equally well.

The above machines are register machines.
Register Functions
Use x1, …, xk as input registers of R.
Let fi: Nk  N be the function computed by an Rprogram  using xi as the output register.
We call the k functions f1, …, fk the (k-adic) register
functions of .
We will considered register functions (the class of
all k-adic, k1, register functions) to be functions
that are computable by R.
Examples
START
x1 , x2 , x3 , x4 , x5
x1  x3  5
5x3 , x2 , x3 , x4 , x5
x2  x1 + x3
f1 : x1 , x2 , x3 , x4 , x5
5x3
f 2 : x1 , x2 , x3 , x4 , x5
6 x3
f3 : x1 , x2 , x3 , x4 , x5
x3
f4 : x1 , x2 , x3 , x4 , x5
x4
f5 : x1 , x2 , x3 , x4 , x5
x5
5x3 ,6 x3 , x3 , x4 , x5
HALT