Evolutionary Algorithm Based Synthesis of Multi-Output Ternary Functions Using
Quantum Cascade of Generalized Ternary Gates¶
Mozammel H. A. Khan* and Marek A. Perkowski#
Department of Computer Science and Engineering, East West University, 43 Mohakhali, Dhaka 1212,
BANGLADESH.
#
Department of Electrical and Computer Engineering, Portland State University, 1900 SW 4 th Avenue, Portland, OR
97201, USA.
*
Abstract: Ternary quantum circuits have recently been introduced to help reduce the size of multi-valued logic for
multi-level quantum computing systems. However, synthesizing these quantum circuits is not easy. In this paper we
describe a new evolutionary algorithm based synthesizer for ternary quantum circuits. Our results show that some of
the synthesized circuits use fewer gates than previously published methods.
Keywords: Evolutionary algorithm, Galois Field logic, generalized ternary gate, generalized ternary Toffoli gate,
incompletely specified ternary function, mirror gate, multi-valued quantum logic, quantum cascade, ternary logic,
ternary permutation quantum gate, ternary Shift gate, ternary Swap gate
1. INTRODUCTION
Quantum computing (QC) is a very promising and flourishing research area [1-3]. QC theoretically allows
designers to build much more efficient computers than the existing classical ones. For example, some problems that
cannot be solved in polynomial time using classical computers can be solved in polynomial time using quantum
computers [1] (proven already experimentally but for small data only). In part, this is because quantum circuits are
inherently able to perform massive parallel computations [1-3]. While most of the results are for binary quantum
computers, the multi-valued quantum logic synthesis is a very new research area. Unfortunately, previous synthesis
methods produce circuits that were unnecessarily complex. One promising approach for reducing the circuit size is
to use gates that are ternary counterparts of the classical binary Feynman gates and new 2-qudit ternary controlled
gates (qudit is a multiple-valued counterpart of binary quantum bit or qubit).
The success in the ion trap quantum realization of some ternary gates [4] gives increasing hopes to physically
build complete ternary quantum circuits in this or other quantum realization technologies. However, even when the
ternary quantum technology will become available, synthesizing automatically a quantum circuit from its
specification is not a trivial problem and most previous attempts have been disappointing or insufficient from one
point of view or the other. Although there are several papers about using genetic algorithm (GA) for binary quantum
computers [5-8] and quantum inspired evolutionary algorithms (EA) [9], to the best of our knowledge, no attempts
have been made to use GAs or EAs for designing ternary quantum circuits. Another issue is the quantum
realizability of gates and their costs. Some authors [10-14] assume complex gates that are not directly realizable in
quantum. The costs of realizing these gates using realizable gates from [4] would be very high. Only two-qudit gates
are directly realizable [4] and other gates are compositions of realizable gates. This paper and [15] are the first
papers to introduce a practical synthesis approach to synthesize directly with quantum realizable 2-qudit generalized
ternary gates (GTG gates) and not only with ternary multi-input Toffoli-like gates [16-18, 12-14]. Paper by
Muthukrishnan and Stroud [4] introduced families of realizable 2-qubit controlled gates in which only one value, the
highest one, can be controlling. That means, for all but the highest value of the controlling variable the data variable
(controlled variable) is unaffected. Otherwise a ternary 1-qudit operation is done on the controlled variable. Based
on our understanding of paper [4], we proposed [16-18, 19] the generalized ternary gates where every value of the
controlling variable can be used to select a ternary 1-qudit operator on the controlled variable. We believe that these
gates are directly realizable from quantum primitives that are used in [4] and in general ion trap and NMR quantum
computing [1-3, 10, 12, 19, 20]. The matrices of such gates are unitary. It can be shown [15] that every GTG can be
build from Muthukrishnan/Stroud gates [4] thus the model introduced in [16-19] and used here is mathematically
correct. Because however we do not know if these gates can be build directly, we are not discussing the costs of
these gates and thus not comparing the costs of solutions with some other models, because in some cases we are
uncertain how the complex gates of the authors would be realized using 2-qudit quantum realizable gates from [4].
¶
Preliminary version of this work will be presented in the Congress of Evolutionary Computing 2004 (CEC 2004),
Portland, Oregon, USA, 19-23 June 2004.
*
Corresponding author. Tel: (+880-2) 988-2308, Fax: (+880-2) 881-2336, Email: [email protected]
1
The assumption of using GTG gates allows us to obtain significant reduction in terms of elementary gates that are
realized in ion trap technology, with yet uncertain realization costs. Our EA method is however general and in
particular it allows to use also any subset of GTG gates, including the realizable subsets described by
Muthukrishanan and Stroud or 2-qudit simplifications of gates from [12], as special cases. All these designs cannot
be done by paper and pencil. Therefore, developing CAD tools for synthesizing ternary function using these gates
and any of their subsets (like those from [4, 15]) has become a demand of time. In this paper we present such a CAD
system where we propose an Evolutionary Algorithm (EA) based method for synthesizing both completely and
incompletely specified multi-output ternary functions using cascades of GTG gates or any subset of these gates. The
gates assumed in [12, 14] or any other gates described by unitary permutative matrices can be also used, but they are
treated as macros in realization. The costs of such gates may be thus high because of our way of realizing them
using our elementary gates.
In this paper, by evolutionary algorithm (EA) we mean genetic algorithm (GA) with real-valued encoding of the
chromosome using complex data structures [21]. GAs are very popular Soft Computing (SC) approaches for solving
problems with no identified structure and high level of noise [21-23]. The reasons behind this popularity are (i) a big
problem space can be searched, (ii) the size of this search space can be moderated by parameters, (iii) a variety of
new solutions can be produced, and (iv) with long enough time a solution can be obtained that is close to the optimal
one. These advantages make GAs useful for synthesizing ternary functions using cascade of GTG gates, because the
problem structure of such cascade is still unidentified and the search space itself is exponentially large since there
are 63 = 216 possible GTG gates (see Section 4).
The rest of the paper is organized as follows. In Section 2, we describe some previous works in multi-valued
logic. Section 3 covers the fundamentals of multi-valued quantum logic along with some key definitions. Section 4
introduces some basic ternary permutation quantum gates. The general model of synthesizing multi-output ternary
functions using cascade of GTG gates is given in Section 5. Section 6 provides details of our EA. In Section 7, we
discuss some knowledge-based local transformation of the circuit. Section 8 discusses a new feature of our approach
– synthesis of incompletely specified ternary functions. Sections 9 and 10 discuss synthesis of generalized ternary
Toffoli gate and ternary swap gate built on the top of GTG gates, respectively. We give our experimental results in
Section 11. Section 12 concludes the paper and Section 13 presents future work.
2. PREVIOUS WORKS
In 2000, Muthukrishnan and Stroud [4] developed multi-valued quantum formalism for multi-level quantum
computing systems and showed realizability of some universal multiple-valued logic operators in linear ion trap
devices. Although no synthesis procedure was proposed in [4], our initial attempt of using this approach [19]
produced circuits that were too large. In 2002, Brylinski and Brylinski [20] discussed universality of n-qudit gates
without giving any design algorithm. Since 2001, Al-Rabadi and Perkowski [10, 11], and Khan et al [16, 17]
proposed Galois Field approach to multi-valued quantum logic synthesis in several regular structures. They used
gates that are ternary counterparts of classical binary Feynman and Toffoli gates, but no experimental data were
given. In 2002, De Vos [24] proposed two ternary 1*1 gates and two ternary 2*2 gates, but again no synthesis
method was proposed. In 2002, Perkowski, Al-Rabadi, and Kerntopf [18] proposed a 2*2 Generalized Ternary Gate
(GTG gate) based on the ternary conditional gate [4] and ternary shift gates [16, 17] and showed the realization of
ternary Toffoli gate using GTG gates. This work introduced for the first time the practical realizability of Galois
Field circuits in existing multi-valued quantum technology. In 2003, papers [16, 17] used multi-input Toffoli gates
built from realizable gates, but the results were non-minimal. Paper [15] proposed a method that can be used to very
large single-output functions, but relatively many input constants are necessary and their experimental results can be
definitely improved. Papers [12-14] use different gate models, so the comparison to them is difficult, although some
comparisons will be included. While Toffoli-like gates with n-1 controlling values are assumed in [12, 13], paper
[14] assumes the controlling gates with arbitrary controlling functions of n-1 inputs. Although such assumptions
simplify creating the synthesis algorithms, we are not certain what are the quantum costs of gates used in them
(unfortunately, nothing has been published so far on quantum realizations of all these gate types and the comparison
of costs of synthesis results for them). More importantly, there is nothing published on synthesizing incompletely
specified multi-output circuits, which is the problem dealt with in this paper.
3. FUNDAMENTALS OF MULTI-VALUED QUANTUM LOGIC
In multi-valued (MV) Quantum Computing (QC), the unit of memory (information) is qudit (quantum digit).
MV quantum logic operations manipulate qudits, which are microscopic entities such as a photon’s polarization or
atomic spin. Ternary logic values of 0, 1, and 2 are represented by a set of distinguishable different states of a qutrit
(quantum ternary digit)). These states can be a photon’s polarizations or an elementary particle’s spins. After
2
encoding these distinguishable quantities into multiple-valued constants, qutrit states are represented by 0 , 1 ,
and 2 , respectively.
Qudits exist in a linear superposition of states, and are characterized by a wavefunction ψ . As an example
( d  2 ), it is possible to have light polarizations other than purely horizontal or vertical, such as slant 45
1
corresponding to the linear superposition of ψ 
2 0  2 1 . In ternary logic, the notation for the
2
superposition is α 0  β 1  γ 2 , where , , and  are complex numbers. These intermediate states cannot be


distinguished, rather a measurement will yield that the qutrit is in one of the basis states, 0 , 1 , or 2 . The
2
2
2
probability that a measurement of a qutrit yields state 0 is α , state 1 is β , and state 2 is γ . The sum of
these probabilities is one. The absolute values are required since, in general, ,  and γ are complex quantities.
Pairs of qutrits are capable of representing nine distinct states, 00 , 01 , 02 , 10 , 11 , 12 , 20 , 21 ,
and 22 , as well as all possible superpositions of the states. This property may be mathematically described using
the Kronecker product (tensor product) operation  [1]. The Kronecker product of matrices is defined as follows:
 x y
 x y   ax ay bx by 
b
a 


 
a b   x y    z v 
 z v     az av bz bv 


c d   z v    x y
 x y    cx cy dx dy

 

d
c


 
 z v    cz cv dz dv
  z v 
As an example, consider two qutrits with  1   1 0   1 1   1 2 and  2   2 0   2 1   2 2 . When the two
qutrits are considered to represent a state, that state  12 is the superposition of all possible combinations of the
original qutrits, where
 12   1  2   1 2 00   1  2 01   1 2 02   1 2 10 
.
 1  2 11   1 2 12   1 2 20   1  2 21   1 2 22
Superposition property allows qubit states to grow much faster in dimension than classical bits, and qudits faster
than qubits [4]. In a classical system, n bits represent 2 n distinct states, whereas n qutrits correspond to a
superposition of 3 n states. In the above formula some coefficient can be equal to zero, so there exist a constraint
bounding the possible states in which the system can exist. As observed in [4] – “Allowing d to be arbitrary enables
a tradeoff between the number of qudits making up the quantum computer and the number of levels in each qudit”.
An output of a gate is obtained by multiplying the unitary matrix of this gate by the vector of Hilbert space
corresponding to this gate’s input state. A resultant unitary matrix of arbitrary quantum circuit is created by matrix
or Kronecker multiplications of composing subcircuits. These all contribute to difficulty in understanding the
concepts of quantum computing and creating efficient analysis, simulation, verification and synthesis algorithms for
QC. Generally, however, we believe that much can be learned from the history of Electronic Computer Aided
Design as well as from MV logic theory and design, and the lessons learned there should be used to design efficient
CAD tools for MV quantum computing.
In terms of logic operations, anything that changes a vector of qudit states to another qudit satisfying
measurement probability properties can be considered as an operator (unitary matrix). These phenomena can be
modeled using the analogy of a “quantum circuit”. In a quantum circuit, wires do not carry ternary constants but
correspond to 3-tuples of complex values, , , and γ. Quantum logic gates of the circuit map the complex values on
their inputs to complex values on their outputs. As mentioned, operation of quantum gates is described by matrix
operations. Any quantum circuit is a composition of parallel and serial connections of blocks, from small to large.
Small blocks correspond to directly realizable quantum gates such as Feynman or Muthukrishnan/ Stroud gates.
Serial connection of blocks corresponds to multiplication of their (unitary) matrices. Parallel connection corresponds
to Kronecker multiplication of their matrices. So, theoretically, the analysis, simulation and verification are easy and
can be based on matrix methods. Practically they are tough because the dimensions of the matrices grow
exponentially. All these become much easier when one deals only with permutative matrices, which are equivalent
to multi-output truth tables of completely specified functions. We deal with such special class in this paper.
3
4. SOME TERNARY PERMUTATION GATES
Any unitary matrix represents a quantum gate. If a unitary matrix has only one 1 in every column and the
remaining elements are 0, then such a matrix is called a permutation matrix. A quantum gate represented by a
permutation matrix is called a permutation quantum gate. In this paper we concentrate only on permutation
quantum gates.
Figure 1 shows a 2*2 ternary Feynman gate, which is the ternary counterpart of the binary Feynman gate with
GF2 sum replaced by GF3 sum. Here A is the controlling input and B is the controlled input. The output P is equal to
the input A and the output Q is GF3 sum of A and B. Observe that GF3 sum is the same as modulo 3 sum. If B  0 ,
then Q  A and the ternary Feynman gate acts as a copying gate. The ternary 2*2 Feynman gate is practically
realizable, for instance see [4].
Six 1*1 ternary Shift gates are proposed in [16, 17]. Operations and symbols of these gates are shown in Figure
2. These gates are realizable using ternary quantum Feynman primitive [16, 17]. A Shift gate is said to be a mirror
gate of another Shift gate if the mirror gate is connected with the output of the original Shift gate, then the input
signal is restored. The mirror gates for all the Shift gates are shown in Figure 3. Two cascaded Shift gates can be
replaced by a single Shift gate as shown in Figure 4.
Gate Name
A
PA
B
Q  A B
Figure 1. 2*2 ternary Feynman gate.
Gate Symbol with
operaton*
Buffer
x
Single-Shift
x
Dual-Shift
Self-Shift
Self-Single-Shift
Gate No. to
refer in the text
x
0
'
x  x  1
1
x
''
x  x  2
2
x
'''
x  2 x
3
#
x  2x  1
4
x
#
5
x ^  2x  2
^
* Addition and multiplication are over GF3.
Self-Dual-Shift
x
Figure 2. Ternary Shift gates.
Original shift gate
Mirror gate
2nd gate
1st gat e
'
''
''
'
'''
'''
#
#
^
^
Figure 3. Mirror gates.
'
''
'''
#
^
'
''
'''
#
^
^
'''
#
#
^
'''
'
''
'
'
''
''
''
'''
'''
#
^
#
#
^
'''
''
^
^
'''
#
'
'
'
''
Figure 4. Equivalent Shift gates for two cascaded Shift
gates.
A very useful 2*2 gate called Generalized Ternary gate (GTG gate) is proposed in [9] as shown in Figure 5.
Here, input A is the controlling input and input B is the controlled input. The output P is equal to the input A. The
controlling input A controls a conceptual ternary multiplexer (a conditional gate) that can be realized using quantum
technology such as ion traps [4]. If A  0 , then the output Q is the x shift of the input B. Similarly, if A  1 , then the
output Q is the y shift of the input B and if A  2 , then the output Q is the z shift of the input B. Here shift means all
ternary shift operations including the Buffer (simple quantum wire). Readers should note that depending on the six
possible Shift gate for each of the three positions of x, y, and z, there are 63 = 216 possible GTG gates. As the
Conditional gate and the Shift gates are realizable in quantum technology, the GTG gate is a truly realizable ternary
quantum gate. For the purpose of this paper we assume that the GTG gate can be controlled from both top and
4
bottom as shown in Figure 6. It should be noted that if x  y  z  0 , then for all values of A, Q  B and the GTG
gate eventually becomes equivalent to two parallel wires as shown in Figure 7(a). Again, if A  0 and x  0 as in
Figure 7(b); if A  1 and y  0 as in Figure 7(c); and if A  2 and z  0 as in Figure 7(d), then the GTG gate also
becomes equivalent to two parallel wires. Two cascaded GTG gates can be replaced by a single equivalent GTG
gate as Shown in Figure 8 using the cascading rule of Figure 4. If x1 & x 2  y1 & y 2  z1 & z 2  0 , then the
equivalent GTG gate will be a wire-gate.
PA
A
B
x
0
y
1
z
2
 x shift of B if A  0

Q   y shift of B if A  1
 z shift of B if A  2

where x, y, z  {0, 1, 2, 3, 4, 5}
B
B
0
0
0
1
0
2
QB
0
0
y
1
z
2
(a)
B
x
0
0
1
z
2
(c)
QB
z
2
Q
B
y
1
z
2
Q
A
PA
(b) Control from bottom
x
0
y
1
0
2
PA
A
P2
2
B
1
0
QB
(b)
P 1
1
y
x
P0
0
B
0
Figure 6. Two different forms of controlling a
GTG gate.
Figure 5. 2*2 Generalized Ternary gates.
PA
x
(a) Control from top
are ternary shift operations
A
PA
A
QB
(d)
B
x1 0
x2 0
y1 1
y2 1
z1 2
z2 2
x1 & x 2  x;
Q
y 1 & y 2  y;
PA
A
B
x
0
y
1
z
2
Q
z 1 & z 2  z;
where & is cascade operator
Figure 8. Equivalent of two cascaded GTG gates. [& is
the cascading operator]
Figure 7. Some configurations of GTG gate that act
as two parallel wires.
A very useful gate for multiple input circuit synthesis is a 3*3 Toffoli gate as shown in Figure 9, which is the
ternary counterpart of the 3*3 binary Toffoli gate with GE2 product and sum are replaced by GF3 product and sum,
respectively. Design of GFSOP (Galois Field Sum of Products) arrays and factorized arrays is based on these gates.
These arrays are the multiple-valued counterpart of well-known binary ESOP (Exclusive-OR Sum of Products) and
factorized ESOP cascades. Here the inputs A and B are the controlling inputs and the input C is the controlled input.
The output P is equal to the input A, the output Q is equal to the input B, and the output R is equal to A  B  C ,
where  and + are GF3 multiplication and addition, respectively.
A generalized Ternary Toffoli gate is proposed in [17] as shown in Figure 10, where f k is an arbitrary ternary
function of the input variables A1 , A2 ,  , Ak . Here, there are k controlling inputs and n controlled inputs.
Any m*m (m > 2) gate is very difficult to realize in quantum technology, since interaction of more than two
particles is nearly impossible to control. Therefore, these gates should be realized from 1*1 and 2*2 gates. As
ternary Feynman gate and GTG gate are relatively easy to realize, they are treated as primitive gates for realizing
other gates. A generalized Toffoli gate is realizable from 1*1 Shift gates, 2*2 Feynman gate, and 2*2 GTG gate as
discussed in Section 9.
Some quantum technologies do not allow wire crossing. In those technologies, Swap gate plays an important
role. The schematic of a ternary Swap gate is shown in Figure 11. Realization of ternary Swap gate using GTG gates
is discussed in Section 10.
5
A
PA
A1
B
QB
Ak
C
R  AB  C
P1  A1
fk
Figure 9. Toffoli gate.
Pk  Ak
f k  arbitrary function of
A1 , A2 , , Ak
Ak 1
Pk 1  f k  Ak 1
Ak n
Pk  n  f k  Ak  n
A
B
B
A
Figure 11. Ternary Swap gate
Figure 10. A generalized ternary Toffoli gate.
5. GENERAL MODEL OF SYNTHESIZING MULTI-OUTPUT TERNARY FUNCTIONS USING
CASCADES OF GTG GATES
C ( A, B)  [0, 0, 0, 0, 0, 1, 0, 1, 1]T
Realization
of
ternary
half-adder
function
and
S ( A, B)  [0, 1, 2, 1, 2, 0, 2, 0, 1]T (which is a multi-output irreversible function) using cascade of GTG gates (which
is a reversible gate) is shown in Figure 12. Signal values at all intermediate wires are shown as maps to verify the
correctness of the circuit. In the proposed realization method an irreversible function is automatically converted into
a reversible one and is implemented using reversible GTG gates. In this realization we assumed the following:
(1) A GTG gate can be controlled either from top or from bottom.
(2) A limited vertical wire crossing for the controlling signals of GTG gates is allowed.
(3) Constant input signals 0, 1, or 2 are added as needed to help convert the irreversible function into reversible
one.
(4) Output may be realized along any primary input line or any constant input line.
(5) Each of the GTG gate form a column where the remaining lines represent quantum wires. The columns are
cascaded to realize the circuit.
B
A
0
1
2
Wire No
0
1
2
0
0
0
0
1
1
1
1
2
0
0
0
B
A
0
1
2
0
0
1
0
1
1
0
1
2
0
1
0
B
A
0
1
2
0
0
1
2
1
1
2
0
2
2
0
1
B
A
0
1
2
0
0
0
0
1
0
0
1
2
0
1
1
A
B
1
0
0
1
1
2
2
S
4
0
0
0
0
0
5
1
4
1
4
1
2
2
0
2
3
2
C
21452
20040
10012
21043
Numeric representation of columns (controlled wire no, controlling wire no,
x-shift, y-shift, z-shift)
Figure 12. Realization of ternary half-adder function C ( A, B)  [0, 0, 0, 0, 0, 1, 0, 1, 1]T and
S ( A, B)  [0, 1, 2, 1, 2, 0, 2, 0, 1]T using cascades of GTG gates.
6. PROPOSED EVOLUTIONARY ALGORITHM
6.1. Problem encoding
In the proposed evolutionary algorithm (EA) we use the model of synthesizing multi-output ternary function
using cascades of GTG gate as discussed in Section 5. In this circuit model, for initial input to the EA, we add three
constant input signals 0, 1, and 2 for up to m  n  3 outputs, where n is the number of inputs. For every increment
of 3 or less outputs, we add additional 3 constant input signals 0, 1, and 2. For example, if the function has 2 inputs
and 6 outputs, then we add 6 constant input signals 0, 1, 2, 0, 1, and 2. Then after convergence of the EA we
6
eliminate the unused constant input signals from the final circuit. Initially we take 2 3n columns (chromosome
length) as the input to the EA. After convergence of the EA we eliminate a column having all wires (i. e. a column
having a GTG gate representing two parallel wires) and other redundant columns as described in Subsection 7.1. We
also replace two cascaded GTG gates by their equivalent GTG gate as discussed in Subsection 7.2.
The primary input lines and the constant input lines are numbered starting from 0 as shown in Figure 12. Each
of the columns of the circuit is represented by an ordered tuple of controlled wire no, controlling wire no, x-shift, yshift, and z-shift of the associated GTG gate as shown in Figure 12. Using this notation the chromosome
representing the circuit of Figure 12 is as shown in Figure 13. Here each of the columns of the circuit is a gene of the
chromosome. In this problem encoding the genotype (chromosome) ties very closely with the phenotype (actual
circuit).
21452 20040 10012 21043
Figure 13. Chromosome representing the circuit of Figure 12.
6.2 Fitness Function
In the proposed EA, we tried to reduce the cost of the resulting circuit by (i) reducing the number of wires in the
circuit (the width of the scratchpad register), i. e. increasing the number of unused constant input lines, (ii) reducing
the number of non-wire columns, i. e. increasing the number of wire columns, (iii) reducing the number of nonbuffer Shift gates, i. e. increasing the buffer gates in the non-wire columns. For this reason we used four components
of the fitness function – (i) output truth vector fitness, (ii) width fitness, (iii) column fitness, and (iv) Shift-gate
fitness.
For determining the output truth vector fitness we group the truth values as stated in Definition 1.
Definition 1: Given an n-variable ternary function f represented as a truth vector, where the locations are designated
from 0 to 3 n  1 . The truth vector is partitioned into n types of sub-vectors, each type having a sub-vector length
3 n i consisting of consecutive truth values starting from location j 3 n  i for i  1, 2,, n and j  0, 1, , (3i  1) .
In this partitioning of the truth vector, i determines the length of a sub-vector and j determines the starting
location of the sub-vector. For example, if n  3 , then for i  1 the sub-vector length is 3ni  331  9 and
j  0, 1, (3i  1  31  1)  2 . So, the starting locations of the sub-vectors are 0, 9, and 18. Similarly, this partitioning
technique partitions the truth vector into sub-vectors of length 1 starting from locations 0, 1, 2, …, 3n  1 ; subvectors of length 3 starting from locations 0, 3, 9, …, 3n  3 ; sub-vectors of length 9 starting from locations 0, 9, 18,
…, 3n  9 and so on to sub-vectors of length 3 n 1 starting from location 0, 3 n 1 , and 2  3 n 1 .
Sub-vector fitness: The sub-vector fitness, for a given output m, for sub-vector type i (having sub-vector length
3 n i ) is defined as follows:
Sm,j = highest number of sub-vectors of type i for the output m realized along any wire/ 3 i .
When, for a given output m, a sub-vector of type i is completely realized, then S m , i  1 .
Individual output truth vector fitness: Individual output truth vector fitness for output m is defined as
follows:
n
Om = (if output m is completely realized along any wire, then 1, otherwise 0) +  S m,i .
i 1
When an output m is completely realized along a wire, then Om  1  n , since there are n types of sub-vectors.
Output truth vector fitness: The output truth vector fitness is defined as follows:
n
O =  Om .
m 1
When all m outputs are realized, then O  m(1  n) .
For finding the output truth vector fitness, we compute the resulting truth vector for all wires and then the bestfit wire is selected for a given output m.
Width fitness: The scratchpad width fitness is defined as follows:
W = number of unused constant input lines/Number of constant input lines.
Column fitness: The column fitness (or cascade length fitness) is defined as follows:
C = number of wire columns/length of the chromosome, L.
Shift-gate fitness: The Shift-gate fitness is defined as follows:
S = number of buffer gates in the non-wire columns/(3  number of non-wire columns).
7
In the current quantum technologies the scratchpad width is a major limitation. Therefore, if we can reduce the
width of the circuit, it will be more favorable. So, we give more selection pressure on width fitness. Reducing the
number of columns will reduce the cost of the circuit. So, we give moderate selection pressure on column fitness.
Finally, reducing the number of non-buffer Shift gates also reduce the cost of the circuit to some extent. So, we give
less selection pressure on Shift-gate fitness. Considering all these factors, we define the fitness function as follows:
F = O + 0.5W + 0.4C + 0.1S
From the fitness function, we can see that the value of (0.5W + 0.4C + 0.1S) will always be less than 1. On the other
hand, when all the m outputs are realized, then the value of O will be m(1  n) . Therefore, the threshold fitness
value is m(1  n) , that is, if the fitness of a chromosome is greater than m(1  n) , then that chromosome is a solution
for the given function.
6.3 Description of the evolutionary algorithm
As the model of our circuit synthesis (see Section 5) is not well structured, we want to make sure that the best
solutions found are not lost in the successive generations. Therefore, we use the simple steady-state GA with T-ary
tournament selection with replacement for selecting parents, classical crossover (one-point, two-point, and uniform)
operator, mutation operator (where the column or gene is replaced by a randomly generated column), and a new
problem specific gene repair operator (see Subsection 6.4). The proposed EA is shown in Figure 14. For a given set
of population size P, crossover probability PC, mutation probability PM, and tournament size T, we repeat the EA R
times with random seed. If for a given run of the EA, the fitness value does not improve within S consecutive
generations, then we stop that run and go to the next repetition with random seed. After all the R repetitions are
complete, we select the minimum solution of all the runs as the final solution. Then we apply the knowledge-based
post-EA local transformation as discussed in Section 7 to reduce the gate count of the solution.
6.4 Repair operation
From the circuit model of Figure 12, we see that, in the gene representation of a column, the wire numbers
representing the controlled signal and the controlling signal should be different. But if, during random generation of
the individuals of the initial population or after mutation of offspring, both the wire numbers of a gene become
same, then we make that column representing wires by setting x  y  z  0 . The motivation behind this repair
operation is to reduce the number of non-wire columns in the final solution. As our circuit model initially starts with
2 3n length, where n is the number of variables, reducing the number of non-wire columns will improve the quality
of the solution. For example, if a gene is 11012, then we make it 11000.
7. POST-EA ELIMINATION AND LOCAL TRANSFORMATION
7.1 Elimination of redundant columns
In the solution produced by the EA, some of the columns will be wire-columns. We eliminate all such wirecolumns from the solution to get the final solution. After elimination of the wire-columns, some of the columns may
be redundant. For example, the EA may produce (after the wire-columns have been eliminated) the circuit of Figure
15 for ternary half-adder function. The third and the fifth columns from the left are redundant, because they modify
the garbage outputs [5]. Therefore, we also eliminate such redundant columns from the solution to get the final
solution.
7.2 Knowledge-based local transformations
In the solution produced by the EA (after elimination of the redundant columns), GTG gates of two columns
may have the same controlling and controlled wires with no signal modification in between, with or without using
them for controlling the GTG gates of the intermediate columns. For example, the GTG gates of the 2 nd and the 4th
columns from the left of Figure 16(a) have the same controlling and controlled wires and the signal values of these
two wires are not changed in between these two columns. However, the top wire is used for controlling the GTG
gate of the 3rd column. These two GTG gates are effectively cascaded and they can be replaced by an equivalent
GTG gate using the cascading rules of Figure 4. The second gate of the cascade is replaced by the equivalent GTG
gate and the first one is made a wire gate as shown in Figure 16(b). After this replacement, the wire gate is
eliminated from the solution using the techniques of elimination of redundant columns.
8
A
Randomize seed
Generate initial population of size P having chromosome
n
length L  2  3, where n is the number of input variables
B
Repair genes of each individual if needed
1
Evaluate each individual
Select two individuals as parents using T-ary tournament
selection with replacement
0
0
1
1
2
2
0
0
1
1
3
2
S
4
0
0
0
0
0
5
1
4
1
4
1
2
2
0
2
3
2
2
0
0
5
1
2
2
C
redundant
redundant
With a high probability, PC, perform selected type crossover
on the parents to generate two offspring. If crossover is not
performed, then copy the parents unchanged to the offspring
Figure 15. Ternary half-adder circuit with redundant
columns.
Mutate the offspring with a small probability, PM
cascaded
Repair the genes of the offspring if needed
A
If offspring are duplicate of any other individual already in
population, then reject the offspring
B
Evaluate offspring
If the offspring are better than the worst individuals in the
population, then replace the two worst individual with the
offspring
Does the fitness value not improve
within S consecutive generations?
1
4
0
4
0
5
1
3
1
2
2
0
2
S
4
0
0
0
0
0
5
1
4
1
4
1
2
2
0
2
3
2
yes
C
(a) Ternary half-adder circuit with cascaded gates
A
no
no
Does the highest fitness eceed
the threshold value?
yes
B
yes
Is within R repetition?
no
Take minimum solution from all repetition
Eliminate redunadant columns
Figure 14. Flowchart of the proposed
evolutionary algorithm.
1
0
0
0
0
0
1
1
1
0
2
2
2
S
4
0
0
0
0
0
5
1
4
1
4
1
2
2
0
2
3
2
replaced by
wire gate
replaced by
equivalent gate
C
(a) Ternary half-adder circuit with cascaded gates replaced by equvalent gate
Figure 16. Replacing cascaded gates with equivalent
gate.
8. SYNTHESIS OF INCOMPLETELY SPECIFIED MULTI-OUTPUT TERNARY FUNCTIONS
For synthesizing an incompletely specified multi-output ternary function, we used the same EA as discussed in
Section 6, except the output truth vector fitness is calculated differently because don’t cares are ignored. Now, the
truth vector of a wire and the output function are compared only for cares and the don’t care positions are considered
as matches. Interestingly, this allows to simplify functions with more wires faster, when the percent of don’t cares is
high. We experimented with a randomly generated 2-input 3-output incompletely specified function
F0 ( A, B)  [3, 2, 1, 3, 1, 3, 2, 0, 1]T , F1 ( A, B)  [1, 2, 3, 2, 3, 3, 2, 0, 2]T , and F2 ( A, B)  [0, 0, 3, 0, 3, 1, 2, 2, 2]T , where
a 3 represents a don’t care output. The resulting circuit is shown in Figure 17. In the figure, intermediate signal
values are shown as maps to verify the correctness of the circuit, where the don’t care values are shown bold.
9. SYNTHESIS OF GENERALIZED TERNARY TOFFOLI GATE
For synthesis of generalized ternary Toffoli gate, we assumed that the controlling function of Figure 10 is
f k  A1 A2  Ak . This type of generalized ternary Toffoli gates are very useful for realization of ternary GFSOP
(Galois Field sum of products) cascades, which are ternary counterpart of classical binary ESOP (exclusive-OR sum
of products) circuits. For synthesizing a generalized ternary Toffoli gate of this type, we first realize the controlling
9
function f k  A1 A2  Ak as a cascade of GTG gates using our EA of Section 6 and then the controlled outputs are
realized using ternary Feynman gates. To restore the primary inputs and the constant inputs, mirror GTG gates are
used. We experimented with a generalized ternary Toffoli gate with 2 controlling inputs and 2 controlled inputs. The
resulting circuit is shown in Figure 18. In this figure, the left four columns generate the controlling function AB and
the right four columns are the mirror columns that restores the controlling inputs A and B and the constant input 2.
Intermediate signal values are shown as maps to verify the correctness of the circuit. The ternary Toffoli gate
realization of [18] requires 10 GTG gates, whereas our EA produces the circuit with 8 GTG gates, which is an
improvement over the previous result.
B
A 0 1
0 0 2
1 0 1
2 2 0
Bold entries
are don't care
B
A
0
1
2
2
1
2
1
0
2
2
1
1
1
1
2
B
A
0
1
2
2
1
1
1
0
1
2
2
1
2
0
0
B
A
0
1
2
2
2
0
2
A
B
3
0
0
1
2
2
0
0
0
2
1
1
0
1
B
A
0
1
2
2
1
0
2
0
0
0
2
1
0
0
2
2
0
3
0
3
1
0
1
4
2
4
2
2
1
1
2
F2
F0
1
3
0
3
0
0
1
4
1
0
2
1
2
F1
Figure 17. Circuit realizing an incompletely specified function F0 ( A, B)  [3, 2, 1, 3, 1, 3, 2, 0, 1]T ,
F1 ( A, B)  [1, 2, 3, 2, 3, 3, 2, 0, 2]T , and F2 ( A, B)  [0, 0, 3, 0, 3, 1, 2, 2, 2]T .
B
A
0
1
2
0
1
1
0
1
1
1
0
2
1
1
0
B
A
0
1
2
0
0
0
1
1
1
1
2
2
0
0
1
B
A
0
1
2
0
0
2
1
1
1
0
2
2
2
1
0
B
A
0
1
2
0
0
0
0
1
0
1
2
B
A
0
1
2
2
0
2
1
0
0
0
1
1
1
1
2
2
0
0
1
B
A
0
1
2
0
0
0
0
1
1
1
1
2
2
2
2
B
A
0
1
2
0
1
1
0
1
1
1
0
2 AB
1 0
1 1
0 2
0
2
2
2
1
2
2
2
2
2
2
2
A
PA
B
2
2
0
4
0
0
0
0
0
2
1
1
1
1
2
2
2
0
0
3
1
5
1
2
1
1
2
4
2
0
2
0
0
1
0
AB
QB
4
0
1
0
1
5
1
3
1
2
4
2
2
2
2
C
R  AB  C
D
S  AB  D
Figure 18. Realization of a generalized ternary Toffoli gate with f k  A1 A2  Ak .
10
10. SYNTHESIS OF TERNARY SWAP GATE
We synthesize ternary Swap gate using cascade of GTG gates using our EA of Section 6, except that no
constant input is used and the outputs are restricted to their corresponding wires. The resultant circuit is shown in
Figure 19. Our EA discovered a new and better solution for the ternary Swap gate, which had very inefficient
realizations [16-18].
B
A
0
1
2
A
B
0
2
0
1
1
1
2
0
2
0
1
2
B
A
0
1
2
0
0
1
2
1
0
1
2
2
0
1
2
B
A
0
1
2
0
0
0
0
1
1
1
1
2
0
5
0
1
1
3
1
0
2
4
2
1
0
2
1
0
2
2
2
2
2
B
A
Figure 19. Realization of ternary swap gate.
11. EXPERIMENTAL RESULTS
We have written C program to implement the proposed EA. We experimented with ternary half-adder function
for different EA parameters. In our experiment we used population size P = 50, 100, 150, 200, 250, 300; crossover
probability PC = 0.5, 0.6, 0.7, 0.8, 0.9, 1.0; and mutation probability PM = 0.02, 0.04, 0.06, 0.08, 0.10. We selected
two parents using tournament selection with replacement using tournament size T = 2, 4, 6, 8, 10. We also
experimented with three types of classical crossover techniques - one-point, two-point, and uniform crossover. For a
given set of P, PC, PM, and T, we repeated the EA for R = 50 times. If, for a given run, the fitness value does not
improve within S = 500 consecutive generations, we stopped the run and went to the next repetition. After all R = 50
repetitive runs are complete, we take the minimum solution over all runs as the final solution. Then we applied the
post-EA elimination and local transformation techniques to produce the final solution. The influence of the EA
parameters on the gate count of the final solution is shown in Figure 20. For this purpose, for a given EA parameter,
we averaged the gate count over the other EA parameters. For example, for finding out the average gate count for P
= 50, we averaged the gate count over 150 cases for P = 50; PC = 0.5, 0.6, 0.7, 0.8, 0.9, 1.0; PM = 0.02, 0.04, 0.06,
0.08, 0.10, and T = 2, 4, 6, 8, 10. From Figure 20, we see that uniform crossover performs better than the other two
crossover types. We also see from Figure 20 that P = 200, 250, 300; PC = 0.5, 0.6, 0.7; PM = 0.06, 0.08, 0.10; and T
= 6, 8, 10 produce better results.
In our experiments we found that some of the combinations of P, PC, PM, and T did not converge to a correct
solution within R = 50 replicated runs. The reason behind this non-convergence is the large search space of the
problem. From Section 4 we know that there are 216 GTG gates. Any of these gates can be placed in any columns
and this gate can be placed across any two wires in both top-control or bottom-control modes. For example, for
ternary half-adder function the number of inputs is n = 2 and the number of outputs is m = 2  n + 3. So, we need n
+ 3 = 5 wires in the solution model. Therefore, we have n  3 P2  5 P2  20 possible connections across two wires from
five wires. Therefore, we have 216  n  3 P2  216  20  4320 possibilities of GTG gates placement in a column. Our
solution model has 2 3n columns. So, for n = 2, we have 18 columns. The size of possible solution space is
n
(216  n  3 P2 ) 23 and for n = 2, this value is 2.7460410 65 . Some of these huge solution spaces include the correct
solutions. Therefore, the EA needs to go through a large search space and for R = 50 and S = 500 the EA fails to
converge to a correct solution. The convergence rate (%) for ternary half-adder function is shown in Figure 21.
Again for this figure, for a given parameter we calculated the convergence rate over all values of the other
parameters. From this figure we see that 2-point crossover performs better than the other two types of crossover.
11
8.5
averageg gates
average gates
8.6
8.4
8.2
8
7.8
7.6
7.4
7.2
8
7.5
7
50
100
150
200
250
300
0.5
0.6
0.7
population size
1-point
2-point
0.9
1
uniform
8.5
average gates
9
average gate
0.8
crossover probability
8.5
8
7.5
0.02
8
7.5
0.04
0.06
0.08
0.1
2
4
mutation probabilty
6
8
10
tournament size
100
95
90
85
80
75
70
convergence rate %
convergance rate %
Figure 20. Influence of EA parameters and crossover type on average gate count for half-adder circuit.
50
100
150
200
250
100
95
90
85
80
75
300
0.5
0.6
population size
2-point
100
convergence rate %
convergence rate %
1-point
95
90
85
80
75
0.02
0.04
0.06
mutation probability
0.7
0.8
0.9
1
crossover probability
0.08
0.1
uniform
100
95
90
85
80
75
70
65
60
2
4
6
8
10
tournament size
Figure 21. Influence of EA parameters and crossover type on convergence rate for half-adder circuit.
We also experimented with some other ternary benchmark functions [25]. For these experiments we used two
types of crossover - 2-point and uniform crossover; P = 200, 250, 300; PC = 0.5, 0.6, 0.7; PM = 0.06, 0.08, 0.1; T = 6,
8, 10; R = 50; and S = 500 to 5,000. Many of these parameter settings did not converge to correct solution. The
minimum solution from the successful runs is reported in Table 1. The table also shows the results from [15] for
comparison. Columns 1, 2, and 3 show the function name, number of inputs, and number of outputs, respectively.
Column 4 and 5 show the number of GTG gates and circuit width, respectively, produced by our EA. Columns 6 and
12
7 show the number of GTG gate and circuit width, respectively, from [15]. From Table 1it is clear that the solution
produced by our EA is much better than the results from [15].
Function
prod2
prod3
prod4
sum2
sum3
sum4
3cy2
4cy2
4cy3
sqsum2
sqsum3
sqsum4
avg2
avg3
avg4
a2bcc
thadd
tfadd
mul2
mul3
mami4
mm3
pal3
swap
Input
2
3
4
2
3
4
3
4
4
2
3
4
2
3
4
3
2
3
2
3
4
5
6
2
Table 1. Experimental results.
Our Result
Output
Gate
Width
1
4
3
1
13
6
1
?
?
1
1
2
1
2
3
1
3
4
1
14
5
1
13
7
1
?
?
1
2
3
1
3
4
1
4
5
1
3
3
1
8
5
1
?
?
1
6
4
2
4
3
2
11
5
2
5
4
2
?
?
2
14
7
1
?
?
1
?
?
2
3
2
Result from [15]
Width
9
6
25
14
63
32
18
9
90
40
51
24
171
78
8
6
36
18
69
34
9
6
36
18
119
55
33
17
-
Gate
10. CONCLUSIONS
GTG gate was proposed in [18] without giving any synthesis algorithm to synthesize from all these gates
directly. In this paper we propose an EA for synthesizing both completely and incompletely specified irreversible
ternary functions using a cascade of GTG gates. The synthesis method automatically converts the irreversible
function into reversible one and realizes that by cascade of GTG gates.
Generalized ternary Toffoli gate and ternary Swap gate were synthesized as well as many benchmark functions
from recent literature. The generalized ternary Toffoli gate realization proposed in [18] requires 10 GTG gates,
whereas the realization of this paper requires 8 GTG gates. Similarly, previous best design of ternary Swap gate [1618] had 4 Feynman gates and one 1-qubit permutative gate. The new design has only 3 GTG gates and is very
elegant, it has the same symmetry as the well-known design of Swap from Feynman gates in binary, so we can say
that the EA has done certain “discovery”.
The synthesis method of [15] uses a subset of the GTG gate family and synthesizes only single-output ternary
functions. Table 1 shows that our EA produces much better solutions than that from [15]. Moreover, our EA can
synthesize multi-output ternary functions in comparison to the single-output function from [15]. However, the
method of [15] is a fast method and as usual our EA method requires long time to produce good result. But as many
logic synthesis applications are not real time applications and solution quality is more important than the time
required to produce the solution.
The methods of [12-14] used a different set of gates and can not be compared with our results. The papers [12,
13] discussed implementation of all 2*2 reversible functions and reported solution of only one irreversible function the ternary full adder. This solution requires four 4*4 gates, eight 3*3 gates, and four 2*2 gates totaling 16 gates. On
the other hand, our EA produces ternary full adder circuit using only 11 2*2 gates. In general, any m*m (m > 2) gate
is very difficult to realize in quantum technology, since interaction of more than two particles is nearly impossible to
control. Therefore, these gates should be realized from 1*1 and 2*2 gates. Considering this fact, our solution is
better than the solution from [12, 13].
13
Other circuits are realized using cascade of GTG gates for the first time and, therefore, cannot be compared with
other results.
11. FUTURE WORK
Our first goal is to extend this work to fully quantum circuits, the ternary counterparts of binary circuits
synthesized in [5-8]. This will require to change the internal representation of cascades from truth tables to unitary
matrices with complex numbers in the fitness function. Our preliminary current work includes 1-qudit Chrestenson
gate as a ternary equivalent of Hadamard gate, phase gates with angles corresponding to ternary logic, and ternary
generalizations of Pauli rotations, and the corresponding controlled 2-qudit gates. The goal would be to synthesize
automatically some known ternary circuits such as: the gates from [12], ternary EPR circuits, and ternary spectral
transforms that generalize quantum Fourier Transform [1, 2, 3].
Another area of future research is further improvement of the EA to a broader class of evolutionary algorithms
like the memetic algorithms and the algorithms that use various local search subroutines [5]. We plan to develop
EAs for synthesizing both completely and incompletely specified multi-output ternary function using a similar
cascade of 2*2 ternary Feynman gate (Feynman gate is linear and it is a special case of GTG gate). Similarly as in
[5, 12-14, 19], future research will also add powerful local transformations of circuits based on ternary quantum
identities, to decrease the cost of the synthesized cascades. In binary quantum the improvements of costs are
sometimes as dramatic as 300% [5], which demonstrated that it is a good idea to combine evolutionary and
algorithmic rule-based approaches into one working program for quantum circuit synthesis. Finally we will compare
all existing algorithms for ternary quantum synthesis [12-17, 19] using the same types of gates, possibly the lowlevel quantum primitives such as controlled-Chrestenson-like gates [19].
11. REFERENCES
[1] Nielsen, M., Chuang, I. (2000). Quantum Computation and Quantum Information. Cambridge University Press.
[2] Hirvensalo, M. (2001). Quantum Computing. Springer Verlag, 2001.
[3] Williams, C.P., Clearwater, S.H. (1998). Explorations in Quantum Computing. New York:Springer-Verlag.
[4] Muthukrishnan, A., Stroud, Jr., C. R. (2000). Multivalued logic gates for quantum computation. Physical
Review A, Vol. 62, No. 5, 052309/1-8.
[5] Lukac, M., Perkowski, M., Goi, H., Pivtoraiko, M., Yu, C.H., Chung, K., Jee, H., Kim, B-G., Kim, Y-D.
(2003). Evolutionary approach to Quantum and Reversible Circuits synthesis. Artificial Intelligence Review,
Kluwer Academic Publishers, 20, pp. 361-417.
[6] Ge, Y. Z., Watson, L. T., Collins, E. G. (1998). Genetic algorithms for optimization on a quantum computer. In
Unconventional Models of Computation, London:Springer Verlag, pp. 218-227.
[7] Yabuki, T., Iba, H. (2000). Genetic algorithms and quantum circuit design, evolving a simpler teleportation
circuit. In Late Breaking Papers at the 2000 Genetic and Evolutionary Computation Conference, pp. 421-425.
[8] Spector, L., Barnum, H., Bernstein, H.J., Swamy, N. (1999). Finding a better-than-classical quantum AND/OR
algorithm using genetic programming. Proc. 1999 Congress on Evolutionary Computation, Vol. 3, Washington
DC, 6-9 July 1999, IEEE, Piscataway, NJ, pp. 2239-2246.
[9] Han, K-H., Kim, J-H. (2002). Quntum-inspired evolutionary algorithm for a class of combinatorial
optimization. IEEE Trans. Evolutionary Computation, 6(6), pp. 58-593.
[10] Al-Rabadi, A. (2002). Novel Methods for Reversible Logic Synthesis and Their Application to Quantum
Computing. Ph. D. Thesis, PSU, Portland, Oregon, USA.
[11] Al-Rabadi, A., Perkowski, M. (2001). Multiple-Valued Galois Field S/D Trees for GFSOP Minimization and
their Complexity. Proc. 31st IEEE Int. Symp. on Multiple-Valued Logic, Warsaw, Poland, May 22-24, 2001, pp.
159-166.
[12] Miller, D.M., Maslov, D., Dueck, G.W. (2004). Synthesis of Quantum Multiple-Valued Circuits. Submitted to
Journal of Multiple-Valued Logic and Soft Compution.
[13] )Miller, D.M., Dueck, G., Maslov, D. (2004). A Synthesis Method for MVL reversible logic. Proc. 34th IEEE
Int. Symp. On Multiple-Valued Logic, Toronto, Canada, May 19-22, 2004.
[14] Curtis, E., Perkowski, M. (2004). A Transformation Based Algorithm for Ternary Reversible Logic Synthesis
using Universally Controlled Ternary Gates. Proc. IWLS 2004. Tamecula, California, June 2 – 4, 2004.
[15] Denler, N., Yen, B., Perkowski, M., Kerntopf, P. (2004). Synthesis of Reversible Circuits from a Subset of
Muthukrishnan-Stroud Quantum Multi-Valued Gates. Proc. IWLS 2004. Tamecula, California, June 2 – 4,
2004.
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[16] Khan, M.H.A., Perkowski, M.A., Kerntopf, P. (2003). Multi-Output Galois Field Sum of Products Synthesis
with New Quantum Cascades. Proc. 33rd IEEE Int. Symp. On Multiple-Valued Logic, Tokyo, Japan, May 16-19,
2003, pp. 146-153.
[17] Khan, M.H.A., Perkowski, M.A., Khan, M.R., Kerntopf, P. (2004). Ternary GFSOP Minimization using
Kronecker Decision Diagrams and Their Synthesis with Quantum Cascades. Journal of Multiple-Valued Logic
and Soft Computing: Special Issue to Recognize T. Higuchi’s Contribution to Multiple-Valued VLSI Computing.
To appear.
[18] Perkowski, M., Al-Rabadi, A., Kerntopf, P. (2002). Multiple-Valued Quantum Logic Synthesis. Proc. of 2002
International Symposium on New Paradigm VLSI Computing, Sendai, Japan, December 12-14, 2002, pp. 41-47.
[19] Perkowski, M., Kerntopf, P., Al.-Rabadi, A., Khan, M. H. A. (2002). Multiple-Valued Quantum Computing.
Issues, Open Problems, Solutions. Technical Report, KAIST, Taejeon, Korea.
[20] Brylinski, J. L., Brylinski, R. (2002). Universal Quantum Gates. Mathematics of Quantum Computation, CRC
Press, LANL e-print quant-ph/010862.
[21] Michalewicz, Z. (1996). Genetic Algorithms + Data Structures = Evolution Programs (3rd edn). Springer.
[22] Goldberg, D. E. (1989). Genetic Algorithms in Search, Optimization, and Machine Learning. Addison Wesley.
[23] Mazumder, P., Rudnick, E.M. (2002). Genetic Algorithms for VLSI Design, Layout & Test Automation. Pearson
Education Asia.
[24] De Vos, A., Raa, B., Storme, L. (2002). Generating the group of reversible logic gates. Journal of Physics A:
Mathematical and General, Vol. 35, pp. 7063-7078.
[25] Marek, please post the ternary benchmark definitions in a web page under your home page and give that address
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