嵌入式系統設計
軟硬體高階合成
HW/SW High-Level Synthesis
陳慶瀚
機器智慧與自動化技術(MIAT)實驗室
國立中央大學資工系
2015年5月12日
硬體高階合成
library IEEE;
use IEEE.std_logic_1164.all;
entity DEMO1 is
port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
S1: in STD_LOGIC;
S2: in STD_LOGIC;
S3: in STD_LOGIC;
A1: out STD_LOGIC;
A2: out STD_LOGIC;
A3: out STD_LOGIC
);
end DEMO1;
architecture DEMO1_arch of DEMO1 is
signal X1,X2,X3:STD_LOGIC;
begin
process(CLK)
begin
if RESET='1' then
X1<='1';
X2<='0';
x3<='0';
elsif CLK'EVENT and CLK='1' then
if X1='1' and S1='1'
if X2='1' and S2='1'
If X3='1' and S3='1'
then
then
then
X1<='0';X2<='1'; end if;
X2<='0';X3<='1'; end if;
X3<='0';X1<='1'; end if;
end if;
A1<=X1;
A2<=x2;
A3<=X3;
end process;
end DEMO1_arch;
(c)
HDL Code
軟體高階合成
Software Synthesis
void main( )
{
while(1)
{
grafcet( );
}
}
void grafcet( )
{
if(…){}
action();
}
void action( )
{
if(x1==1){…}
if(x2==1){…}
…
}
C Code
Harware Synthesis Model of Grafcet
VHDL synthesis of Grafcet
Fundamental Block
X0
A0
R0
Xn
An
if X0='1' and R0='1' then X0<='0'; Xn<='1';
end if;
A0 <= X0 ;
An <= Xn ;
VHDL synthesis of Grafcet
Convergence AND
X0
A0
X1
A1
R0
Xn
An
if X0='1' and X1='1' and R0='1' then X0<='0'; X1<='0'; Xn<='1';
end if;
A0 <= X0 ;
A1 <= X1 ;
An <= Xn ;
VHDL synthesis of Grafcet
Divergence AND
X0
A0
R0
X1
A1
Xn
An
if X0='1' and R0='1' then X0<='0'; X1 <='1'; Xn<='1';
end if;
A0 <= X0 ;
A1 <= X1 ;
An <= Xn ;
VHDL synthesis of Grafcet
Convergence OR
X0
A0
R0
Xn
X1
A1
R1
An
if X0='1' and R0='1' then X0<='0'; Xn <='1';
elsif X1='1' and R1='1' then X1<='0'; Xn <='1';
end if;
A0 <= X0 ;
A1 <= X1 ;
An <= Xn ;
VHDL synthesis of Grafcet
Divergence OR
X0
A0
R0
X1
R1
A1
Xn
An
if X0='1' and R0='1' then X0<='0'; X1 <='1';
elsif X0='1' and R1='1' then X0<='0'; Xn <='1';
end if;
A0 <= X0 ;
A1 <= X1 ;
An <= Xn ;
VHDL template
VHDL code of Grafcet Controller
library IEEE;
use IEEE.std_logic_1164.all;
entity DEMO1 is
port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
S1: in STD_LOGIC;
S2: in STD_LOGIC;
S3: in STD_LOGIC;
A1: out STD_LOGIC;
A2: out STD_LOGIC;
A3: out STD_LOGIC
);
end DEMO1;
architecture DEMO1_arch of DEMO1 is
signal X1,X2,X3:STD_LOGIC;
begin
process(CLK)
begin
if RESET='1' then
X1<='1';
X2<='0';
x3<='0';
elsif CLK'EVENT and CLK='1' then
if X1='1' and S1='1'
if X2='1' and S2='1'
If X3='1' and S3='1'
end if;
A1<=X1;
A2<=x2;
A3<=X3;
end process;
end DEMO1_arch;
then
then
then
X1<='0';X2<='1'; end if;
X2<='0';X3<='1'; end if;
X3<='0';X1<='1'; end if;
Synthesis of Grafcet Controller
X1
A1=1
S1
X2
A2=1
S2
X3
A3=1
S3
(a)
(b)
Software Synthesis Model of Grafcet
Software
Synthesis
C code
C synthesis of Grafcet
Fundamental Block
X0
A0
R0
Xn
An
if((X0==1)&&(R0==1))
{
X0=0;
X1=1;
}
if X0='1' and R0='1
end if;
A0 <= X0 ;
An <= Xn ;
C synthesis of Grafcet
Convergence AND
X0
A0
X1
A1
R0
Xn
An
if X0='1' and X1='1' and R0='1' then X0<='0'; X1<='0'; Xn<='1';
if((X0==1)&&
(X1==1)&&(R0==1))
end if;
{
A0 <= X0 ;
X0=0;
A1 <= X1 ;
AnX1=0;
<= Xn ;
X1=1;
}
C synthesis of Grafcet
Divergence AND
X0
A0
R0
X1
A1
Xn
An
if((X0==1)&&(R0==1))
{ if X0='1' and R0='1' then X0<='0'; X1 <='1'; Xn<='1';
end if;X0=0;
X1=1;
A0 <=Xn=1;
X0 ;
} A1 <= X1 ;
An <= Xn ;
C synthesis of Grafcet
Convergence OR
X0
A0
R0
Xn
X1
A1
R1
An
if((X0==1)&&
(R0==1))
if X0='1' and R0='1' then X0<='0'; Xn <='1';
{ elsif X1='1' and R1='1' then X1<='0'; Xn <='1';
end if; X0=0;
A0 <= Xn=1;
X0 ;
} A1 <= X1 ;
An <= Xn ;
if((X1==1)&&
(R1==1))
{
X1=0;
Xn=1;
}
C synthesis of Grafcet
Divergence OR
A0
X0
R1
R0
X1
A1
Xn
An
if X0='1' and R0='1' then X0<='0'; X1 <='1';
elsif X0='1' and R1='1' then X0<='0'; Xn <='1';
end if;
A0 <= X0 ;
A1 <= X1 ;
An <= Xn ;
If(X0==1)
{
if(R0==1))
{
X0=0;
X1=1;
}
else if(R1==1)
{
X1=0;
Xn=1;
}
}
C code Synthesis of Grafcet Model
Software Synthesis
void main( )
{
while(1)
{
grafcet( );
}
}
void grafcet( )
{
if(…){}
action();
}
void action( )
{
if(x1==1){…}
if(x2==1){…}
…
}
C Code