ALCT firmware

ALCT firmware
A. Madorsky
University of Florida
ALCT trigger logic structure
Input demultiplexor
Pulse extender
Pattern detector
Ghost cancellation
Best pattern selector
Output multiplexor
TAMU workshop A. Madorsky
Input demultiplexor
 Wiregroup hits come multiplexed at 80 MHz, 2 frames
 Input demux unwraps them into a single 40 MHz frame
Input bit
CLK 80 MHz
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Output bits
CLK 40 MHz
Pulse extender
 Wiregroup hits extended
 Allows for overlap with extended hits from other wiregroups
Original hits
Extended hits
TAMU workshop A. Madorsky
Pattern detector
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Detects patterns tied to one key wire group in layer 3
Collision patterns are programmable within envelope
Collision and halo patterns detected independently
During entire first LHC run, collision patterns was matching envelope
Each pattern detector has dead time after valid pattern detection
 6 clocks
 NOT entire ALCT, dead time is per pattern detector
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layers hit
Quality code
<=3
0
4
1
5
2
6
TAMU workshop
A. Madorsky
3
Key wire group
Collision pattern
envelope
Programmed collision
pattern example
= wiregroup
Fixed halo pattern
= wiregroup enabled for detection
Ghost Cancellation Logic
 Patterns next to actual track often fire with lower quality
 GCL removes lower-quality neighbors of better quality patterns
Including delayed ghosts
Ghost creation mechanism example
Cancellation examples
BX 0
BX 1
BX 2
Ghost
Q=0
Better pattern
Q=3
= inactive pattern key wiregroup
= wiregroup
= good quality pattern key wiregroup
= wiregroup that’s been hit
= worse quality pattern key wiregroup
TAMU workshop A. Madorsky
Best pattern selector
 Receives quality codes from pattern detectors
32, 48, 64, 96, or 112 codes depending on chamber type
 Finds two best patterns on each BX
 “Colliding” search algorithm
Single clock latency
First best search direction
Second best pattern
Second best search direction
First best pattern
= inactive pattern key wiregroup
= good quality pattern key wiregroup
= worse quality pattern key wiregroup
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Output multiplexor
 Sends data to TMB in two frames at 80 MHz
 Also includes TMB link diagnostic and error correction circuitry
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Latency
Algorithm step
Latency, BX
Input demultiplexor
1.5
Drift delay (programmable)
3
Pattern detection and GCL
1
Best track selection
1
Output encoding and multiplexor
2
Total
8.5
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Possible improvements
From Vadim Khotilovich:
Use narrower patterns for ME1/1 chambers
Patterns are programmable in current firmware
No f/w modifications necessary, just reprogram the patterns
Modify Ghost Cancellation
Disable removing higher-quality patterns because of earlier low-quality
patterns in the vicinity
Will increase latency by 3 clocks
Reduce dead time in pattern detector
Currently 6 clocks
All the above should be possible even in Virtex-E firmware
TAMU workshop A. Madorsky
Possible improvements in Spartan-6
 Stub timing is currently defined by pre-trigger (V. Khotilovich)
First 3 or 4 hits arriving = pre-trigger
Proposed to measure timing by median time of hits in wiregroups
Need more details on this
 Multiple collision patterns
Second collision pattern used to exist in firmware for Virtex-E
 Have been removed as unnecessary
May be useful in the future
 Deeper DAQ buffer
Very straightforward
 Suggestions are welcomed
TAMU workshop A. Madorsky