Modified RSD Analog Digital Converter
with BIST Technology
RADIMIR VRBA1 - IVO VECERA2 – JAN LUDVIK1
Department of Microelectronics, Brno University of Technology, 2SCG CDC
1
Udolni 53, CZ-60200 Brno, 2B. Nemcove 1720, 756 61 Roznov pod Radhostem
CZECH REPUBLIC
1
2
[email protected] http://www.vutbr.cz
[email protected] http://www.onsemi.com
1
Abstract: - Paper deals with pipelined switched-current A/D converter designed in 0.6 μm BiCMOS technology with
embedded BIST features. Modified RSD redundant-sign-digit conventional-restoring algorithm was implemented what
decreases the amount of high-precision components. By changing from pipeline conversion to cycling mode, less
power dissipation is obtained at the expense of conversion time (less than 1 μA current consumption in sleep mode).
Since the switched-current structure changes the mode of operation of current copiers, large fault coverage can be
reached if creating proper design-for-test. Proposed A/D converter is suitable for conversion of the current with very
low amplitude from analog into digital domain. Current mode enables operation down to 3V thus is suitable for battery
powered applications. The system integrates band-gap reference and independent supervisory circuit with 1% accuracy.
A/D converter is prepared to meet 1451.2 specifications. The models developed were utilized and SPICE simulations
performed to verify theoretical proposals.
Key-Words: - current mode, A/D converter, RSD redundant-sign-digit, pipeline architecture, BiCMOS, BIST.
1 Introduction
A lot of work is being done in the field of analog-todigital conversion. The steering factor is definitely a
rapid accession of low-cost microcontrollers and DSP’s
in analog signal world.
Low input impedance is the advantage of current mode
compared to voltage mode due to increased noise
immunity. It makes such approach suitable for
processing of sensor signals.
Current processing is based on current mirrors [1], [2].
In CMOS technology where their use is significant, the
design must be very careful according to mismatch thus
their required large dimensions can become limiting
factors when speaking of the die size.
Switched-current techniques overcome this side effect
since the mirroring is done on one MOS transistor and
the only resolution of the gate-charge sampling is
important.
On the contrary to most voltage-mode types of
converters, switched-current technique does not require
VOLTAGE
REFERENCE
VOLTAGE
SUPERVISOR
MSB
CLOCK
GENERATOR
SENSOR
MSB
-1
MSB
-2
+
…
LSB
+1
LSB
TRANSDUCER
INDEPENDENT
INTERFACE
U/I
DATA PROCESSING
CONTROL
LOGIC
ADC
mode
cycling
pipeline
Figure 1: Block diagram of the proposed algorithmic
A/D converter
either high precision resistors or capacitors thus it is
compatible with standard CMOS processes.
This paper describes pipelined switched-current A/D
converter designed in 0.6μm BiCMOS technology.
Modified conventional-restoring algorithm, called
redundant-sign-digit (RSD), was implemented what
decreases the amount of high-precision components.
Two modes of operation are possible. By changing from
pipeline conversion to cycling mode, less power
dissipation is obtained at the expense of conversion time.
Proposed A/D converter (Fig. 1) is suitable for
conversion of the current with very low amplitude from
analog into digital domain. Current mode enables
operation down to 3 V supply suitable for battery power.
The system integrates band-gap reference and
independent supervisory circuit with 1 % accuracy.
Current consumption in sleep mode is less than 1 μA.
A/D converter is prepared to meet 1451.2 specifications.
2 IC Testing
Testing has not been still solved exhaustively because the
development of new technologies and increasing of the
scale of the integration are rising more rapidly then
techniques (and also standards) ensuring an acceptable
fault test coverage. It seems rather difficult to choose the
right method when testing analog or mixed-signal circuits
comparing to digital where the scan-based structures
appear in the most microprocessor designs, for instance.
Moreover, in mixed-signal IC’s tests are using standard
industrial hardware testing equipment.
C
current sources
M1
P-cell
I out = 2I in
S
6
input
from sensor
to the next
cell
N-cell
N-cell
I II III
SR
buffer
S1
S2
out
I in
S7
The related costs are more proportional to the size of
analog portion of the design. Therefore a lot of effort
focuses on development of new test principles, methods,
environments and tools for analogs' application domains.
Self-test methods call for few added functional blocks
and for design for testability (DFT) approach. The goal
is to obtain proper diagnosability of faults present in the
circuit by defect analysis with use of fault models. In
analog circuits, according to the application
requirements, different testing techniques must be used.
Presented paper deals with testing of an algorithmic A/D
converter operating in switched-current mode. From the
test point of view, either on-line test or off-line test can
be applied and further, self-calibration of the system is
performed just during the precise off-line test.
3 RSD A/D converter
Algorithmic current-mode A/D converters are based on the
multiply-by-two method what can be seen from the Eq. 1,
where q is a quantizing step and YFS is a full-scale input
signal.
N 1
i 0
S
5
YFS N 1
2 
2N

1
1

  a N 1   a N  2  ...  a 0  ; a i  0,1
2
2


(1)
The way to multiply input current by two is shown in Fig.
2 and Fig. 3. First, the input current Iin is stored in
transistor M1 and in the next two clock periods stored
current is shifted into transistors M2, M3. This is so called
conventional restoring (CR) algorithm, in voltageequivalent A/D converters known as successive
approximation technique.
The Redundant-Sign-Digit (RSD) algorithmic A/D
converters, derived from the CR algorithm, are based on
the
Sweeny-Robertson-Tocher
numerical-division
principle.
S8
M2
M3
C
Figure 2: One cell of N-bit switched-current RSD A/D
converter (pipeline structure)
Y  q ai 2 i 
S3
S
4
data
C
Figure 3: Basic principle of the multiply-by-two SI memory cell
The RSD coding, which is well known from digital
multiplier coding, uses special algorithms (Booth). After
multiplication by two, the signal to be converted is
compared with two non-critical levels -- P and Q -- instead
of a single critical level as in the Conventional Restoring
(CR) principle. Those comparison levels P and Q are
arbitrary but can best be chosen as half as the full-range
signal.
Comparison proceeds algorithmically from MSB to LSB
and according to the output code digits, the current
reference must be subtracted according to
I i  2 I i 1  bi I ref
(2)
In this case bi may take the values 2, 1 or 0, and Ii-1
means incoming current and Ii is outgoing one. It can be
shown that modifications of the P and Q levels, although
they affect the sequence of '2', '1', '0' digits, do not
change the representation of the converted signal.
The Redundant Sign Digit (RSD) algorithm can be
successfully applied to cyclic and pipeline analog-todigital converters. It is superior to the Conventional
Restoring (CR) algorithm regarding from cancellation of
offset errors, speed and an additional bit.
4 BIST features for SI circuits
In the case of A/D converter, stochastic processed current
from input stimuli will change the value of the current in
the memory cells. The purpose of testability of the A/D
converter is to detect all possible faults which can appear
in the structure. Two modes of testing are possible in the
proposed structure:
*
on-line test mode,
*
off-line test mode.
Both modes differ from the way they detect the
malfunction of the circuit and the separate analysis was
performed. Under the assumption that MOS transistor
faults can be modeled by stuck-at/stuck-open fault model
(Fig. 3), a set of analyses for each transistor must be
performed to cover most frequently used faults
Simulated results of the transient behavior of the internal
potentials in RSD A/D converter cell show three main
types of the response: top plot indicates that if not smart
detection is used then collapsed circuit cannot be
detected. Middle one represents only a very week
divergence from expected response; in this case the
abnormality cannot be detected. The bottom plot shows
fully detectable fault when the potential went out of the
expected range.
was designed in 0.6 μm BiCMOS technology and the
example of the simulated results is shown in Fig. 6.
Bottom left picture shows copying of the current in the
P-memory cell (M1) during phase Φ1 and in the middle
and top there is sampling of the gate-charge on the
transistors M2 and M3, respectively.
VDD
BIAS
15uA
VDD
REFERENCE
50uA
Refreshing
VDD
Ibias
Ibias
O2
O1
Comparator
part
Iinput
Figure 5: Decrease in area of the cycling conversion
structure of the A/D converter (black-white border)
compared to pipelined one
O1
Iref
O2
CELL
1
(W/L)1
(W/L)2
CELL
2
Vcomp
VSS
BIAS
15uA
VSS
Analog window comparator
Figure 4: On-line testing of node voltages inside one cell
of an algorithmic A/D converter (an analog part)
5 Conclusion
Built-in self test (BIST) topology can be employed in the
proposed structure of the converter. Current-copier cells
are added to the circuit to ensure its controllability. This
is general testing approach for analog circuits in
switched-current mode. If full-scale signal is brought to
the input of the converter, the sequence of all ones (1111
... 11) is expected in the array of digital data. In the
opposite, if the zero signal is fed into the converter then
all zeros (0000 ... 00) are anticipated at the output of the
converter.
Algorithmic ADC, moreover, allows the measure of the
non-linearity over the full scale by applying random
signal to the input of the ADC. The signal is in each cell
multiplied by two and known value is assumed to be
subtracted. Thus if the conversion process is repeated
longer than N times (for N-bit resolution), the image
about resolution of the converter can be reached from the
real response to those test signals. Let’s consider random
input signal, for example 100.1 LSB. Comparison levels
P and Q are 480 and 530 LSB, respectively. Reference
value to be subtracted is 512 and 1024 LSB,
respectively. Proposed RSD algorithmic A/D converter
Right panel displays corresponding propagation of the
current: The input current is stored in M1 memory cell
during time frame I, it is copied onto M2 and M3
transistors during II and III and them doubled signal is
sent back into M1 again with no subtraction during IV.
Simulation results show that for input currents in the
range between 0 and 10 μA and bias current of 1 μA, 9bit resolution can be achieved at sampling rate up to
200kHz.
References
[1] C. Toumazou, F. J. Lidgey, D. J. Haigh, 'Analog IC
Design: the Current-Mode Approach', Peter
Peregrinus Ltd., London, 1990.
[2] T. S. Fiez, G. Liang, D. J. Allstot, 'SwitchedCurrent Circuit Design Issues', IEEE JSSC, Vol. 26,
pp. 192-201, March 1991.
[3] N. Tan, 'Switched-current delta-sigma A/D
converters', Analog IntegratedCircuits and Signal
Processing, vol. 9, no. 1, pp. 7–24, Jan.1996.
[4] F. Cennamo, P. Daponte, L. Michaeli, 'Introduction
to special issue on ADC modelling and testing',
Computer Standards & Interf. 19 (1998) 169-171.
[5] P. N’Goran and A. Kaiser, 'A building block
approach to the design and simulation of complex
current memory circuits', Analog Int.Circuits and
Signal Proc., vol. 7, no. 3, pp. 189–200, May 1995.
[6] P. Arpaia, P. Daponte, L. Michaeli, 'The influence
of the architecture on ADC modelling', IEEE Trans.
on Instrumentation and Measurement, Vol 48.,
No.5., pp. 956-967. October 1999, ISSN 00189456J.