Statistical Critical Path Selection
for Timing Validation
Kai Yang, Kwang-Ting Cheng, and Li-C Wang
Department of Electrical and Computer Engineering
University of California, Santa Barbara
Outline
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Abstract
Background
Motivation
Universal Representative Path Set
Statistical Timing Simulator
UR-Path Construction
Experimental Result
Conclusion and Future Works
Outline
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Abstract
Background
Motivation
Universal Representative Path Set
Statistical Timing Simulator
UR-Path Construction
Experimental Result
Conclusion and Future Works
Abstract
Statistical critical path selection for timing validation
Path selection aims at tolerating inaccurate timing
models
o Develop an efficient statistical timing simulator
which can model both intra-die and inter-die
process variation
o Analyze the timing validation quality using the
generated patterns for the selected paths
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 Previous researches utilize static path analysis
Outline
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Abstract
Background
Motivation
Universal Representative Path Set
Statistical Timing Simulator
UR-Path Construction
Experimental Result
Conclusion and Future Works
Background
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Continuous shrinking of device feature size
increases the following timing effects:
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Process Variation
Power Noise
Crosstalk
Random Defects
Thermal Effects
Modeling Issue
 Traditional discrete-value timing models are no longer
effective
 Statistical timing modeling make more sense in deep
sub-micron domain
Background – Timing Validation
Verify the design with the timing constraints
o Functional pattern v.s. structure-based pattern
o Focus on the impact of process variations
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 No target on spot defects
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Structure-based pattern
 Critical path selection for timing validation
 Test pattern generation for selected path set
A
B
C
Outline
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Abstract
Background
Motivation
Universal Representative Path Set
Statistical Timing Simulator
UR-Path Construction
Experimental Result
Conclusion and Future Works
Motivation
Traditional discrete-value modeling not able to
efficiently capture deep sub-micron timing effects
o Even with a statistical methodology, an accurate
timing model may not be available during the
design phase
o Even with an accurate timing model, the number
of selected critical paths for timing validation may
be huge
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Outline
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Abstract
Background
Motivation
Universal Representative Path Set
Statistical Timing Simulator
UR-Path Construction
Experimental Result
Conclusion and Future Works
Universal-Representative Path
o Definition: Universal-Representative Path Set
(UR)
If we make sure the delays of these paths are less than a
given clock period, then we can guarantee that the worst-
case circuit timing is also less than the clock period.
probabilit y (circuit _ delay  clk | pUR, p  clk )  0
Factor Analysis v.s. UR-Path
Identify the underlying
structure of data matrix
Y=function of (3 factors)
Y’=function of (6 variables)
regression
Statistical
Timing
Simulation
Statistical
Timing
Simulation
ATPG
ATPG
Representative
paths
reduced to 3 factors
regression
Factor Analysis
6 aspects in your questionnaire
Path Selection
Outline
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Abstract
Background
Motivation
Universal Representative Path Set
Statistical Timing Simulator
UR-Path Construction
Experimental Result
Conclusion and Future Works
Statistical Timing Simulator - DSIM
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Objective: build a flexible, accurate, and efficient
timing simulator
 Support flexible interface for incorporating different DSM timing effects
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Inter-Die Process Variation
Hierarchical Intra-Die Process Variation Modeling
Allow us to study the impact of process variations
software released !
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Download source code at http://cadlab.ece.ucsb.edu
Statistical Timing Simulator
Statistical Delay
Library
Layout
Information
Intra-Die Process Variation
Profile
Delay Random Variables
Statistical Timing
Simulator -- DSIM
Circuit
Netlist
Sample 1
Simulation
Patterns
Sample 2
Sample K
…..
Delay 1
Delay 2
Delay K
Experimental Result and Efficiency
Statistical Simulation Efficiency
– 100 samples and 1000 random patterns
– P4 2GHz Linux workstation
Circuit CPU Time(sec) Memory
c880
46.45
2.56M
c1355
116.2
2.86M
c1908
97.74
2.55M
c2670
161.54
4.39M
c3540
229.37
4.63M
c5315
432.58
6.91M
c6288
679.72
6.58M
c7552
761.02
8.77M
s9234
1210.05
13M
s13207
1969.77
21M
s15850
2515.29
23M
s35932
5350.5
45M
s38417
3599.41
37M
s38584
6714.64
53M
Intra-Die Process Variations
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Process variation can be divided into two
categories
 Inter-Die Variation
 Intra-Die Variation
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Inter-die variation is more likely to be random
 Modeled in the statistical delay library
 Intra-die variation is spatially correlated which is
hard to directly modeled into the delay library
 Proximately-close devices may have similar behaviors
Hierarchical Intra-Die Process Variation
Modeling
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Originally developed by David Blaauw’s group on channellength modeling
C10
 Each region is associated with
a variation parameter Cn
 Cn characterize the change in
standard deviation
Example
X  Dx  ( N * C10  N * C20  N * C30 )
Y  D y  ( N * C10  N * C20  N * C30 )
C20
N  Normal  Dis (0,1)
 3% 
C30
Layout
C10  C20  C30
 0.03
std x
Proximity-closer devices have a
stronger correlations in theirs
delay
Impact of Modeled Intra-Die
Process Variation
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Layout Information – UCLA Capo
Without real process variation profile, randomly setup Cn
For each region, the change of accumulative std in percentage is less or
equal to 15%
3000 critical path delay test patterns with 6 different variation profiles
Summary of DSIM
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Each circuit sample has a different but fixed delay
configuration
Given a set of patterns, the simulator performs timing
simulation on each circuit sample
For a given clock and for each pattern, the simulator can
compute the probability of circuit delay exceeding the clock
Consider the effect of intra-die process variations into timing
simulation process
clk
Primary Output
Outline
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Abstract
Background
Motivation
Universal Representative Path Set
Statistical Timing Simulator
UR-Path Construction
Experimental Result
Conclusion and Future Works
UR-Path Construction
Two-Phase algorithm
o Path selection:
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 Select the superset of path (U-Path) from the whole
path space which may affect the critical timing
 Timing guard-band based selection method to tolerate
inaccurate timing model
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Path refinement:
 Select the subset of path (UR-Path) from U-Path which
can represent the timing behavior of the whole U-Path
set
Phase-1: Path Selection
o Goal: timing guard-band based method to select the set of
path which may affect the critical timing
o Construction of U-Path [iccad2002]
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Given a clock clk and the threshold value Δ, U-Path includes all paths with
non-zero critical probabilities to exceed the specified value clk- Δ.
For a large Δ will produce a large number of paths which will make the path
selection very inefficient.  Path Refinement
A
Δ
c5315
20000
B
c5315
c5315
15000
Number of U-Path

10000
5000
C
0
clk
333
332
331
330
329
328
327
326
clk-delta
333
clk- Δ
319
325
324
323
321
320
319
Phase-2: Path Refinement
o Goal: Select a small set of path which can represent the
timing behavior of U-Path
o Timing behavior: the possibility to be longer than the
clk
Sample-based method [iccad2002]
circuit
sample
DSIM
circuit
sample
circuit
sample
circuit
sample
Identify the path p has the largest
critical probability
Remove those samples which
p is longer than clk
For the remaining circuit samples,
select the path with the largest
critical probability, estimated based
on all remaining samples
Phase-2: Path Refinement
After phase-1, we get a set of UR-path but due to the
inaccurate timing model, we need to enlarge the path set
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Correlation based heuristic – statistical factor analysis
Select the paths which are more independent
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Paths with high correlation tend to have similar timing behavior
Remaining paths sorted
with mean delay
Pick one path p’ can calculate
the correlation coefficient with
each path in UR-set
UR-path set
If the correlation is less than
the given threshold value,
include p’ into UR-path set
Outline
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Abstract
Background
Motivation
Universal Representative Path Set
Statistical Timing Simulator
UR-Path Construction
Experimental Result
Conclusion and Future Works
Experimental Setup
Incorporate the statistical simulator to calculate
the failing sample rate as the evaluation metric
o Perform the proposed path selection with interdie process variation only
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 Modeled directly in the statistical delay library
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Evaluate the quality of the resulting pattern of
the circuit samples with both intra-die and interdie process variations
 To demonstrate the proposed method can tolerate the
inaccurate timing model
Metric: Failing Sample Rate
Statistical Timing Simulator
Circuit Instance with
both Inter-die and
Intra-die variations
Test set T
Cause delay
Exceeding clock?
yes
no
Not-Detected
Failing Sample
Rate
=
Detected
Detected
Detected + Not-Detected
Experimental Result
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Construct UR-Path set with different correlation coefficient
Compare with other path selection strategies
The number of selected critical path converge quickly
compare to the traditional selection methodology
Ind32opt
Experimental Results
c2670opt
Outline
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Abstract
Background
Motivation
Universal Representative Path Set
Statistical Timing Simulator
UR-Path Construction
Experimental Result
Conclusion and Future Works
Conclusions and Future Work
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Conclusion
Propose a sample-based strategy to select statistical critical
paths for timing validation. Experiment shows that the
number of selected path converge quickly.
For some circuits, the proposed sampled-based method is
much more efficiency than the traditional critical path
selection.
Develop an efficient statistical timing simulator which can
simulate both intra-die and inter-die delay.
Future Work
 Theoretically analyze the path selection problem for timing
validation
 Incorporate real process variation profiles to evaluate the
proposed methodology