Advanced Digital Design
Synthesis of Control Circuits
by A. Steininger and J. Lechner
Vienna University of Technology
1
Outline


Control Circuits
Petri Nets & Signal Transition Graphs



Synthesis of SI control circuits




Properties
Common PN/STG fragments
State Encoding
Next-state functions
Implementation
Synthesis tool: Petrify
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
2
Control Circuits
Control logic essential part of
asynchronous circuits
Latch

How to specify?
How to implement?
Req
Req
Ack
Lecture "Advanced Digital Design"
Comb.
Logic
Ack
Req
Latch

Latch

Comb.
Logic
Ack
Control ?
© A. Steininger & J. Lechner / TU Vienna
Req
Ack
Req
Ack
3
Petri Nets (PNs)






For modelling concurrent systems
Directed graph with nodes and arcs
Nodes: places, transitions
Places can be marked with tokens
Transition is enabled (allowed to fire) if
all input places have tokens
When a transitions fires:


Token removed from all input places
Token added to each output place
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
4
STGs





Restricted subclass of petri nets
PN transitions = signal transitions
Simple places omitted (places with a
single input and a single output)
Places/arcs represent causal
relationships between signal transitions
Marking represents circuit state
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
5
PN/STG - Example
Muller C-gate
Source:
[Sparso 06]
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
6
Properties of STGs I

Input free choice


1-bounded


Alternative transitions only controlled by
mutually exclusive inputs
Max. one token per place
Liveness

STG is live iff from every reachable
marking, every transition can eventually
fire
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
7
Typical PN/STG Fragments
Choice
Merge
Fork
Join
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
8
PN/STG Fragments - Example
Source:
[Sparso 06]
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
9
Properties for STGs II

STGs can be implemented as speedindependent circuits. Requirements:

Consistent state assignment


Persistency


In any execution, any transition alternates
between rising and falling
Enabled signals will eventually fire, cannot be
disabled by other transition
Complete state coding (CSC)

Different markings must represent different
states
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
10
Speed-Independence (SI)

Delay-model: speed-independence


Arbitrary gate delays (bounded but
unknown)
Ideal zero-delay wires
Source:
[Sparso 06]
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
11
STG Synthesis
Specification
State graph
State Graph with CSC
Next-State functions
Decomposed functions
Gate netlist
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
Reachability
analysis
State encoding
Boolean
minimization
Logic
decomposition
Technology
mapping
12
Specification
Source: [Sparso 06]
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
13
State Graph
0000
b+
c-
0100
a+
1000
0010
c+
0110
b-
b+
1100
d+
a-
1110
d-
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
1101
c+
1111
(a,b,c,d)
14
Excitation Regions
for Output Signal c
ER1(c+)
0000
b+
c-
0100
0010
c+
0110
b-
ER1(c-)
1000
b+
1100
d+
a-
1110
QR1(c+) d-
Lecture "Advanced Digital Design"
a+
© A. Steininger & J. Lechner / TU Vienna
1101
c+ ER2(c+)
1111
15
Quiescent Regions
for Output Signal c
0000
b+
C-
0100
QR1(c-)
1000
0010
c+
0110
a+
b-
b+
1100
d+
a-
1110
QR1(c+) d-
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
1101
c+
1111
16
Next-State Functions
KV Diagram for c
ER1(c+)
0000
b+
C-
0100
0010
c+
0110
b- ER1(c-)
a+
QR1(c-)
1000
cd
ab
00
01
11
10
00
0
x
x
F
01
R
x
x
1
11
0
R
1
1
10
0
x
x
x
b+
1100
d+
a-
1110
QR1(c+) d-
Lecture "Advanced Digital Design"
1101
c+ ER2(c+)
1111
© A. Steininger & J. Lechner / TU Vienna
17
Atomic Complex Gate
Implementation
cd
ab
00
01
11
10
00
0
x
x
F
01
R
x
x
1
11
0
R
1
1
10
0
x
x
x
c = d + a‘b + bc
Attention: Decomposition into
simple gates can introduce hazards!
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
18
State-holding Gates
Implementation

Signals toggle between excitation and
quiescent/stable regions


ER(c+)  QR(c+)  ER(c-)  QR(c-) etc.
Implementation with SR-latches, Cgates or generalized C-gates possible
Generalized Celement
Source: [Sparso 06]
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
19
State-holding Gates
Set/Reset Functions



c = Set + c ∙ Reset‘
Set ∙ Reset = 0
Set Function:




must contain all states in ER(c+)
may contain states in QR(c+)
may contain not reachable states
Reset Function:



must contain all states in ER(c-)
may contain states in QR(c-)
may contain not reachable states
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
20
State-holding Gates
Implementation
cd
ab
00
01
11
10
00
0
x
x
F
01
R
x
x
1
11
0
R
1
1
10
0
x
x
x
Lecture "Advanced Digital Design"
Set function:
c-set = d + a‘b
© A. Steininger & J. Lechner / TU Vienna
21
State-holding Gates
Implementation
cd
ab
00
01
11
10
00
0
x
x
F
01
R
x
x
1
11
0
R
1
1
10
0
x
x
x
Lecture "Advanced Digital Design"
Set function:
c-set = d + a‘b
Reset function:
c-reset = b‘
© A. Steininger & J. Lechner / TU Vienna
22
State-holding Gates
Implementation
cd
ab
00
01
11
10
00
0
x
x
F
01
R
x
x
1
11
0
R
1
1
10
0
x
x
x
Lecture "Advanced Digital Design"
Set function:
c-set = d + a‘b
Reset function:
c-reset = b‘
© A. Steininger & J. Lechner / TU Vienna
23
State-holding Gates
Hazards
0000
b+
c-
0100
a+
1000
0010
c+
0110
b-
b+
1100
d+
a-
1110
1101
cd
ab
00
01
11
10
00
0
x
x
F
01
R
x
x
1
11
0
R
1
1
10
0
x
x
x
010
0101 0
c+
d-
1111
010
010
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
24
State-holding Gates
Monotonic Cover Constraint

A cube (product term) may only be
entered through ER states (monotonic
cover or unique entry constraint)
cd
ab
00
01
11
10
00
0
x
x
F
01
R
x
x
1
11
0
R
1
1
10
0
x
x
x
Lecture "Advanced Digital Design"
Hazardous set function:
c-set = d + a‘b
© A. Steininger & J. Lechner / TU Vienna
25
State-holding Gates
Monotonic Cover Constraint

A cube (product term) may only be
entered through ER states (monotonic
cover or unique entry constraint)
cd
ab
00
01
11
10
00
0
x
x
F
01
R
x
x
1
11
0
R
1
1
10
0
x
x
x
Lecture "Advanced Digital Design"
Fixed set function:
c-set = d + a‘bc‘
© A. Steininger & J. Lechner / TU Vienna
26
Example
VME Bus Controller
D
DSr
DTACK
LDS
VME Bus
Controller
LDTACK
STG of Read Cycle
DSr+
LDS+
LDTACK+
LDTACK-
Lecture "Advanced Digital Design"
DTACKD+
DTACK+
DSr-
D-
LDS-
© A. Steininger & J. Lechner / TU Vienna
27
VME Bus Controller
CSC Conflict
LDS+
10000
DSr+
LDTACK-
10010
10100
LDTACK+
10110
DSr+
LDS-
10110
00000
DTACK-
LDTACK-
00100
LDTACK-
DTACK-
LDSDSr+
00110
01000
01100
LDS-
DTACK-
01110
D+
10111
DTACK+
11111
DSr-
D-
01111
(DSr, DTACK, LDTACK, LDS, D)
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
28
VME Bus Controller
CSC Conflict
DSr+
LDS+
LDS+
LDTACK+
D+
DTACK+
LDS-
DSr+
DTACK-
LDTACK-
Lecture "Advanced Digital Design"
DTACK-
LDTACK-
LDTACK+
10110
D+
DTACK+
DSr-
D-
10110
DSr-
D-
LDS-
© A. Steininger & J. Lechner / TU Vienna
29
Resolving CSC Conflict
Concurrency Reduction

Solution I: Remove conflict state by
concurrency reduction
LDS+
10000
DSr+
LDTACK-
10010
10100
LDTACK+
10110
DSr+
LDS-
10110
00000
DTACK-
LDTACK-
00100
LDTACK-
DTACK-
LDSDSr+
00110
01000
01100
LDS-
DTACK-
01110
D+
10111
Lecture "Advanced Digital Design"
DTACK+
11111
DSr-
D-
01111
© A. Steininger & J. Lechner / TU Vienna
30
Resolving CSC Conflict
Concurrency Reduction

Solution I: Remove conflict state by
concurrency reduction
LDS+
10000
DSr+
LDTACK-
10010
10100
DSr+
LDTACK+
00000
DTACK-
LDTACK-
00100
LDTACK-
DTACK-
LDS-
10110
00110
01000
01100
LDS-
DTACK-
01110
D+
10111
Lecture "Advanced Digital Design"
DTACK+
11111
DSr-
D-
01111
© A. Steininger & J. Lechner / TU Vienna
31
Resolving CSC Conflict
Concurrency Reduction

Concurrency reduction reflected by
adding an arc to the STG specification.

Introduces timing assumption (LDSbefore DSr+)
DSr+
LDS+
LDTACK+
LDTACK-
Lecture "Advanced Digital Design"
DTACKD+
DTACK+
DSr-
D-
LDS-
© A. Steininger & J. Lechner / TU Vienna
32
Resolving CSC Conflict
Adding State Signal

Solution II: Inserting an internal state
signal to make conflict states unique
100001
CSC+
LDS+
100101
LDTACK+
101101
100000
DSr+
LDTACK-
101000
DSr+
LDS-
101100
000000
DTACK-
010000
LDTACK-
001000
DTACK-
LDTACK-
011000
LDS-
DSr+
001100
LDS-
DTACK-
D+
011100
D-
DTACK+
101111
111111
DSr-
011111
CSC-
011110
(DSr, DTACK, LDTACK, LDS, D, CSC)
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
33
Petrify

Synthesis of speed independent control
circuits from STG specifcations



Simple text format for describing STGs
Petrify can solve CSC problem
Public domain tool


Developed at different universities
http://www.lsi.upc.edu/~jordicf/petrify/
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
34
Petrify - Example
.model cgate
.inputs a b
.outputs c
.graph
a+ c+
b+ c+
c+ ac+ ba- cb- cc- a+
c- b+
.marking { <c-, a+> <c-, b+> }
.end
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
35
Petrify

Set of command-line tools




petrify: synthesis command
write_sg: derives state graph
draw_astg: draws STGs/state graphs
Different circuit implementations



Complex gates (-cg)
Generalized C-elements (-gc)
Specific target library (-tm)
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
36
Summary



Control logic essential part of
asynchronous circuits
PNs/STGs convenient for modeling
control circuits
STGs need to fulfill certain properties


Input-free choice, 1-bounded, CSC, etc.
Synthesis from STGs to SI gate
implementations possible

Tool available: Petrify
Lecture "Advanced Digital Design"
© A. Steininger & J. Lechner / TU Vienna
37