FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
Page 1 of 6
LP: VL7201
Department of Electronics and Communication Engineering
B.E/B.Tech/M.E/M.Tech : M.E : EC
Rev. No: 01
Regulation:2013
PG Specialisation
: Applied Electronics
Sub. Code / Sub. Name
: VL7201- CAD FOR VLSI CIRCUITS
Unit
:I
Date: 28/08/2015
UNIT I VLSI DESIGN METHODOLOGIES
9
Introduction to VLSI Design methodologies, Review of Data structures and algorithms,
Review of VLSI Design automation tools, Algorithmic Graph Theory and Computational
Complexity, Tractable and Intractable problems, general purpose methods for combinatorial
optimization.
Objective: To study various physical design methods in VLSI
Session
No*
Topics to be covered
Ref
Teaching
Aids
1
Introduction to VLSI Design Methodologies
1-Ch-1; pg 1(1-3)
4-Ch-1; pg 1(2-11)
PPT
2
Review of Data Structures and Algorithms
1-Ch-1; pg 1(3- 5)
PPT
3
Review of VLSI Design Automation Tools
1-Ch-2; pg (11-19)
PPT
4
Design Style
2-Ch-1; pg (15-25)
PPT
5
Algorithmic Graph Theory
PPT
6
Computational Complexity
7
Tractable Problems
1-Ch-3; pg (21-24)
2-Ch-4; pg (97-99)
1-Ch-4; pg (115117)
1-Ch-4; pg (42-44)
BB/PPT
8
Intractable Problems
1-Ch-4; pg (44-50)
PPT
9
General Purpose Methods for Combinatorial Optimization.
1-Ch-5; pg (53-79)
PPT
Content beyond syllabus covered (if any):
Design Style
Course Outcome 1:
The students will be able to design combinatorial optimization problems.
* Session duration: 50 minutes
PPT
FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
Page 2 of 6
Sub. Code / Sub. Name: VL7201- CAD for VLSI Circuits
Unit : II
UNIT II DESIGN RULES
9
Layout Compaction, Design rules, problem formulation, algorithms for constraint graph
compaction, placement and partitioning, Circuit representation, Placement algorithms,
partitioning
Objective: To understand the concepts behind the VLSI design rules and routing techniques.
Session
No *
10
11
12
13
14
15
Topics to be covered
Layout Compaction
Ref
Design Rules
1-Ch-6; pg (83-84)
3- Ch-1;pg (381-382)
1-Ch-6; pg (84-85)
Problem Formulation
1-Ch-1; pg (86-90)
Algorithms for Constraint Graph Compaction
1-Ch-6; pg (91-97)
Algorithms for Constraint Graph Compaction
1-Ch-6; pg (91-97)
Placement and Partitioning
Teaching
Aids
PPT
PPT
BB/PPT
PPT
PPT
1-Ch-7; pg (101-102)
2-Ch-5; pg (163-167)
PPT
Circuit Representation
1-Ch-7; pg (102-105)
PPT
Placement Algorithms
1-Ch-7; pg (106-110)
2-Ch-5; pg (168-172)
1-Ch-7; pg (112-118)
2-Ch-5; pg (173-182)
CAT-I
16
17
18
Partitioning
PPT
PPT
Content beyond syllabus covered (if any): -Course Outcome 2:
The students will be able to apply various VLSI design rules and routing techniques
* Session duration: 50 mins
FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
Page 3 of 6
Sub. Code / Sub. Name: VL7201- CAD for VLSI Circuits
Unit : III
UNIT III
FLOOR PLANNING
9
Floor planning concepts, shape functions and floorplan sizing, Types of local routing problems,
Area routing, channel routing, global routing, algorithms for global routing.
Objective: To understand the concepts of various algorithms used for floor planning and routing
techniques
Session
No *
19
Topics to be covered
Floor Planning Concepts
Ref
Teaching
Aids
PPT
20
Shape Functions
1-Ch-8; pg (119-124)
2-Ch-6; pg (193-194)
1-Ch-8; pg (125-126)
21
Floor Plan Sizing
1-Ch-8; pg (126-129)
PPT
22
Floor Plan Sizing
1-Ch-8; pg (133-134 )
PPT
23
Types of Local Routing Problems
1-Ch-9; pg (133-134 )
PPT
24
Area Routing
1-Ch-9; pg (134-135 )
PPT
25
Channel Routing
PPT
26
Global Routing
1-Ch-9; pg (138-146)
3-Ch-7; pg (289-290)
1-Ch-9; pg (125-126)
2-Ch-8; pg (247-257)
27
Algorithms for Global Routing.
1-Ch-9; pg (125-126)
2-Ch-8; pg (260-273)
PPT
28
Maze Routing Algorithm.
2-Ch-8; pg (261-269)
PPT
Content beyond syllabus covered (if any):
Maze routing algorithm.
Course Outcome 3:
The students will be able to design various routing techniques.
* Session duration: 50 mins
PPT
PPT
FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
Page 4 of 6
Sub. Code / Sub. Name: VL7201- CAD for VLSI Circuits
Unit : IV
UNIT IV
SIMULATION
9
Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis.
Objective: To use the simulation techniques at various levels in VLSI design flow.
Session
No *
29
Topics to be covered
Simulation
1-Ch-10; pg (167-168)
Teaching
Aids
BB,PPT
Ref
30
Gate-Level Modeling
1-Ch-10; pg (171)
PPT
31
Switch-Level Modeling
1-Ch-10; pg (170)
PPT
32
Gate-Level Modeling Simulation
1-Ch-10; pg (169-176)
PPT
CAT-II
33
Switch-Level Modeling Simulation
1-Ch-10; pg (180-183)
PPT
34
Combinational Logic Synthesis
1-Ch-11; pg (195-199)
PPT
35
Binary Decision Diagrams
1-Ch-11; pg (201-219)
PPT
36
Two Level Logic Synthesis
1-Ch-11; pg (222-225)
37
Two Level Logic Synthesis
1-Ch-11; pg (222-225)
Content beyond syllabus covered (if any):-Course Outcome 4:
The students will be able to model and simulate various logic synthesis problems
* Session duration: 50 mins
PPT
PPT
FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
Page 5 of 6
Sub. Code / Sub. Name: VL7201- CAD for VLSI Circuits
Unit : V
UNIT V MODELLING AND SYNTHESIS
9
High level Synthesis, Hardware models, Internal representation, Allocation, assignment and
scheduling, Simple scheduling algorithm, Assignment problem, High level transformations.
Objective: To understand the concept of various synthesis and scheduling algorithm.
Session
No *
38
Topics to be covered
Ref
Teaching
Aids
High Level Synthesis
1-Ch-12; pg (235-237)
39
Hardware Models
1-Ch-12; pg (237-238)
40
Internal Representation
1-Ch-12; pg (239-245)
41
Allocation
1-Ch-12; pg (247-251)
42
Assignment and Scheduling
1-Ch-12; pg (247-251)
5
ICT
PPT
PPT
PPT
PPT
43
Simple Scheduling Algorithm
1-Ch-12; pg (253-260)
PPT
44
Simple Scheduling Algorithm
1-Ch-12; pg (253-260)
PPT
45
Assignment Problem
1-Ch-12; pg (261-265)
46
Assignment Problem
1-Ch-12; pg (261-265)
PPT
47
High Level Transformations
1-Ch-12; pg (266-270)
PPT
CAT-III
Content beyond syllabus covered (if any):--
Course Outcome 5:
The students will be able to design various assignment problems.
* Session duration: 50 mins
PPT
FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY
Page 6 of 6
Sub. Code / Sub. Name: VL7201- CAD for VLSI Circuits
REFERENCES:
1. S.H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons, 2002.
2. N.A. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwer Academic
Publishers, 2002.
3. Sadiq M. Sait, Habib Youssef, “VLSI Physical Design automation: Theory and Practice”,
World scientific 1999.
4. Steven M.Rubin, “Computer Aids for VLSI Design”, Addison Wesley Publishing 1987.
5. http://nptelvideos.iitm.ac.in/softlinks/117101007 & other relevant materials from internet.
Prepared by
Approved by
Dr.R.Gayathri
Dr.S.Ganesh Vaidyanathan
Designation
Asso. Prof.
HoD - EC
Date
Remarks *:
28.08.2015
28.08.2015
Signature
Name
Remarks *:
* If the same lesson plan is followed in the subsequent semester/year it should be mentioned and
signed by the Faculty and the HOD.