Report for Experiment 14
Name : 20121071 김민우, 20121196 박미진 Date : 2013.03.17 Class : CSE20101
Objectives :
□ Demonstrate how a latch can debounce an SPDT switch.
□ Contruct and test a gated D latch from four NAND gates and an inverter.
□ Test a D flip-flop and investigate several application circuits for both the latch and the
flip-flop.
Data and Observations :
Step 3. Observations for SPDT switch debounce circuit :
FIGURE 3-1
After simulating a bouncing switch by removing the A end of the wire and reconnecting the
wire to A several times, the red LED is on.
FIGURE 3-2
After touching B and simulating the switch bouncing several times, the green LED is on.
Step 5. Observations for D latch circuit :
FIGURE 5-1
FIGURE 5-2
At first, the red LED was on as shown in FIGURE 5-1. When we leaved the enable LOW and
place a momentary short to ground first on one output, the red LED was off. Then we put the
first wire back to its original place, the green LED was on as shown in FIGURE 5-2. We
conducted the next step to the other output as we did on the first output. Then the green one
was off. We put the second wire to its original place, the red LED was on again.
Step 6. Observations for the simple burglar alarm :
FIGURE 6-1
FIGURE 6-2
We made the simple burglar alarm. If the switch is off, it means a theft is occurred. Then the
red LED is on as shown in FIGURE 6-1. If the switch in on, it means peaceful situation(no
theft.). But to off the red LED, we need to reset the system. We put a momentary ground on
the Q output then the red LED is off as shown in FIGURE 6-2.
Step 7 and 8. Observations for setup time :
FIGURE 7-1
FIGURE 7-2
FIGURE 7-1 and 7-2 show that the D flip-flop with the delay circuit.
The output is 1 with a sufficient setup time as shown in FIGURE 7-2.
FIGURE 8-1
FIGURE 8-2
FIGURE 8-1 and 8-2 show the D flip-lop without the delay circuit.
As shown in FIGURE 8-2, without a sufficient setup time, the output has changed to 0.
The prove of channel 1 was accidently disconnected so our result shows 0 in the channel one.
Step 10. Obsevations for the D flip-flop :
FIGURE 10-1
FIGURE 10-2
FIGURE 10-1 and 10-2 show the circuit with the clock delay but disconnected D input.
Results and Conclusion :
This experiment's object is to demonstrate howe a latch can rebounce an SPDT
switch, construct and test a gated D latch from four NAND gates and an inverter.
Combinational logic circuits are circuits in which the outputs are determined fully by
the inputs. Sequential logic circuits contain information about previous conditions.
Difference is that sequential circuits contain memory and combinational circuits do
not.
The basic memory unit is latch, which uses feedback to lock onto and hold data.
Design problems are often simplified by having all transitions in a system occur
synchronously by using a common source of pulses to cause the change. This common
pulse is called a 'clock'. The output changes occur only on either the leading or the
trailing edge of the clock pulse. Some ICs have inputs that directly set or reset the
output any time they are asserted. These inputs are labeled asynchronous inputs
because no clock pulse is required.
We constructed S-R latch, D latch, and D flip-flop following the instructions. First,
S-R latch, we could use a wire to simulate the SPDT switch. LEDs are used as logic
monitors. Because TTL logic is much better at sinking current than at sourcing current,
the LEDs are arranged to be ON when the output is LOW. Simulating a bouncing
switch is to make the latch to be 'set state' and 'reset' state. When Q=1 and Q'=0, it is
said to be 'set', and Q=0 and Q'=1, is said to be 'reset'.
We modified S-R latch to D latch by adding the steering gates and the inverter. When
'En'(enable) is 0, next state of Q has no change. And we made the simple burglar
alarm(Figure 14-3). The data input represents switches connected to windows and
doors. The enable input is pulled HIGH when the system is activated or LOW for
standby. To reset the system, we had to put a momentary ground on the Q output.
7474 is a dual, positive edge-triggered D flip-flop containing two asynchronous
inputs PRE(preset) and CLR(clear). We constructed test circuit following the Figure
14-6. We connected the clock through the delay circuit, and the purpose of the delay is
to allow setup time for the D input. When we removed the clock delay by connecting
the clock input directly to the purse generator, the output dc level on oscilloscope was
changed because there was insufficient setup time. We leaved the clock delay circuit
in place, but disconnected the D input, and attached a wire from Q' to the D input. For
relative timing measurements, we should trigger the scope using the channel that has
the slowest waveform as the trigger channel. When the input clock in the positiveedge-triggered flip-flop makes a positive transition, the value of D is transferred to Q.
A negative transition of the clock does not affect the output, nor is the output affected
by changes in D when Clk is in the steady logic-1 level or the logic-0 level. The
timing of the response of a flip-flop to input data and to the clock must be taken into
consideration when one is using edge-triggered flip-flops. There is a minimum time
called the setup time during which the D input must be maintained at a constant value
prior to the occurrence of the clock transition.
Report for Experiment 15
Name : 20121071 김민우, 20121196 박미진 Date : 2013.03.17 Class : CSE20101
Objectives :
□ Design a circuit that detects the presence of a tripped-over carton for a foodprocessing application and rejects it before it reaches the carton-sealing machine.
□ Decide on a troubleshooting procedure for testing the circuit if it fails.
□ Write a formal laboratory report documenting your circuit and a simple test procedure.
Data and Observations :
FIGURE 1
FIGURE 2
FIGURE 3
FIGURE 4 The logic diagram of the circuit for this experiment.
Results and Conclusions :
This experiment is to design a circuit that detects the presence of a tipped-over carton for a
food-processing application and rejects it before it reaches the carton-sealing machine. We
had to decide on a troubleshooting procedure for testing the circuit if it fails.
D flip-flop can hold information temporarily, acting as a memory element capable of storing
one bit of information. For this experiment, it is necessary to store information temporarily to
use after the inputs have changed. The circuit can then take an action even though the
originating event has passed. The event can do the clocking action to assure that the flags are
set each time an event occurs. The occurrence of an event is asynchronous, so it is not related
to a clock signal. Since the event will do the clocking, it is necessary to use delay in the clock
signal to assure that sufficient setup time is given to the D flip-flop.
The circuit which we designed is in picture. It have two photocells, as illustrated in Figure
15-1. Photocell which is connected to Clk is A and to D is B. An upright carton will cause
photocell A to be covered first and then photocell B to be covered. We had to experiment with
the value of R1(1옴) to determine a value that gives TTL logic levels for our particular
photocell and room lighting. The resistance of a photocell is lower as the light intensity
increases. If the photocell is covered, the output should be set for a logic High, and it is
uncovered, it should be a logic LOW. LED are turned on with a LOW signal.