Efuse block
Description and simulation
Symbol
vddp
vddd
T3NW
6
address
NR1
16
NR2
out_bus
WE
48
Sense
out_still
Burn_CK
Burn_RN
FEI4_A_EFUSE
in_bus
Burn_srout
EFUSE_errorflag
16
subCon
sub
gndd
2
Pin name
Address<5:0>
in_bus<15:0>
out_bus<15:0>
out_still<47:0>
NR1
NR2
Burn_RN
Burn_CK
Burn_srout
Sense
EFUSE_errorflag
WE
Vddp
Vddd
T3Con
Sub
Gndd
SubCon
I/O list
Description
INPUT - 6-bit address bus
INPUT - 16-bit data bus
OUTPUT - 16-bit data bus
OUTPUT – 48 bit data bus
Comment
Provided by CMD block
From CMD block
To EOCHL block
To end of column Shift Register Select (40b),
voltage ref trim (4b) and current ref trim (4b)
INPUT – General Reset
Active low – reset when NO (NR1 AND NR2)
INPUT – General Reset
Active low – reset when NO (NR1 AND NR2)
INPUT - EFUSE reset
Reset the sense state machine and the EFUSE
Active low
internal memory.
INPUT - Independent EFUSE Clock to independently output the EFUSE
readout shift register clock
values. From pad
Rising edge data sampling
Falling edge data shift
OUTPUT – Shift register Shift register output. Flag the end of the
output
programming sequence or read out
programmed values – To dig buffered pad
INPUT – Start the sense Start the sense circuitry.
circuitry – Rising edge
From control block
OUTPUT – active high
Flag an error in latches
To error block
INPUT - Write enable
Validate a write in the latch from the data bus
From CMD block
Program Vdd
Typ 3.3V, Min 3V, 15mA flowing during prog.
Digital Vdd
Typ. 1.4V
Triple Well contact
To be tied to dedicated vdd
Substrate
Digital Ground
15mA flowing during programming
Substrate contact
-
3
Block Scheme
Data bus out
Data bus in
EFUSE out bus
64 bits
Still Data bus
Address bus
EFUSE in bus
COM
Error_flag
64 bits
MODULE
Sense
Burn_CK
Burn_RN
EFUSE CORE
Burn_srout
4
Data bus in
Data bus out
Error_flag
WE
Com Block Scheme
WORD address 35
WORD address 34
Still Data bus
WORD address 33
Re-sense
Address decoder
EFUSE in bus, 64 bits
Address bus
EFUSE out bus, 64 bits
WORD address 32
5
Layout
6
How to write
• Writing sequence :
– 3.3V is down
– chip is reseted and EFUSE is reseted
– Data are sent to the EFUSE register
– 3.3V is turned on
– Burn_CK starts until the one that is
propagating reach the register output
 Bit are written one after another to avoid
excessive current in the chip (10-13mA per
bit)
7
Burn Simulation
In that simulation, the latches are loaded with word 1010101010101010 at address 32, all the other latches are kept at 0.
The burn process is then started and the current flowing out of Vddp is sensed.
8
How to read
• Independant reading sequence :
–
–
–
–
3.3V is not needed, chip has been reseted
Sensing circuitry detect the Efuse value
Burn shift register is loaded through the MUX
Data are serially outputted through the burn shift register
• Chip programming
– As soon as sense circuitry has read out the fuse value, the data
are loaded in the EFUSE register
– In case of SEU, the data are automatically reloaded and an error
flag is sent to the error block
– It is possible to write custom value in the register, these value
will be overwritten by the EFUSE value if sense is activated or if
an SEU occurs
9
Read simulation
In that simulation, the values programmed in the efuse are sensed; an SEU is emulated to ensure that the values are
automatically reloaded. A new set of value is programmed in the latches and a second SEU is simulated to check that the
EFUSE values are correctly reloaded.
10
Spare slides
One cell block
from/to internal memory
IN
OUT
Connect to chip register
from previous cell
Dburn
Control the efuse shift register
EFUSE
Qburn
to next cell
Control the sense circuitry
Burn_CK
Ctrl_MUX
FCLRN
FSETP
12
One cell block (2)
IN
&
FCLRN
FSETP
Write
circuitry
Dburn
OUT
Sense
EFUSE circuitry
Qburn
Ctrl_Mux
FCLRN
Dburn
FSETP
D
Q
Qburn
Burn_CKRN
1.5V
3.3V
1.5V  3.3V
Ctrl_Mux
Burn_RN
Burn_CK
13
One cell block (3)
• The same shift register is used both for :
– Writing token, ensuring that only one ’1’ is in
the SR thus only one cell is programmed at a
time
– Reading out programmed data to ensure a
correct programming independantly of the
chip general memory
14
Cell connection
This first cell ensures
only one ‘1’ is in the SR during writing
DFF
All other cells are standard
EFUSE cells
EFUSE
Dburn
Qburn
Qburn
Ctrl_Mux
FCLRN
FSETP
SETN
RN
Burn_CK
Burn_CK
DFF
EFUSE
EFUSE
EFUSE
EFUSE
EFUSE
EFUSE
EFUSE
15
Sense circuitry control
• Need to work without clock
• Start the sensing sequence and store the
sensing result in the stand alone shift
register.
 Use of an asynchronous state machine
FSETP
Sense
Power on reset
SENSE
ASM
FCLRN
MUX_CTRL
LOAD
16
State bit generation
IN
OUT
SET
RESET
Release token
Data ack.
Delay rising ~ 30ns
Delay falling < 5ns
Q0
Sense
Power on reset
Q1
Q2
Start
cell
17
State bit generation
Sense
Q0
Q1
Q2
18
Output bit generation
State
bits
Q0
Q1
Q2
FCLRN
FSETP
CTRL
MUX
LOAD
Sequence take around 100ns to complete
19
IBM Efuse specs
20
© IBM
Sensing circuitry
21
© IBM
Sensing chronogram
22
© IBM
Sensing output vs Efuse resistance
23