Multi-Project
Reticle Design & Wafer Dicing
under Uncertain Demand
Andrew B Kahng, UC San Diego
Ion Mandoiu, University of Connecticut
Xu Xu, UC San Diego
Alex Zelikovsky, Georgia State University
Multi-Project Wafers
Mask set cost: >$1M for 90 nm technology
 Share cost of mask tooling between multiple designs!
 Prototyping
 Low volume production

Images courtesy of EuroPractice and CMP
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Design Flow for MPW
Die Sizes + Production Volumes
Project Partitioning
Project Cloning
Reticle Floorplaning
Shotmap Definition
Dicing Plan Definition
Reticle, Wafer Shotmap, Wafer Dicing Plans
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Design Flow for MPW
Die Sizes + Production Volumes
Project Partitioning
Project Cloning
Reticle Floorplaning
Shotmap Definition
Dicing Plan Definition
Reticle, Wafer Shotmap, Wafer Dicing Plans
4
Why is Dicing a Problem?
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Side-to-side dicing!
Correctly sliced out dies
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Cut lines along all four edges
No cut line partitioning the die
Standard wafer dicing
MPW dicing
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Side-to-side Dicing Problem
Given:
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Production volume for each die
Reticle floorplan
Wafer shot-map
Find:
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Horizontal and vertical dicing
plans for each wafer
To Minimize:

#wafers required to meet
production volumes
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Dicing Strategies
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Wafer Dicing Plan (DP): all horizontal and vertical cut lines
used to cut a wafer
Row/Column DP: cut lines through row/column of reticle images
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1
2
1
2
3
4
3
4
3
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Single wafer dicing plan (SDP) [ISPD04] [KahngR04]
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The same wafer DP used for all wafers
Different DPs used for different rows/cols in a wafer
Multiple wafer dicing plans (MDP)
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Restricted MDP: the same DP used for all rows/cols of a wafer
Graph coloring based heuristic in [Xu et al. 04]
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Independent Dies
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Under restricted MDP dicing, all reticle images on wafer yield
the same set of dies
Independent set: set of dies that that can be simultaneously
diced from a reticle image

Only maximal independent sets are of interest!
1
2
3
4
Maximal Independent Sets: {1, 4} {2} {3}
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ILP for Restricted MDP
Minimize : nw  n p
Subject to :
 Q( I , D) y
DC
I
 N ( D)
D
nw   y I
I
n p   xI
I
N max xI  y I
I
y I  # wafers used to dice indep. set I
xI  1 if y I  0,  0 otherwise
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CMP Floorplan
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SDP vs. MDP
9 wafers with SDP
5 wafers with MDP
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4-Part Dicing

Partition each wafer into 4 parts then dice each part
separately using side-to-side cuts
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Design Flow for MPW
Die sizes + Production Volumes
Project Partitioning
Project Cloning
Reticle Floorplaning
Shotmap Definition
Dicing Plan Definition
Reticle, Wafer Shotmap, Wafer Dicing Plans
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Shotmap Definition Problem
Shotmap #1
?
Reticle Floorplan
Shotmap #2

Simple grid-based shotmap definition algorithm yields an
average reduction of 13.6% in #wafers
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Design Flow for MPW
Die sizes + Production Volumes
Project Partitioning
Project Cloning
Reticle Floorplaning
Shotmap Definition
Dicing Plan Definition
Reticle, Wafer Shotmap, Wafer Dicing Plans
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Reticle Floorplaning Problem
Given:
 Die sizes & production volumes
 Maximum reticle size
Find:
 Placement of dies within the reticle
To Minimize:
 Production cost (reticle cost, #wafers, …)
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Reticle Floorplaning Methods
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Key challenge: cost estimation
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Previous approaches
Simulated annealing [ISPD04]
 Grid-packing [Andersson et al. 04, KahngR04]
 Integer programming [WuL05]
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Our approach: Hierarchical Quadrisection (HQ)
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Hierarchical Quadrisection Floorplan
At most one die assigned to each region at lowest level
 Region widths/heights easily computed from die assignment
 HQ mesh more flexible than grid
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HQ Algorithm
Random initial assignment improved using simulated annealing
 SA moves: region exchange, die rotation
 Max reticle size enforced throughout the algorithm
 Hierarchical structure enables quick cost estimation
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HQ Floorplan of CMP Testcase
Reticle Area = 2.30 (vs. 2.45)
4 wafers with MDP (vs. 5)
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Design Flow for MPW
Die sizes + Production Volumes
Project Partitioning
Project Cloning
Reticle Floorplaning
Shotmap Definition
Dicing Plan Definition
Reticle, Wafer Shotmap, Wafer Dicing Plans
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Project Cloning
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Motivation
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Post-processing approach [WuL05]
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Die-to-die inspection [Xu et al.]
Reduced wafer cost when there is large variation in production
demands
Insert clones in white space left on reticle
Our approach
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Before floorplaning: number of clones proportional to square root of
production volume; clones arranged in clone arrays
During floorplaning: clone arrays assigned to single cell in HQ; new
SA moves: add/delete clone array row/column
After floorplaning: insert additional clone array rows/columns
without increasing cell size
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Design Flow for MPW
Die sizes + Production Volumes
Project Partitioning
Project Cloning
Reticle Floorplaning
Shotmap Definition
Dicing Plan Definition
Reticle, Wafer Shotmap, Wafer Dicing Plans
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Schedule Aware Partition
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More decision knobs: fabrication schedule
I will not pay you
after June
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Project Partitioning Problem
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?
But, money will be
saved if waiting for
other orders…
Given: Reticle size, set of projects
Find: Partition of projects into reticles
To minimize: Sum of manufacturing cost and delay cost
[BACUS05] Schedule-aware partitioning leads to an average
cost reduction of 63.8% vs. schedule-blind partitioning
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Demand Uncertainty
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Customer demands (over reticle life period) may not be
fully known at design time
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Only rough customer demand distribution available (e.g., min/max
demand)
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MPW become even more attractive in this context: sharing
of demand misprediction risks
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Online wafer dicing combined with production of larger
wafer lots can bring further economies of scale (see paper)

Feasible when there are no IP protection issues
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Robust Reticle Floorplaning
Given:
 Die sizes
 Maximum reticle size
 Distribution of customer orders
Find:
 Placement of dies within the reticle
To Minimize:
 Expected #wafers required to meet customer orders
over a fixed time horizon
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Compared Algorithms

HQ with production volume set to the expected customer
demand
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HQ+Cloning with production volume set to the expected
customer demand

Distribution-driven simulated annealing
 Use expected production cost for evaluating SA moves
 Monte-Carlo simulation used to estimate expected cost
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Robustness Results - Normal
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Robustness Results – Uniform
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Conclusions & Future Research
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Improved MPW design flow
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Schedule-aware partitioning: 60% average cost reduction
Project cloning: 10% average wafer cost reduction
HQ reticle floorplan: 15% average wafer cost reduction
Wafer shot-map definition: 13% average wafer cost reduction
MDP wafer dicing: 60% average wafer cost reduction
Future work
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Multi-layer reticle design
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