Chapter 6
FPGA Modules and Hardware Interface
Design
Professor Tzyy-Kuen Tien
E-mail: [email protected]
Http://www.eecs.stut.edu.tw
STUT/EE
Outline
6.1 The Implementation of IDCT on FPGA
6.2 AMBA I/O Interface Design
6.3 I/O Interface Design
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6.1 The Implementation of IDCT on FPGA
6.1 The Implementation of IDCT on FPGA
6.2 AMBA I/O Interface Design
6.3 I/O Interface Design
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6.1 Compression/Decompression System
 A block diagram of a compression/decompression system.
 DCT/IDCT can be used in the system to reduce the
bandwidth requirements.
Input Signal
Source
Coder
Encoder
Channel
Coder
Reconstructed
Output Signal
Source
Decoder
Decoder
Channel
Decoder
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6.1 Introduction to IDCT
 Inverse Discrete Cosine Transform.
 IDCT is used to decompress DCT compressed data in the
decoder.
 IDCT is one of the most computation-intensive parts of the
MPEG decoding process.
 A fast, hardware based IDCT implementation is crucial to
speed the MPEG decoding process.
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6.1 2D IDCT Equations (1/2)
 The algorithm used for the calculation of the 2D IDCT
coefficients is based on the following equation:
M-1
XCpq = ∑
m=0
N-1
c(p)c(q)
∑
XNmn ·
4
n=0
·cos
Π(2m+1)p
2M
·cos
Π(2n+1)q
(EQ 1)
2N
 First, the 1D DCT of the rows are calculated and then the 1D
IDCT of the columns are calculated.
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6.1 2D IDCT Equations (2/2)
 The 1D IDCT coefficients for the rows and columns can be
calculated by separating equation 1 into the row part and
the column part.
C = K · cos
(2·col number + 1) · row number ·Π
2·M
√2
√1
K=
Ct
N
= K · cos
for row = 0,
M
K=
N
for row ≠ 0
(2·row number + 1) · col number ·Π
(EQ 3)
2·N
√2
√1
K=
(EQ 2)
for col = 0,
K=
M
for col ≠ 0
M = total number of columns, N = total number of rows.
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6.1 Constant Values of C and Ct
 The constant values for C and Ct calculated from equations
2 and 3 are as follows:
C=
Ct =
23170 23170 23170
32138 27246 18205
30274 12540 –12540
27246 –6393 –32138
23170 –23170 –23170
18205 –32138 6393
12540 –30274 30274
6393 –18205 27246
23170 23170 23170 23170
6393 –6393 –18205 –27246
–30274 –30274 –12540 12540
–18205 18205 32138 6393
23170 23170 –23170 –23170
27246 –27246 –6393 32138
–12540 –12540 30274 –30274
–32138 32138 –27246 18205
23170
–32138
30274
–27246
23170
–18205
12540
–6393
23170 32138 30274 27246 23170 18205 12540 6393
23170 27246 12540 –6393 –23170 –32138 –30274 –18205
23170 18205 –12540 –32138 –23170 6393 30274 27246
23170 6393 –30274 –18205 23170 27246 –12540 –32138
23170 –6393 –30274 18205 23170 –27246 –12540 32138
23170 –18205 –12540 32138 –23170 –6393 30274 –27246
23170 –27246 12540 6393 –23170 32138 –30274 18205
23170 –32138 30274 –27246 23170 –18205 12540 –6393
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6.1 2D IDCT using Vector Processing
 A one-dimensional 8-point IDCT followed by an internal
double buffer memory, followed by another one-dimensional
8-point IDCT provides the 2D IDCT architecture.
1D IDCT
RAM Double
Buffer
1D IDCT
 Vector processing using parallel multipliers is a method used
for implementation of IDCT.
 Advantages of vector processing method.
 Regular structure, simple control and interconnect, good
balance between performance and complexity of
implementation.
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6.1 Behavioral Model (1/2)
 The output Y of an 8‧8 IDCT for input X is given by Y =
C‧X‧Ct, where C is the cosine coefficients and Ct is the
transpose coefficients.
 The equation can also be written as Y = Ct‧Z, where Z = X‧C.
X=
x00 x01 x02 x03 x04 x05 x06 x07
x10 x11 x12 x13 x14 x15 x16 x17
x20 x21 x22 x23 x24 x25 x26 x27
x30 x31 x32 x33 x34 x35 x36 x37
x40 x41 x42 x43 x44 x45 x46 x47
x50 x51 x52 x53 x54 x55 x56 x57
x60 x61 x62 x63 x64 x65 x66 x67
x70 x71 x72 x73 x74 x75 x76 x77
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23170 23170 23170 23170 23170 23170 23170
32138 27246 18205 6393 –6393 –18205 –27246
30274 12540 –12540 –30274 –30274 –12540 12540
C = 27246 –6393 –32138 –18205 18205 32138 6393
23170 –23170 –23170 23170 23170 –23170 –23170
18205 –32138 6393 27246 –27246 –6393 32138
12540 –30274 30274 –12540 –12540 30274 –30274
6393 –18205 27246 –32138 32138 –27246 18205
第六章：FPGA模組與硬體介面設計
23170
–32138
30274
–27246
23170
–18205
12540
–6393
P-10/93
6.1 Behavioral Model (2/2)
Z(0,0) = 23170x00 + 32138x01 + 30274x02 + 27246x03 + 23170x04 + 18205x05 + 12540x06 + 6393x07
Z(0,1) = 23170x00 + 27246x01 + 12540x02 – 6393x03 – 23170x04 – 3213805 – 30274x06 – 18205x07
Z(0,2) = 23170x00 + 18205x01 – 12540x02 – 32138x03 – 23170x04 + 6393x05 + 30274x06 + 27246x07
Z(0,3) = 23170x00 + 6393x01 – 30274x02 – 18205x03 + 23170x04 + 27246x05 – 12540x06 – 3213807
Z(0,4) = 23170x00 – 6393x01 – 30274x02 + 18205x03 + 23170x04 – 27246x05 – 12540x06 + 32138x07
Z(0,5) = 23170x00 – 18205x01 – 12540x02 + 32138x03 – 23170x04 – 6393x05 + 30274x06 – 27246x07
Z(0,6) = 23170x00 – 27246x01 + 12540x02 + 6393x03 – 23170x04 + 32138x05 – 30274x06 + 18205x07
Z(0,7) = 23170x00 – 32138x01 + 30274x02 – 27246x03 + 23170x04 – 18205x05 + 12540x06 – 6393x07
Or:
Z(k,0) = (23170xk0 + 30274xk2 + 23170xk4 + 12540xk6) + (32138xk1 + 27246xk3 + 18205xk5 + 6393xk7)
= P01 + P02
Z(k,1) = (23170xk0 + 12540xk2 – 23170xk4 – 30274xk6) + (27246xk1 – 6393xk3 – 32138xk5 – 18205xk7)
= P11 + P12
Z(k,2) = (23170xk0 – 12540xk2 – 23170xk4 + 30274xk6) + (18205xk1 – 32138xk3 + 6393xk5 + 27246xk7)
= P21 + P22
Z(k,3) = (23170xk0 – 30274xk2 + 23170xk4 – 12540xk6) + (6393xk1 – 18205xk3 + 27246xk5 – 32138xk7)
= P31 + P32
Z(k,4) = P31 – P32
Z(k,5) = P21 – P22
Z(k,6) = P11 – P12
Z(k,7) = P01 – P02
where k = 0, 2, …, 7
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6.1 1D IDCT
 The block diagram for the implementation of the 1D IDCT is
shown below.
×IN
23170 23170 23170 23170 23170 23170 23170 23170
32138 27246 18205 6393 -6393 -18205 -27246 -32138
30274 12540 -12540 -30274 -30274 -12540 12540 30274
27246 -6393 -32138 -18205 18205 32138 6393 -27246
23170 -23170 -23170 23170 23170 -23170 -23170 23170
18205 -32138 6393 27246 -27246 -6393 32138 -18205
12540 -30274 30274 -12540 -12540 30274 -30274 12540
6393 -18205 27246 -32138 32138 -27246 18205 -6393
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S
h
i
f
t
R
e
g
i
s
t
×
×
×
×
×
×
×
×
×K0
×K1
×K2
×K3
×K4
A
d
d
e
r
ZK(0 to 7)
×K5
×K6
×K7
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6.2 AMBA I/O Interface Design
6.1 The Implementation of IDCT on FPGA
6.2 AMBA I/O Interface Design
6.3 I/O Interface Design
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6.2 AMBA I/O Interface Design
 Introduction to the AMBA buses
 AMBA AHB bus
 AMBA ASB bus
 AMBA APB bus
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6.2 Introduction (1/5)
 What is AMBA?
 The Advanced Microcontroller Bus Architecture
specification.
 An on-chip communication standard for designing highperformance embedded microcontroller.
 Three distinct buses.
 AHB (the Advanced High-performance Bus).
High-performance system backbone bus.
 ASB (the Advanced System Bus).
An alternative system bus.
 APB (the Advanced Peripheral Bus).
Minimal power consumption.
Reduced interface complexity.
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6.2 Introduction (2/5)
 Objectives of the AMBA specification.
 To facilitate the right-first-time development of embedded
microcontroller products.
 To be technology-independent.
 To ensure that highly reusable peripheral and system.
macrocells can be migrated across a diverse range of IC
processes.
 To encourage modular system design.
 To minimize the silicon infrastructure required for both
operation and manufacturing test.
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6.2 Introduction (3/5)
 Typical AMBA system.
High-performance
ARM-processor
High-bandwidth
External Memory
Interface
High-bandwidth
On-chip RAM
AHB or ASB
B
R
I
D
G
E
UART
Timer
APB
Keypad
PIO
DMA bus
master
AHB to APB Bridge
Or
ASB to APB Bridge
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6.2 Introduction (4/5)
 Feature
Feature
AMBA AHB
AMBA ASB
AMBA APB
High performance
High performance
Low power
Pipelined operation
Pipelined operation
Latched address and control
Multiple bus masters
Multiple bus masters
Simple interface
Burst transfers
Burst transfers
Suitable for many
peripherals
Split transactions
Dual-clock edge
operation
Single-clock edge operation
(rising edge)
AHB master
ASB master
APB bridge (slave on AHB or
ASB)
AHB slave
ASB slave
APB slave
AHB arbiter
ASB arbiter
AHB decoder
ASB decoder
Single-cycle bus master
handover
Single-clock edge operation
(rising edge)
Wider data bus configuration
Components
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6.2 Introduction (5/5)
 When to use AMBA AHB/ASB or APB.
 A full AHB or ASB.
 Bus masters.
 On-chip memory blocks.
 External memory interface.
 High-bandwidth peripherals with FIFO interfaces.
 DMA slave peripherals.
 A simple APB interface.
 Simple register-mapped slave devices.
 Very low power interfaces where clocks cannot be
globally routed.
 Grouping narrow-bus peripherals to avoid loading
the system bus.
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6.2 AMBA I/O Interface Design
 Introduction to the AMBA buses
 AMBA AHB bus
 AMBA ASB bus
 AMBA APB bus
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6.2 A Typical AHB and APB System
High-performance
ARM-processor
High-bandwidth
on-chip RAM
B
R
I
D
G
E
AHB
High-bandwidth
Memory Interface
DMA bus
master
UART
Timer
APB
Keypad
PIO
AHB to APB Bridge
AMBA Advanced High-performance Bus (AHB)
AMBA Advanced Peripheral Bus (APB)
*High performance
*Low power
*Pipelined operation
*Latched address and control
*Burst transfers
*Simple interface
*Multiple bus masters
*Suitable for many peripherals
*Split transactions
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6.2 AMBA AHB Bus Interconnect
 Multiplexor interconnection.
Arbiter
HADDR
HWDATA
HADDR
Master
#1
HRDATA
HWDATA
HRDATA
HADDR
HWDATA
HADDR
Master
#2
HWDATA
Address and
control mux
HRDATA
HRDATA
HADDR
Master
#3
Slave
#1
HWDATA
HADDR
HWDATA
Write data mux
Read data mux
HRDATA
HRDATA
Slave
#2
Slave
#3
HADDR
HWDATA
HRDATA
Slave
#4
Decoder
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6.2 AMBA AHB Transfer Type
 Transfer type encoding.
 HTRANS[1:0]
 00 – IDLE
No data transfer is required.
 01 – BUSY
Bus masters insert IDLE cycles in the middle of bursts of
transfers.
 10 – NONSEQ
The first transfer of a burst or a single transfer is initiated.
 11 – SEQ
The remaining transfers are in a burst.
The address is related to the previous transfer.
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6.2 Slave Transfer Responses
 Response encoding.
 HRESP[1:0]
 00 – OKAY.
 01 – ERROR.
 10 – RETRY.
The signal shows the transfer has not yet completed,
so the bus master should retry the transfer.
 11 – SPLIT
The slave will request access to the bus on behalf of
the master when the transfer can complete.
 If the response is the one among ERROR, RETRY and
SPLIT, a two-cycle response is required.
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6.2 AMBA AHB Bus Arbitration
 Bus master grant signals.
 The HGRANTx signal is only used by the master to
determine when it owns the bus.
HMASTER[3:0]
HGRANT_M1
Decoder
Master
HADDR_M1[31:0]
#1
Arbiter
HGRANT_M2
Master
HADDR_M2[31:0]
HADDR to all slaves
#2
Address and Control
multiplex
HGRANT_M3
Master
HADDR_M3[31:0]
#3
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6.2 AMBA AHB Bus Slave
 AHB bus slave interface.
Select
HSELx
HADDR[31:0]
Address
and
control
HWRITE
HTRANS[1:0]
HSIZE[2:0]
HBURST[2:0]
Data
Reset
Clock
HREADY
AHB
slave
HWDATA[31:0]
HRESP[1:0]
HRDATA[31:0]
Transfer
response
Data
HRESETn
HCLK
HMASTER[3:0]
HMASTLOCK
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Split-capable
slave
HSPLITx[15:0]
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6.2 AMBA AHB Bus Master
 AHB bus master interface.
HBUSREQx
Arbiter
grant
HLOCKx
Arbiter
HTRANS[1:0]
Transfer type
HGRANTx
HREADY
Transfer
response
HRESP[1:0]
Reset
HRESETn
Clock
HCLK
HADDR[31:0]
AHB
master
HWRITE
HSIZE[2:0]
Address
and
control
HBURST[2:0]
Data
HRDATA[31:0]
HPROT[3:0]
HWDATA[31:0]
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Data
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6.2 AMBA AHB Arbiter
 AHB arbiter interface.
HBUSREQx1
HLOCKx1
Arbiter
requests
and locks
HBUSREQx2
HLOCKx2
HBUSREQx3
HGRANTx1
HLOCKx3
HGRANTx2
HADDR[31:0]
Address
and control
HSPLITx[15:0]
HTRANS[1:0]
HBURST[2:0]
AHB
arbiter
HGRANTx3
Arbiter
grants
HMASTER[3:0]
HMASTLOCK
HRESP[1:0]
HREADY
Reset
HRESETn
Clock
HCLK
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6.2 AMBA I/O Interface Design
 Introduction to the AMBA buses
 AMBA AHB bus
 AMBA ASB bus
 AMBA APB bus
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6.2 A Typical AMBA ASB-based Microcontroller
 A typical AMBA system.
High-performance
ARM-processor
High-bandwidth
Memory Interface
High-bandwidth
on-chip RAM
B
R
I
D
G
E
ASB
DMA bus
master
UART
APB
Keypad
PIO
ASB to APB Bridge
AMBA Advanced System Bus (ASB)
AMBA Advanced Peripheral Bus (APB)
*High performance
*Low power
*Pipelined operation
*Latched address and control
*Burst transfers
*Simple interface
*Multiple bus masters
*Suitable for many peripherals
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Timer
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6.2 AMBA ASB Description
 Basic flow of the bus operation.
 The arbiter determines which master is granted access to the
bus.
 When granted, a master initiates transfers on the bus.
 The decoder uses the high order address lines to select a bus
slave.
 The slave provides a transfer response back lines to the bus
master and data is transferred between the master and slave.
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6.2 ASB Transfers
 Three types of transfer.
 NONSEQUENTIAL
Used for signal transfers or the first transfer of a burst.
 SEQUENTIAL
Used for transfers in a burst. The address of a
SEQUENTIAL transfer is always related to the
previous transfer.
 ADDRESS-ONLY
Used when no data movement is required.
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6.2 AMBA ASB Bus Slave
 ASB bus slave interface.
Select
DSEL
BA[31:0]
Address
and
control
BWRITE
BSIZE[1:0]
Reset
BnRES
Clock
BCLK
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BWAIT
ASB
slave
BERROR
BLAST
BD[31:0]
Transfer
response
Data
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6.2 AMBS ASB Bus Master
 ASB bus master interface.
Arbiter
grant
AREQ
AGNT
BLOK
Arbiter
BTRAN[1:0]
Transfer type
BWAIT
Transfer
response
BERROR
BLAST
ASB
master
BA[31:0]
BWRITE
Reset
BnRES
BSIZE[1:0]
Clock
BCLK
BPROT[1:0]
BD[31:0]
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Address
and
control
Data
第六章：FPGA模組與硬體介面設計
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6.2 AMBA ASB Bus Decoder
 ASB decoder interface.
DSEL1
Transfer type
BTRAN[1:0]
DSEL1
…..
BA[31:0]
Address
and
control
BWRITE
BSIZE[1:0]
BPROT[1:0]
DSELn
ASB
decoder
BWAIT
Reset
BnRES
BERROR
Clock
BCLK
BLAST
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Selects
Transfer
response
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6.2 AMBA ASB Bus Arbiter
 ASB arbiter interface.
AREQx1
AGNTx1
Arbiter
requests
AREQx2
AGNTx2
AREQx3
AGNTx3
Wait
BWAIT
Lock
BLOK
Reset
BnRES
Clock
BCLK
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Arbiter
grants
ASB
arbiter
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6.2 AMBA I/O Interface Design
 Introduction to the AMBA buses
 AMBA AHB bus
 AMBA ASB bus
 AMBA APB bus
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6.2 A Typical AMBA-based Microcontroller
 AMBA Advanced Peripheral Bus (APB).
High-performance
ARM-processor
High-bandwidth
Memory Interface
High-bandwidth
on-chip RAM
B
R
I
D
G
E
AHB or ASB
DMA bus
master
UART
Timer
APB
Keypad
PIO
APB Bridge
AMBA Advanced Peripheral Bus (APB)
*Low power
*Latched address and control
*Simple interface
*Suitable for many peripherals
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6.2 Avtivity of the Peripheral Bus
 State diagram.
 IDLE
 The default state for the peripheral bus.
 SETUP
 The bus moves into this state when a
transfer is required.
 The bus remains in the SETUP state for
one clock and will always move to the
ENABLE state.
 PSELx is asserted.
 ENABLE
 PENABLE is asserted.
 The address, write and select signals all
remain stable during SETUPENABLE.
 Glitch is acceptable during
No transfer
ENABLESETUP.
教育部顧問室PAL聯盟/系統雛型與軟硬體整合設計
No transfer
IDLE
PSELx = 0
PENABLE = 0
Transfer
SETUP
PSELx = 1
PENABLE = 0
ENABLE
PSELx = 1
PENABLE = 1
第六章：FPGA模組與硬體介面設計
Transfer
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6.2 AMBA APB Interface Design
 APB bridge interface.
PSEL1
PSEL2
.
.
.
PSELn
System bus
slave interface
APB
slave
PENABLE
PADDR
Read data
PRDATA
PWRITE
Reset
Clock
Selects
Strobe
Address
and
control
PRESETn
PCLK
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PRDATA
Write data
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6.2 AMBA APB Slave
 APB slave interface.
Select
Strobe
Address
and
control
Reset
Clock
PSELx
PENABLE
PADDR
PWRITE
APB
slave
PRESETn
PCLK
PRDATA
Write data
Read data
PWDATA
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6.3 I/O Interface Design
6.1 The Implementation of IDCT on FPGA
6.2 AMBA I/O Interface Design
6.3 I/O Interface Design
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6.3 I/O Interface
 Provides a method for transferring information between
CPU (or internal storage) and external I/O devices.
 I/O devices connected to a computer need special
communication links for interfacing them with the CPU.
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6.3 Purposes of the Communication Link
 Conversion of signal values.
 The manner of operation for an I/O device may be
different from the operation of the CPU.
 Providing a synchronization mechanism.
 The data transfer rate of I/O devices is usually slower
than the transfer rate of the CPU.
 Word format transformation.
 Data codes and formats in I/O differ from the word
format in the CPU.
 The control of I/O devices.
 To ensure the operation of an I/O device is not disturbed
by another I/O devices.
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6.3 I/O Bus and Interface Modules
 The I/O bus consists of data lines, address lines, and control
lines.
Data
Address
Control
Processor
Processor
Interface
Interface
Interface
Keyboard
and
display
terminal
Printer
Magnetic
disk
Magnetic
tape
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6.3 I/O versus Memory Bus
 There are three ways that computer buses can be used to
communicate with memory and I/O:
 Use two separate buses, one for memory and the other
for I/O.
 Use one common bus for both memory and I/O but have
separate control lines for each.
 Use one common bus for memory and I/O with common
control lines.
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6.3 Isolated versus Memory-Mapped I/O
 Isolated I/O.
 Isolate all I/O interface addresses from the addresses
assigned to memory.
 Distinct input and output instructions for I/O transfer.
 Memory-mapped I/O.
 Use the same address space for both memory and I/O.
 No specific input or output instructions.
 The CPU manipulates I/O data with the same
instructions that are used to manipulate memory words.
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6.3 Example of I/O Interface
Bidirectional
data bus
Bus
buffers
Port A
register
I/O data
Port B
register
I/O data
Control
register
Control
Status
register
Status
Chip select
Register select
RS1
RS0
I/O read
I/O write
RD
WR
To CPU
CS RS1
RS0
Timing
and
control
Internal bus
CS
To I/O device
Register selected
0
X
X
None: data bus in high-impedance
1
0
0
Port A register
1
1
0
1
1
0
Port B register
Control register
1
1
1
Status register
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6.3 Asynchronous Data Transfer
 Asynchronous data transfer between two independent units
requires control signals to transmit data.
 Two different types of control mechanism for data
transferring between two independent units .
 Strobe control.
 Handshaking.
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6.3 Strobe Control (1/3)
 The strobe control method employs a single control line to
time each transfer.
 The strobe may be activated by either the source or the
destination.
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6.3 Strobe Control (2/3)
 Source-initiated strobe for data transfer.
Data bus
Source
unit
Strobe
Destination
unit
(a) Block diagram
Data
Valid data
Strobe
(b) Timing diagram
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6.3 Strobe Control (3/3)
 Destination-initiated strobe for data transfer.
Data bus
Source
unit
Strobe
Destination
unit
(a) Block diagram
Data
Valid data
Strobe
(b) Timing diagram
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6.3 Problem of Strobe Method
 The disadvantage of the strobe method is that the source
(destination) unit that initiates the transfer has no way of
knowing whether the destination (source) unit has actually
received the data item that was placed in the bus.
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6.3 Handshaking
 The basic principle of the two-wire handshaking method of
data transfer is as follows.
 One control line from the source unit is used to inform
the destination whether there are valid data in the bus.
 The other control line from the destination unit is used
to inform the source whether it can accept data.
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6.3 Data Transfer by Handshaking (1/2)
 Data transfer procedure initiated by the source.
Data bus
Source
unit
Data valid
Data accepted
(a) Block diagram
Valid data
Data bus
Destination
unit
Source unit
Destination unit
Place data on bus.
Enable data valid.
Accept data from bus.
Enable data accepted.
Data valid
Disable data valid.
Invalidate data on bus.
Data accepted
(b) Timing diagram
教育部顧問室PAL聯盟/系統雛型與軟硬體整合設計
Disable data accepted.
Ready to accept data
(initial state).
(c) Sequence of events
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6.3 Data Transfer by Handshaking (2/2)
 Data transfer procedure initiated by the destination.
Data bus
Source
unit
Data valid
Ready for data
Destination
unit
Destination unit
Source unit
(a) Block diagram
Ready to accept data.
Enable ready for data.
Place data on bus.
Enable data valid.
Ready for bus
Accept data from bus.
Disable ready for data.
Data valid
Disable data valid.
Invalidate data on bus
(initial state).
Data bus
Valid data
(b) Timing diagram
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(c) Sequence of events
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6.3 Asynchronous Serial Transfer
 A serial asynchronous data transmission technique employs
special bits that are inserted at both ends of the character
code.
 With this technique, each character consists of three parts:
 A start bit.
 The character bits.
 Stop bits.
1
1
0
Start
bit
教育部顧問室PAL聯盟/系統雛型與軟硬體整合設計
0
0
Character bits
1
0
1
Stop
bits
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6.3 Asynchronous Communication Interface
data bus
Chip select
Bus
buffer
Transmitter
register
CS
Register select
I/O read
RS
RD
I/O write
Timing
and
control
Internal bus
Bidirectional
Shift
register
Control
register
Transmitter
control
and clock
Status
register
Receiver
control
and clock
WR
Receiver
register
CS
RS
Operation
0
1
1
1
1
X
0
1
0
1
X
WR
WR
RD
RD
教育部顧問室PAL聯盟/系統雛型與軟硬體整合設計
Shift
register
Transmit
data
Transmitter
clock
Receiver
clock
Receive
data
Register selected
None：data bus in high-impedance
Transmitter register
Control register
Receiver register
Status register
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6.3 Modes of Transfer
 Data transfer to and from I/O devices may be handled in
one of three possible modes.
 Programmed I/O.
 Interrupt-initiated I/O.
 Direct memory access (DMA).
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6.3 Programmed I/O
 Programmed I/O operations are the result of I/O
instructions written in the computer program.
 Each data item transfer is initiated by an instruction in the
program.
 Transferring data under program control requires constant
monitoring of the I/O by the CPU.
 The I/O device does not have direct access to memory.
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6.3 Example of Programmed I/O
 The steps of data transfer.
 I/O device places data to the I/O bus and enables the
data valid line.
 The interface accepts the data into its register and
enables the data accepted line.
 The interface sets a bit of flag “F”.
 The CPU reads the data from the interface according to
flag “F”.
Data bus
Address bus
CPU
Interface
I/O bus
Data register
Data valid
I/O read
I/O write
Status
register
F
Data accepted
I/O
device
F = Flag bit
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6.3 Flowchart for CPU Reads Data From I/O
Read data register
Check flag bit
=0
Flag
=1
Read status register
Transfer data to memory
Operation
Complete?
no
yes
Continue
with
program
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6.3 Interrupt-Initiated I/O
 Instead of constantly monitoring the flag, the CPU is
informed to receive data when an interrupt signal happens
from the interface.
 The CPU responds to the interrupt signal by storing the
return address from the program counter into a memory
stack and then control branches to a service routine that
processes the required I/O transfer.
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6.3 Priority Interrupt
 The system establishes a priority over the various sources to
determine which condition is to be serviced first when two
or more requests arrive simultaneously .
 Two methods of priority interrupt.
 Software priority-interrupt.
A polling procedure.
 Hardware priority-interrupt.
Daisy-chaining priority.
Parallel priority-interrupt.
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6.3 Daisy-Chain Priority Interrupt
Processor data bus
Device 3
Device 2
Device 1
PI
VAD3
VAD2
VAD1
PO
PI
PO
PO
PI
Interrupt request
To next
device
INT
CPU
Interrupt acknowledge
INTACK
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6.3 Parallel Priority-Interrupt
Interrupt
register
Disk
0
Printer
1
VAD
to CPU
I0
y
Reader
2
Keyboard
3
x
I1
I2
0
Priority
encoder
0
0
0
0
I3
0
Enable
IEN
IST
0
1
2
3
Interrupt
to CPU
INTACK
from CPU
Mask
register
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6.3 DMA
 Removing the CPU from the path and letting the I/O
devices manage the memory directly.
 During DMA transfer, the CPU is idle and has no control of
the memory buses.
 Two signals are used to facilitate the DMA transfer.
 Bus request: a signal from DMA controller.
 Bus grant: the CPU informs the DMA that the buses are
in high-impedance state.
Bus request
BR
CPU
Bus grant
BG
教育部顧問室PAL聯盟/系統雛型與軟硬體整合設計
DBUS
Address bus
ABUS
Data bus
RD
Read
WR
Write
High-impedance
(disable)
when BG is
enable
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6.3 DMA Controller
 Block diagram of DMA controller.
Address bus
Data bus
buffer
DMA select
DS
Register select
RS
Read
RD
Write
WR
Bus request
BR
Bus grant
BG
Interrupt
Control
logic
Interrupt
教育部顧問室PAL聯盟/系統雛型與軟硬體整合設計
Address bus
buffer
Address register
Internal bus
Data bus
Word count register
Control register
DMA request
DMA Acknowledge
to I/O device
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6.3 Initialization of DMA
 The CPU initializes the DMA by sending the following
information through the data bus.
 Starting address of the memory block.
 Word count.
 Mode of transfer.
 A start signal to do DMA transfer.
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6.3 DMA Transfer
Interrupt
Random-access
memory (RAM)
CPU
BG
BR
RD
WR
Address Data
RD
WR
Address Data
Read control
Write control
Data bus
Address bus
Address
select
RD
DS
RS
BR
WR
Address Data
Direct memory
access (DMA)
controller
BG
DMA acknowledge
DMA request
I/O
Peripheral
device
Interrupt
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References
 http://www.xilinx.com/bvdocs/appnotes/xapp611.pdf
 http://www.arm.com/products/solutions/AMBA_Spec.html
 Mano, M. Morris, “Computer system architecture,” Prentice
Hall,1993.
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