The GBT-FPGA project
GBT
GBT
Versatile Link
FPGA
Timing & Trigger
Timing & Trigger
GBTIA
DAQ
GBTX
PD
DAQ
GBLD
LD
Slow Control
Slow Control
Custom ASICs
On-Detector
Radiation Hard Electronics
Off-Detector
Commercial Off-The-Shelf (COTS)
• Started in 2009 as a simple proof-of-concept,
Code implemented on an Altera SIIGx and a Xilinx V5
Interoperability validated, link characterized
Presented at TWEPP2009
• Core made available, studies conducted on determinism, used to test the GBT prototype
• Many requests from various teams and for various usages
• Project launched in 2013, Manoel started to work on it extensively
03/02/2015
S. Baron, BE-BI & PH-ESE GBT/VL meeting
1
Pure Concept
One single IP core as generic as possible to be
ported on all FPGAs …
TX_WORDCLK
(120MHz or
240MHz)
MGT_TXOUTCLK (120MHz or 240MHz)
TX_FRAMECLK
(40MHz)
GBT TX
120bit
84bit
TX_DATA
40bit
or
20bit
Scrambler
MGT TX
1bit
GearBox
GBT-Frame
Encoder
TX
Serial
Data
MGT_REFCLK
(120MHz or 240MHz)
MGT
GBT RX
MGT RX
Barrel
Shifter
84bit
120bit
DeScrambler
RX_DATA
GBT-Frame
Decoder
GearBox
Pattern
Search
40bit
or
20bit
1bit
Frame Aligner
/
03/02/2015
RX_WORDCLK
(120MHz or 240MHz)
RX_FRAMECLK (40MHz)
S. Baron, BE-BI & PH-ESE GBT/VL meeting
MGT_RXRECCLK (120MHz or 240MHz)
2
RX
Serial
Data
Realistic Concept
Allowing all the encoding modes offered by the
GBTx …
TX_WORDCLK
(120MHz or
240MHz)
MGT_TXOUTCLK (120MHz or 240MHz)
TX_FRAMECLK
(40MHz)
GBT TX
4bit
8b10b
TX_8b10_EXTRADATA
TX_DATA
TX_WIDEBUS_EXTRADATA
ISDATA_SEL
84bit
32bit
Wide-bus
4bit
(120MHz or 240MHz)
Barrel
Shifter
8b10b
84bit
120bit
GBT-Frame
DeScrambler
Wide-bus
Decoder
/
1bit
GearBox
TX
Serial
Data
MGT
GBT RX
32bit
03/02/2015
RX_WORDCLK
MGT TX
Encoder
MGT_REFCLK
(120MHz or 240MHz)
RX_8b10_EXTRADATA
RX_DATA
RX_WIDEBUS_EXTRADATA
ISDATA_FLAG
120bit
GBT-Frame
Scrambler
40bit
or
20bit
RX_FRAMECLK (40MHz)
GearBox
Pattern
Search
40bit
or
20bit
MGT RX
1bit
Frame Aligner
S. Baron, BE-BI & PH-ESE GBT/VL meeting
MGT_RXRECCLK (120MHz or 240MHz)
3
RX
Serial
Data
Reality
Ensuring a low, fixed and deterministic phase
and latency of the recovered clock and signals
TX_WORDCLK
(120MHz or
240MHz)
MGT_TXOUTCLK (120MHz or 240MHz)
TX_FRAMECLK
(40MHz)
TX_8b10_EXTRADATA
TX_DATA
TX_WIDEBUS_EXTRADATA
ISDATA_SEL
GBT TX
4bit
8b10b
84bit
32bit
RX_FRAMECLK
Phase
Aligner
/
03/02/2015
RX_WORDCLK
(120MHz or 240MHz)
MGT TX
GearBox
1bit
PISO
Wide-bus
TX
Serial
Data
SerialClk
(2400MHz)
Tx PLL
Encoder
MGT_REFCLK
(120MHz or 240MHz)
RX_8b10_EXTRADATA
RX_DATA
RX_WIDEBUS_EXTRADATA
ISDATA_FLAG
120bit
GBT-Frame
Scrambler
40bit
or
20bit
MGT
GBT RX
4bit
84bit
120bit
GBT-Frame
32bit
Barrel
Shifter
8b10b
DeScrambler
Wide-bus
Decoder
GearBox
Pattern
Search
Bitslip
Control
Frame Aligner
RX_FRAMECLK (40MHz)
S. Baron, BE-BI & PH-ESE GBT/VL meeting
40bit
or
20bit
MGT RX
Barrel
Shifter
SIPO
CDR
RXRECCLK
Phase
Aligner
1bit
RX
Serial
Data
/
MGT_RXRECCLK (120MHz or 240MHz)
4
Augmented Reality
GBT TX
MGT
GBT RX
GBT TX
MGT
GBT RX
TX_WORDCLK
(120MHz or
240MHz)
MGT_TXOUTCLK (120MHz or 240Mhz)
TX_FRAMECLK
(40MHz)
GBT TX
4bit
8b10b
84bit
TX_8b10_EXTRADATA
TX_DATA
TX_WIDEBUS_EXTRADATA
ISDATA_SEL
Scrambler
RX_FRAMECLK
Phase
Aligner
/
03/02/2015
RX_WORDCLK
(120MHz or 240MHz)
MGT TX
GearBox
1bit
PISO
Wide-bus
Serial
Data
Out
SerialClk
(2400MHz)
Tx PLL
Decoder
MGT_REFCLK
(120MHz or 240MHz)
RX_8b10_EXTRADATA
RX_DATA
RX_WIDEBUS_EXTRADATA
ISDATA_FLAG
120bit
GBT-Frame
32bit
40bit
or
20bit
MGT
GBT RX
4bit
Barrel
Shifter
8b10b
84bit
120bit
GBT-Frame
32bit
DeScrambler
Wide-bus
Decoder
GearBox
Pattern
Search
40bit
or
20bit
Bitslip
Control
Frame Aligner
MGT RX
Barrel
Shifter
SIPO
CDR
RXRECCLK
Phase
Aligner
1bit
Serial
Data
In
/
RX_FRAMECLK (40MHz)
S. Baron, BE-BI & PH-ESE GBT/VL meeting
MGT_RXRECCLK (120MHz or 240MHz)
5
2015 Status
• Available Package on svn: https://svn.cern.ch/reps/ph-ese/be/gbt_fpga
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Core code (VHDL)
Example Designs
Documentation & tutorials
TCL Scripts
Targeting
• Xilinx : Kintex 7 (FC7, KC705) , Virtex 7 (VC707), Virtex 6 (GLIB)
• Altera: Cyclone V (SAT, Cyclone V GT Devkit), Stratix V (AMC40), Arria V GT
(coming)
– Additional Unsupported Cores (GBTx and SCA slow control)
• Website: https://espace.cern.ch/GBT-Project/GBT-FPGA/default.aspx
• egroup : GBT-FPGA-users
• 120 users
– Some of them contributing very actively
03/02/2015
S. Baron, BE-BI & PH-ESE GBT/VL meeting
6