Power-Aware Variable Partitioning for
DSPs with Hybrid
PRAM and DRAM Main Memory
Tiantian Liu,
Yingchao Zhao,
Chun Jason Xue,
Minming Li
City University of Hong Kong
June 8, 2011
PRAM (phase change random access memory)
VS DRAM
PRAM
DRAM
WIN
Volatility
No
Access latency
Read: 60 ns
Read: 40–60 ns
Write: 100-1000ns
Write: 40–60 ns
Yes
No
Lifetime limitation
Yes
WIN
Sustain 108-109 writes
Power consumption No refresh and activation
power, lessWIN
leakage and
access power
WIN
Leakage, refresh,
activation, and access
power
Low power consumption
Hybrid both?
Less performance and
endurance degradation
What we do?
 PRAM or PCM (phase change memory)
 reduce write activities: redundant write removing, row shifting
Embedded and DSP
 Hybrid PRAM
DRAM (or other types)
Only&on
systems are application Dhiman et. al [DAC’09]:
hardware/controller
level proposes architecture and system
policies for managing a PRAM/DRAM based
main memory
specific
 Mogul et. al [HotOS’09]: provides OS support for a hybrid
NOR flash and PRAM main memory.
 This paper: software domain

Variable partitioning problem on a hybrid PRAM and DRAM
main memory.
Putting data in PRAM
can save power
Conflict
But will lead to many
writes on PRAM
Putting data in DRAM
can improve
performance
But will consume more
power
Reduce power consumption while minimizing
performance and endurance degradation!
Motivational example(1)
 Input
 A hybrid PRAM and DRAM memory architecture
 A DSP application represented by a Data Flow Graph (DFG)
0
a
1
4
a
b
2
b
6
d
c
3
A node: a variable access operation
or an Function Unit (FU) operations
5
A read
7
An edge: computation dependency
between nodes
An FU operation
8
9
c
d
A write
eg: a+b=d
10
a
11

Variable set = {a, b, c,d}
Different time latencies and power consumptions


trd(a), twd(a), trp(a), twp(a)
prd(a), pwd(a), prp(a), pwp(a)
 Output: to partition variables to different banks
 Objective 1 : The power consumption is minimized.
 Objective 2 : The number of writes on PRAM is minimized
Motivational example(2)
0
a
1
4
a
b
2
FU1
FU2
FU1
trd=1, twd=1,
……
Power &3writes & 7parallel:
8
9 with big
put the variables
c
d
write ratio10to DRAM
trp=2, twp=6,
DRAM
PRAM
DRAM1
(a) Two FUs, One PRAM + One DRAM
p
=5, pwd=5,
…rdDRAMi PRAM1
…
b
6
d
c
FUm
5
PRAMj
p =1, p =3
a
(b) m FUs,
+ j PRAMs
rp i DRAMs
wp
11
Parallel partitioning
DRAM PRAM
b
d
a
c
Our partitioning
DRAM PRAM
c
d
a
b
Schedule
length = 19;
Schedule
length = 18;
Power
consumption
= 29;
Power
consumption
= 27;
Writes on
PRAM=2.
Writes on
PRAM=1.
Reduced power consumption & reduced number of
writes on PRAM & reduced performance overhead
Main strategy
 Graph models



Interference Graph (IG), Leupers et. al [ICASSP’01]: access
interference between variables
Variable Independence Graph (VIG), Zhuge et. al [TSP’03]:
schedule step parallel potential between variables
PRAM-aware MAX CUT problem
 Heuristic methods



For power consumption: try not to put variables with too many
Variables with big write
accesses in DRAM;
ratio
DRAM
For endurance: try not to put variables with
tootomany
writes in
PRAM;
IG, VIG edge weights
For performance: try to put variables in different banks to
maximize parallel accesses.
 Integer Linear Programming (ILP)


Suppose with an initial schedule
Objectives: Min P, Min W, Min L
Experimental results
(d) (e): reduce 7988% writes than (b)

Techniques under comparison:

(a) pure DRAM banks & a parallel partitioning;

(b) pure PRAM banks & the parallel algorithm;

(c) a hybrid memory & the parallel algorithm;

(d) a hybrid memory & the proposed heuristic;

(e) a hybrid memory & the proposed ILP (lp_solve)
(d) (e): reduce 2736% writes than (c)
Comparison of writes: baseline (b)
Comparison of power: baseline (a)
62%
45%
(d) (e): 8-11% better
than (c)
53%
56%
(d) sometimes can
obtain optimal solutions
(c) (e) lead to more
power consumption
than (d)
Comparison
of execution time:
(d) (e) : increase
baseline
(a)
about 2-18%
(d) (e): 2-5% better
than (c)
Conclusion：
Introducing PRAM will dramatically save power
Pure
DRAM: About 53-56% power saving VS About 2-18% time increasing
The proposed methods obtain better solutions
Pure PRAM: About 79-88% write reduction
Conclusion
 Contributions:




Hybrid PRAM and DRAM main memory
Variable partitioning problem
PRAM-aware heuristics
ILP optimal solutions
 Experimental results:


Pure DRAM: About 53-56% power saving VS About 2-18%
time increasing
Pure PRAM: About 79-88% write reduction
 Future work:

ILP without initial schedule: a global optimal
 To learn more, please come to my poster!