Cortex-M4 Processor
-Low Power and System Control Features
김민수
목차
1. Low power design
2. Low power feature
3. Developing low power applications
4. The SysTick timer
5. Self-reset
6. CPU ID base register
7. Configuration control register
8. Auxiliary control register
9. Co-processor access control register
1. Low power design
1.1. What dose low power mean in microcontroller?
- low power can benefit product design in many ways.
(battery size & life, lower EMI, simpler power design, etc. )
- low power measurement only focuses on the active current and
sleep current .
1. Low power design
1.2. Low power system requirements
Requirements
Typical measurements & Considerations
Active current
It mostly caused by dynamic power needed by memories,
peripherals and is also affected the actual program code.
Sleep mode
current
It is generally composed of leakage current in the Tr and
the current consumed by some of analog circuits.
Energy
efficiency
How much work can be done with a limited amount of
energy?
The measurement is based on popular benchmarks.
Wake-up
latency
Typically, it is the time from a hardware request to the
time the processor resume program execution
- Some of the above factors are more important factors than others.
It depends on requirements of application.
1. Low power design
1.3. Low power characteristics of the Cortex-M3&M4
- Low power design; silicon area↑ -> power consumption↑
8-,16-bit’s silicon area<Cortex’s<other 32-bit’s
- High performance;
Users can run the processor at a lower clock frequency or have
the processor finish the processing task quicker and stay in sleep
mode longer.
- High code density;
Because the Thumb instruction set offers excellent code density,
users can use the processor with a smaller flash memory.
2. Low power feature
2.1. Sleep modes
- Cortex-M4 support two sleep
modes(Sleep & Deep Sleep).
- What exactly happens during
sleep modes depends on the
chip designs.
2. Low power feature
2.2. System control register(SCR)
Bits Name
Type Reset
value
Descriptions
4
SEVONPEND
R/W
0
Set 1; the processor wakes up
from WFE if a new interrupt is
pended, regardless of interrupt’s
priority and whether it was
enabled
2
SLEEPDEEP
R/W
0
Set 1; the deep sleep mode is
selected.
1
SLEEPONEXIT
R/W
0
Set 1; It enables the sleep on
exit
- SCR can be accessed in privileged state.
2. Low power feature
2.3. Entering sleep modes
Instruction Descriptions
WFI
The processor can wake-up by interrupt request, debug
request or reset.
WFE
Enter sleep mode conditionally.
The processor enters sleep mode, when event register is
clear.
The processor can wake-up by interrupt request, event input,
debug request or reset.
2.4. Wake-up conditions
- If the sleep mode is entered using WFI or Sleep On Exit, the
interrupt request needs to be enabled and has a higher priority
than the current level for the wake-up to occur.
2. Low power feature
2.4. Wake-up conditions
-In WFE sleep, the processor can be woken up by event input
signal(RXEV) and events that happened in the past.
- SEVONPEND can be used to generate a wake-up event when
an interrupt request arrives and set the pending status, even if the
interrupt was disabled or had the same or lower priority that the
current level.
- SEVONPEND generates the wake-up event only when a
pending status switches from 0 to 1.
2. Low power feature
2.4. Sleep-on-Exit feature
- When this is enabled, the
processor automatically enters
sleep mode when exiting from
an exception handler.
- Unlike normal interrupt
handling sequences, the
stacking and unstacking
processes are minimized to
save power as well as memory.
- Sleep-On-Exit should be
enabled at the end of the
initialization.
2. Low power feature
2.7. Sleep extension/wake-up delay
- Cortex-M3&4 provide a set of signals to allow to the waking-up
to be delayed so that the rest of system can get ready.
2.8. Wake-up interrupt controller(WIC)
- During deep sleep, all the clock signals are stopped.
- WIC is interrupt detection circuit that is coupled with the NVIC
and linked to Power Management Unit and interrupt masking
information is transferred from NVIC to WIC.
2.9. Event communication interface
- The primary goal is to allow the processor to stay sleep mode
until a certain event has occurred(between a peripheral and
processor, between multiple processors).
3. Developing low power applications
- Reducing the active power ;
Choose the right device, Run at the right frequency, Turn off
unused clock, Running the program from SRAM etc.
- Reducing of active cycles ;
Utilizing sleep modes, Reducing run-time.
- Sleep mode current reduction ;
Using the right sleep mode, Utilizing power control features,
Power off flash memory during sleep.
4. The SysTick timer
4.1. Why have a SysTick timer?
- In modern operating systems, a periodic interrupt is needed to
ensure that the OS kernel can invoke regularly.
- The SysTick timer is a decrement 24-bit timer.
- Since all the Cortex-M processors have the same SysTick timer,
an OS written for Cortex-M can be reused on other Cortex-Ms.
4.2. Operation of the SysTick timer
- SysTick has SysTick Control and Status, SysTick Reload Value,
SysTick Current Value and SysTick Calibration register.
4. The SysTick timer
4.2. Operation of the SysTick timer
- When the counter is enabled, the current value register
decrements at every processor clock cycle or every rising edge of
the reference clock. If it reaches 0, it will reload the value from
the reload register.
- SysTick Calibration Register is available to allow the on-chip
hardware to provide calibration information for the software.
4.3. Using the SysTick timer
- To generate a periodic SysTick interrupt, use a CMSIS-Core
function “SysTick_Config”.
5. Self-reset
-SYSRESETREQ bit(bit2 in AIRCR) generates a system reset
request to the microcontroller’s system reset control logic.
The exact timing of the reset is device-specific.
-VECTRESET control bit(bit0 in AIRCR) is indented for use by
debuggers. Setting 1 to this bit, the processor reset without the
debug logic and does not reset the peripherals.
The VECTRESET happens almost immediately because the reset
path is not dependent on other logic circuits.
- Do not set SYSRESETREQ and VECTRESET simultaneously.
- Set PRIMASK before starting the self-reset operation. Otherwise
reset could occur in the middle of interrupt handler.
-DMB instruction is needed to make sure previous memory accesses
are completed before the reset happens.
6. CPU ID base register
- This register is a read-only register that shows the processor
type and reversion number(privileged access only).
7. Configuration control register
- This register can be used to adjust some of the behaviors in the
processor and for controlling advanced features.
7. Configuration control register
Bits Name
Type Reset Descriptions
- This register is a read-only register
that shows the processor
value
type and reversion number(privileged access only).
9
STKALIGN
R/W
0 OR
1
7.
Configuration
control
register
8
BFHFNMIGN
R/W 0
Force exception stacking
start in double-word aligned
address.
Ignore data bus fault during
and NMI in
handlers.
- This register can be used to adjust someHardFault
of the behaviors
the
processor
and for controllingR/W
advanced
features.
4
DIV_0_TRP
0
Trap on divide by 0.
3
UNALIGN_TRP
R/W
0
Trap on unaligned accesses.
1
USERSETMPEND
R/W
0
If set to 1, allow user code to
software trigger interrupt
register.
0
NONBASETHRDENA R/W
0
If set to 1, allow exception
handler to return to thread
state.
8. Auxiliary control register
Bits Name
Type Reset
value
Descriptions
2
DISFOLD
R/W
0
Disable IT(If-Then) folding.
1
DISDEFWBUF R/W
0
Disable write buffer for default
memory map.
0
DISMCYINT
0
Disable interruption of multiple cycle
instructions(LDM or STM).
R/W
- This register is used for debugging.
9. Co-processor access control register
- This register is available in Cortex-M4 with floating point unit for
enabling the floating point unit.
Bits
Name
Type
Reset
value
Descriptions
23:22 CP11
R/W
0
Access for floating point unit
21:20 CP10
R/W
0
Access for floating point unit
- CP10 & CP11 must be identical.
Bits
Setting
00
Access denied.
01
Privileged access only.
10
Reserved – result unpredictable
11
Full access