Eesti Infotehnoloogia Kolledž
Digitaalloogika ja digitaalsüsteemid
KODUTÖÖ
Maarek Varres
EIK10088313
DK21
Tallinn 2009
1. Leida oma matriklinumbrile vastav 4-muutuja loogikafunktsioon
Matrikli nr: 10088313
f(x1…x4) = Σ (1, 2, 6, 7, 9, 13)1 (3, 4)_
2. Kirjutada välja oma matriklinumbrist leitud osaliselt määratud 4-muutuja
loogikafunktsiooni tõeväärtustabel.
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
X1 X2
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
X3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Y
0
1
1
0
1
1
0
1
0
0
0
1
0
0
3. Leida MDNK (minimaalne DNK) ja MKNK (minimaalne KNK)
3.1 MDNK Karnaugh kaardiga
x3x4
x1x2
00
01
11
10
00
0
0
0
0
01
1
0
0
1
11
1
1
0
0
10
1
1
1
0
y = ( x 2 x3 x 4 ) v ( x 2 x3 x 4 ) v ( x1 x3 )
3.2 MKNK Karnaugh kaardiga
x3x4
x1x2
00 01
00 0
1
01 0
11 0
0
10 0
1
11
1
0
0
10
1
1
1
0
Y = ( x3 V x 4 )( x 2 V x3 )( x1 V x 2 V x 4 )( x1 V x 2 V x3 )
4. Kirjutada oma funktsiooni 1-de piirkonnast välja täielik DNK (TDNK)
(ignoreerides määramatuspiirkonda).
x1 x 2 x3 x 4
Y =
v
x1 x 2 x3 x 4 v x1 x 2 x3 x 4
x1 x 2 x3 x 4
v
x1 x 2 x3 x 4
v
x1 x 2 x3 x 4
v
5. Lihtsustada loogikaalgebra põhiseoste abil eelnevalt leitud täielikku DNK-d
lihtsaima DNK-ni, milleks see TDNK lihtsustub.
x1 x 2 x3 x 4
Y =
v
x1 x 2 x3 x 4 v x1 x 2 x3 x 4
x1 x 2 x3 x 4
x1 x 2 x3 x 4
x1 x3 x 4
x1 x3 x 4
Y =
v x1 x 2 x3 x 4
v x1 x 2 x3 x 4
v x1 x 2 x3 x 4
v x1 x 2 x3 x 4
x1 x3 x 4
x1 x 2 x3 x 4
x1 x 2 x3 x 4
v
x1 x 2 x3 x 4
= x1 x3 x 4
= x 2 x3 x 4
= x1 x3 x 4
= x1 x3 x 4
v x1 x 2 x3
v
v x 2 x3 x 4
v x1 x 2 x3
v x 2 x3 x 4
v x 2 x3 x 4
Lihtsustatud TDNK ning MDNK ei ole võrdsed, sest MDNK leidmisel kasutati
määramatust.
v
6. Leida ja näidata, milleks (0 või 1) väärtustuvad (punktis 3) leitud MDNK ja MKNK
määramatuspiirkonna kõikide argumentvektorite korral.
Otsustada (hinnata), kas leitud MDNK ja MKNK on teineteisega võrdsed või mitte.
(3,4)_
MDNK:
0011 Y = ( x 2 x3 x 4 ) v ( x 2 x3 x 4 ) v ( x1 x3 ) = 1
0100 Y = ( x 2 x3 x 4 ) v ( x 2 x3 x 4 ) v ( x1 x3 ) = 0
MKNK:
0011 y = ( x3 V x 4 )( x 2 V x3 )( x1 V x 2 V x 4 )( x1 V x 2 V x3 ) = 1
0100 y = ( x3 V x 4 )( x 2 V x3 )( x1 V x 2 V x 4 )( x1 V x 2 V x3 ) = 0
MDNK = MKNK
7. Realiseerida (punktis 3) MDNK-na saadud loogikafunktsioon minimaalseima
keerukusega loogikaskeemina, kasutades vabaltvalitud loogikaelemente AND OR
ja NOT.
8. Realiseerida (punktis 3) MKNK-na saadud loogikafunktsioon
minimaalseima keerukusega loogikaskeemina elementidel AND OR
NOT.
9. Realiseerida (punktis 3) MDNK-na saadud loogikafunktsioon lihtsaima
loogikaskeemina kahe sisendiga loogikaelementidel (OR-NOT)
9.1 läheme Karnaugh kaardi abil MDNK pealt MKNK peale
Y = x 2 x3 x 4 v x 2 x3 x 4 v x1 x3
x3x4
x1x2
00
01
11
10
00
0
0
0
0
01
1
0
0
1
11
1
1
0
0
10
1
1
1
0
y = ( x3 V x 4 )( x 2 V x3 )( x1 V x 2 V x 4 )( x1 V x 2 V x3 )
9.2 läheme üle kujule OR-NOT ja 2 sisendilistele elementidele
________________________________________________________________________________________________________________
________________________________________________________________
________________________________________________________________
___________________________________________
_____________________________
_____________________________
__________________________________________
_________________
_________________
__________________
__________________
_________________
_________________
( x3 V x 4 )V( x 2 V x3 )V( x1 V x 2 V x 4 )V( x1 V x 2 V x3 )
10. Realiseerida (punktis 3) MKNK-na saadud loogikafunktsioon lihtsaima
loogikaskeemina kahe sisendiga loogikaelementidel (AND-NOT) .
10.1 Läheme Karnaugh kaardi abil üle MKNK pealt MDNK peale
y = ( x3 V x 4 )( x 2 V x3 )( x1 V x 2 V x 4 )( x1 V x 2 V x3 )
x3x4
x1x2
00
01
11
10
00
0
0
0
0
01
1
0
0
1
11
1
1
0
0
10
1
1
1
0
y = ( x 2 x3 x 4 ) v ( x 2 x3 x 4 ) v ( x1 x3 )
10.2 läheme üle kujule AND-NOT ja 2-sisendilistele elementidele
_________________________________________________________________
______________________________________________
______________
______________________________________________
_________________
_________________
____________
___________
____________
___________
( x 2 x3 x 4 ) ( x 2 x3 x 4 ) ( x1 x3 )
11. Modelleerida punktides 4, 7, 8, 9, 10 saadud tulemusi VHDL-is.
entity MDNK is
port ( x1, x2, x3, x4 : in bit;
y : out bit );
end MDNK;
architecture dataflow of MDNK is
signal s1, s2, s3, s4: bit;
begin
s1 <= (not x2) and x4;
s2 <= (not x3) and x4;
s3 <= (not x1) and x2;
y <= s1 or s2 or s3;
end dataflow;
entity mdnk_test is
end mdnk_test;
architecture
bench
of
mdnk_test
is
signal x1, x2, x3, x4, y: bit := '0';
component MDNK
port ( x1, x2, x3, x4: in bit;
y: out bit );
end component;
constant i1_arr:
"0000001100111";
constant i2_arr:
"0011110100001";
constant i3_arr:
"0100111001011";
constant i4_arr:
"1101011100001";
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
begin -- bench
process -- Constants not allowed?!
begin
for i in i1_arr'range loop
x1 <= i1_arr(i);
x2 <= i2_arr(i);
x3 <= i3_arr(i);
x4 <= i4_arr(i);
wait for 10 ns;
end loop;
wait for 10 ns; wait;
end process;
u1: MDNK port map (x1, x2, x3, x4, y);
end bench;
entity MKNK is
port ( x1, x2, x3, x4 : in bit;
y : out bit );
end MKNK;
architecture dataflow of MKNK is
signal s1, s2, s3, s4: bit;
begin
s1 <= (not x1) or (not x2) or (not x3);
s2 <= x2 or x4;
y <= s1 and s2;
end dataflow;
component MKNK
port ( x1, x2, x3, x4: in bit;
y: out bit );
end component;
constant i1_arr:
"0000001100111";
constant i2_arr:
"0011110100001";
constant i3_arr:
"0100111001011";
constant i4_arr:
"1101011100001";
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
begin -- bench
process -- Constants not allowed?!
begin
for i in i1_arr'range loop
x1 <= i1_arr(i);
x2 <= i2_arr(i);
x3 <= i3_arr(i);
x4 <= i4_arr(i);
wait for 10 ns;
end loop;
wait for 10 ns; wait;
end process;
u1: MKNK port map (x1, x2, x3, x4, y);
end bench;
entity TDNK is
port ( x1, x2, x3, x4 : in bit;
y : out bit );
end TDNK;
architecture dataflow of TDNK is
signal s1, s2, s3, s4, s5, s6, s7, s8: bit;
begin
s1 <= (not x1) and (not x2) and (not x3) and x4;
s2 <= (not x1) and (not x2) and x3 and x4;
s3 <= (not x1) and x2 and (not x3) and (not x4);
s4 <= (not x1) and x2 and (not x3) and x4;
s5 <= (not x1) and x2 and x3 and (not x4);
s6 <= (not x1) and x2 and x3 and x4;
s7 <= x1 and (not x2) and x3 and x4;
s8 <= x1 and x2 and (not x3) and x4;
y <= s1 or s2 or s3 or s4 or s5 or s6 or s7 or s8;
end dataflow;
entity tdnk_test is
end tdnk_test;
architecture
bench
of
tdnk_test
is
signal x1, x2, x3, x4, y: bit := '0';
component TDNK
port ( x1, x2, x3, x4: in bit;
y: out bit );
end component;
constant i1_arr:
"0000001100111";
constant i2_arr:
"0011110100001";
constant i3_arr:
"0100111001011";
constant i4_arr:
"1101011100001";
begin -process
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
bench
-- Constants not allowed?!
begin
for i in i1_arr'range loop
x1 <= i1_arr(i);
x2 <= i2_arr(i);
x3 <= i3_arr(i);
x4 <= i4_arr(i);
wait for 10 ns;
end loop;
wait for 10 ns; wait;
end process;
u1: TDNK port map (x1, x2, x3, x4, y);
end bench;
OR-NOT:
entity vidin is
port ( x1, x2, x3, x4 : in bit;
y : out bit );
end vidin;
architecture dataflow of
signal s1, s2, s3, s4,
begin
y <= (((((x1 nor (x2
(x2 nor x4)) nor x4) nor
end dataflow;
vidin is
s5, s6, s7, s8: bit;
nor x2)) nor (x3 nor x3)) nor
(x1 nor x1));
entity vidin_test is
end vidin_test;
architecture
bench
of
vidin_test
is
signal x1, x2, x3, x4, y: bit := '0';
component vidin
port ( x1, x2, x3, x4: in bit;
y: out bit );
end component;
constant i1_arr: bit_vector (0 to 12) :=
"0000001100111";
constant i2_arr: bit_vector (0 to 12) :=
"0011110100001";
constant i3_arr: bit_vector (0 to 12) :=
"0100111001011";
constant i4_arr: bit_vector (0 to 12) :=
"1101011100001";
begin -- bench
process -- Constants not allowed?!
begin
for i in i1_arr'range loop
x1 <= i1_arr(i);
x2 <= i2_arr(i);
x3 <= i3_arr(i);
x4 <= i4_arr(i);
wait for 10 ns;
end loop;
wait for 10 ns; wait;
end process;
u1: vidin port map (x1, x2, x3, x4, y);
end bench;
AND-NOT:
entity vidin is
port ( x1, x2, x3, x4 : in bit;
y : out bit );
end vidin;
architecture dataflow of
signal s1, s2, s3, s4,
begin
y <= ((((x1 nand x1)
x4)) nand (((x1 nand x1)
x4))) nand ((x4 nand (x3
end dataflow;
entity vidin_test is
end vidin_test;
vidin is
s5, s6, s7, s8: bit;
nand x2) nand ((x2 nand x2) nand
nand x2) nand ((x2 nand x2) nand
nand x3)));
architecture
bench
of
vidin_test
is
signal x1, x2, x3, x4, y: bit := '0';
component vidin
port ( x1, x2, x3, x4: in bit;
y: out bit );
end component;
constant i1_arr:
"0000001100111";
constant i2_arr:
"0011110100001";
constant i3_arr:
"0100111001011";
constant i4_arr:
"1101011100001";
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
bit_vector (0 to 12) :=
begin -- bench
process -- Constants not allowed?!
begin
for i in i1_arr'range loop
x1 <= i1_arr(i);
x2 <= i2_arr(i);
x3 <= i3_arr(i);
x4 <= i4_arr(i);
wait for 10 ns;
end loop;
wait for 10 ns; wait;
end process;
u1: vidin port map (x1, x2, x3, x4, y);
end bench;