FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 Finite State Machine (FSM)
 A Digital Circuit, in general, can be subdivided into two
parts:
Combinational part – A circuit whose output is a function of its
current inputs only
Sequential part – A circuit whose output is a function of its current
inputs plus the past inputs [requires memory elements such as latches
or flip-flops]
 FSM is a mathematical abstraction of a Sequential Circuit
A System - comprising of inputs, outputs, and states while modeling
time as discrete instants at which inputs or outputs can change
Synchronous FSM – when states and output transitions are
synchronized with a clock (positive or negative edge)
Asynchronous FSM - when states and output transitions can occur
at any time in response to input changes
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Models
Mealy Model – Contains three components:
 State Memory to store the current state S(t)
 State Transition Function  to determine the next state
S(t+1) depending upon the current state S(t) and the input X(t)
 Output Function  which generates the output Y(t) as
function of the current state S(t) and the input X(t)
Fig-01: Mealy Model of FSM
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Models – Cont’d
Moore Model – Similar to Mealy Model except that Output
Function  which generates the output Y(t) as function of the
current state S(t) only.
Fig-02: Moore Model of FSM
Both Mealy and Moore Models can be mapped into each other
Mealy Machines usually have fewer state variables (memory
elements)- Widely used in Engineering Applications
Moore Machines are simpler to analyze mathematically
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Models – Cont’d
 A Problem with Mealy Machine (as shown in Fig-01) –
Output may have glitches. So, a slightly modified version of
Mealy Machine is more commonly used.
Fig-03: Mealy FSM with Registered Output
 All Digital Systems can be viewed as networks of
FSMs ?
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Models – Cont’d
Autonomous FSM – Special FSM having no inputs, e.g. LFSR
Communicating FSMs – Two or more FSMs interacting with
each other
Fig-04: Communicating FSMs
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Introduction to ASIC Design
5
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Steps
1. Understand the Specifications
2. Problem Definition Using State Diagram and/or State Table
3. State Minimization – Removal of redundant internal states
4. State Assignment – Assigning binary codes to the states
5. Determination of State Transition Function and Output
Function Equations
6. Logic Equation Minimization
7. Design Mapping to a given Technology or Device
 Steps 3, 4 and 6 are Optimization Problems – valuable
but not necessary steps
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Introduction to ASIC Design
6
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Steps – Cont’d
 Step-1: Understanding the Specifications
A Simple Vending Machine Design Example: [a] Accepts 1 or 2
Rupees Coins [b] Delivers a Pak-Cola bottle of drink costing
Rupees 3 [c] Provides change where applicable
Rs. 1 Coin
Vend
COINS
Input Conditioning
Output
Drivers
FSM
Rs. 2 Coin
Drink / Change
Change
CLOCK
Fig-05: A Vending Machine Model
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Introduction to ASIC Design
7
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Steps –
Cont’d
Step-2: State Diagram
Representation
Each State is represented as a circle
with output arrows
Inputs: Rs. 1: Rs. 2 00/00 Outputs: Vend: Change
 Next to the arrow, input and outputs
are given
 For Vending Machine, FSM remains in
state S0 until there is some coin, either
State Name
of Rs. 1 or Rs. 2 inserted.
S0
 Upon such an event, depending upon
Idle
the coin type, it switches to another state
Description
 FSM should not activate the Vend /
Change driver unless the credit equals or
10/00
01/00
exceed the Rs. 3
 A state transition diagram can be
Fig-06: Notation used in State Diagram Representation
drawn as shown in Fig-07(Next Slide)
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Introduction to ASIC Design
8
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
FSM Design Steps – Cont’d
Step-2: State Diagram Representation – Let us Complete it
Inputs/Outputs = Rs.2:Rs.1/Vend:Change
S0
S1
S3
S7
S2
S4
S5
S6
S8
Fig-07: State Diagram Representation of Vending Machine
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Introduction to ASIC Design
9
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Steps – Cont’d
Step-3: State Minimization
Equivalent States: Two states are said to be equivalent if they
have identical next states and outputs.
00/00
00/00
Inputs/Outputs=
Rs.2:Rs.1/Vend:Change
Reset
S0
Reset
S0
00/00
00/00
00/00
00/00
01/10
01/00
S2
S2
10/10
10/11
00/00
S1
10/00
01/00
S1
S3
[a]
[b]
Fig-08: State Minimization Step-03 [a] Cyclic State Diagram of VM [b] Reduced FSM for VM
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Introduction to ASIC Design
10
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Steps – Cont’d
 Step-3: State Minimization – Cont’d
 Addition of Invalid State(s) due to State Assignment (Binary Codes)
00/00
Inputs/Outputs=
Rs.2:Rs.1/Vend:Change
S0
00/00
S3
xx/00
00/00
01/10
01/00
S2
10/10
S1
10/00
10/11
01/00
Fig-09: Final Reduced FSM for VM
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Introduction to ASIC Design
11
FSM Design and Optimization
Step-4: State Assignment and State Transition Table
Table-01: State Transition Table for Vending Machine
Current State
Inputs = Rs.2:Rs.1
Next State
Outputs= Vend:Change
S0
S0
S0
S1
S1
S1
S2
S2
S2
S3
00
01
10
00
01
10
00
01
10
XX
S0
S1
S2
S1
S2
S0
S2
S0
S0
S0
00
00
00
00
00
10
00
10
11
00
Table-02: Compact State Transition Table for VM
Current State
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Steps – Cont’d
NDG-L19-24
S0
S1
S2
S3
00
S0, 00
S1, 00
S2, 00
S0, 00
Inputs = Rs. 2: Rs. 1
01
11
S1, 00
S0, 00
S2, 00
S0, 00
S0, 10
S0, 00
S0, 00
S0, 00
Introduction to ASIC Design
10
S2, 00
S0, 10
S0, 11
S0, 00
12
FSM Design and Optimization
Step-4: State Assignment and State Transition Table
Table-02: Compact State Transition Table for VM
Current State
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Steps – Cont’d
00
S0, 00
S1, 00
S2, 00
S0, 00
S0
S1
S2
S3
Inputs = Rs. 2: Rs. 1
01
11
S1, 00
S0, 00
S2, 00
S0, 00
S0, 10
S0, 00
S0, 00
S0, 00
10
S2, 00
S0, 10
S0, 11
S0, 00
Table-03: Compact State Transition Table for
00
01
10
11
00
00, 00
01, 00
10, 00
00, 00
Inputs = Rs. 2: Rs. 1
01
11
01, 00
00, 00
10, 00
00, 00
00, 10
00, 00
00, 00
00, 00
10
10, 00
00, 10
00, 11
00, 00
Step-5: Determination of Logical Equations
s1(next) = /s1*/s0*Rs.2*/Rs.1 + /s1*s0*/Rs.2*Rs.1 + s1*/s0*/Rs.2*/Rs.1
s0(next) = /s1*/s0*/Rs.2*Rs.1 + /s1*s0*/Rs.2*/Rs.1
?
Vend = s1*/s0*Rs.2 + s1*/s0*Rs.1 + /s1*s0*Rs.2*/Rs.1
Change = s1*/s0*Rs.2*/Rs.1
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Introduction to ASIC Design
13
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Steps – Cont’d
Step-6-7: Simplification of Logic Equations and
Hardware Implementation
Use of K Maps or Other Methods
Implementation is Technology Dependent
Clock
Rs. 2
Rs. 1
Vend
Combinational Logic
Gates
Change
Fig-10: Implementation of VM FSM
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Introduction to ASIC Design
14
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Example – Huffman Codec
Used for JPEG/MPEG Compression
Relies on known probability of a set of fixed symbols
Table-04: Symbols with Their
Binary Code and Frequency
Fig-11: Huffman Tree Developed based on Symbol Frequency
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Introduction to ASIC Design
15
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Example – Huffman Codec – Cont’d
 Huffman Decoder Circuit Implementation as FSM
Fig-11: Huffman Decoder FSM State Diagram and FSM Implementation
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Optimization
Three Ways to Optimize the HW Complexity of FSM
 State Minimization
 State Assignment
 Logic Equation Minimization
State Minimization Methods
 State Merging by Observation
 State Partitioning
 Application of Implication Tables
State Merging by Observation
 Vending Machine Example
 Bit Sequence Detector
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Optimization – Cont’d
 State Merging by Observation
 Bit Sequence Detector – A Circuit that generates an output
Z = 1 when it detects a bit sequence from a serial data input D
as 001, 010, 100, or 111.
Fig-12: Bit Sequence Detector [a] State Diagram [b] State Table
S3 and S6 are Equivalent, and so are S4 and S5.
Eliminate S5 and S6
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Optimization – Cont’d
 State Merging by Observation – Cont’d
 Bit Sequence Detector after State Minimization
Fig-13: Minimal State Bit Sequence Detector [a] Stat Table [b] State Diagram
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Optimization – Cont’d
State Partitioning
 An FSM Example
Fig- 14: State Table for FSM of State
Partitioning Example
Best Solution for this FSM takes only 5 States ?
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Introduction to ASIC Design
20
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Optimization – Cont’d
State Partitioning – Cont’d
 An FSM Example
Step-1: State Partitioning by Outputs – Divide the states into
sets with identical outputs
Step-2: State Partitioning with Next States – For states in
each set, find their next states separately
B set is unacceptable as its
NDG-L19-24
Next State sets, for both input
0 and 1, do not belong to any
other single set of states
Introduction to ASIC Design
21
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Optimization – Cont’d
State Partitioning – Cont’d
 An FSM Example
Step-3: Repartitioning based on Next States – After Step-2, two
things have happened: next state group for C (input = 0) now belongs to
B2, however, next state group for A (input = 1) now belongs to no single
state group, so, A partition has become invalid
NOW all the next state groupings belong
to some single state partition/group.
WHAT is Final Partitioning ?
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Optimization – Cont’d
State Partitioning – Cont’d
 An FSM Example
Finally We got a State Partitioning Where
Next outputs are the same for each state in the same state
partition/group
AND
Next states are the same for each state in the same
set/group
Final Optimized FSM has got only
Five States……………….!
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Introduction to ASIC Design
23
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Optimization – Cont’d
Self-study Exercise: Application of
Implication Table: Easy to Computerize
and Suitable for Larger FSM
Optimization
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Introduction to ASIC Design
24
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Optimization – Cont’d
 State Assignment
Assigning Unique Binary Codes to the States of a Minimized
FSM
 State Minimization has a Unique Technology-Independent
Solution, however, State Assignment Depends on
 Technology such as PLA, ROM, PAL, logic gates
 Type of storage circuit, D-latches or FF
 For a FSM of r Rows (States), with n-bit State Variables, All
Possible Permutations are
N = 2n ! / (2n-r)!
 Many, among above Assignments, are just Rearrangements,
according to McCluskey, Number of Distinct Assignments is
Reduced to
ND = (2n -1)! / (2n-r)!* n!
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Optimization – Cont’d
 State Assignment – Cont’d
 Even the number given by McCluskey is still very large
 Very Complex Problem, called Intractable or np-Complete.
Such a problem usually have no optimal solution but some
solution based on heuristics (thumb rules or simple rules)
 Aim here would be to have Rules that provide maximum
number of 1’s in adjacent cells of next-state truth table for
better k-map reduction
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Introduction to ASIC Design
26
FSM Design and Optimization
 FSM Optimization – Cont’d
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 State Assignment – Cont’d
 Rule-1: States with the same next state for a given input
condition should be assigned codes differing in one (binary) bit
position only. For Example,
 Rule-2: Next States of a single state should be given logically
adjacent state assignments. For Example,
NDG-L19-24
Introduction to ASIC Design
27
FSM Design and Optimization
 FSM Optimization – Cont’d
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 State Assignment – Cont’d
Example-01: Consider the Bit Sequence Detector FSM
Fig-15: Bit Sequence Detector FSM
 Applying Rule 2, S1 and S2 should be assigned logically
adjacent codes, so, let S1 = 100 and S2 = 101
 Applying Rule 1, S3 and S4 both have the same next state with
given input condition, so, S3 and S4 are assigned logically
adjacent codes. S3 = 110 and S4 = 111
 S0 can be assigned 000 (arbitrary), and unassigned states would
be 010, 011, and 001
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Introduction to ASIC Design
28
FSM Design and Optimization
 FSM Optimization – Cont’d
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 State Assignment – Cont’d
 One-Hot State Assignment
 Sometimes, instead of log2 r bi-stable latches, it is more
efficient (and convenient as well ) to have r latches/flip-flops,
i.e. one for each state. It is called One-Hot State Assignment.
 At any time, only one FF will be set (FF corresponding to
the state where FSM lies at that instant)
 No State Assignment is required
 One-hot state assignment is particularly suitable for FPGA
(LUT and MUX based Architecture) implementation of FSM
 Number of FF required is much higher than Min. Length
State Encoding
 Slower in Operation as compared to other option.
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Introduction to ASIC Design
29
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Implementation- HW Considerations
Fig-16:
Generic Block
Diagram of
FSM
 Implementation Alternatives
 Standard ICs – Suitable for Simple Designs
 PROM – Suitable for many Outputs/States, No Logic Minimization needed,
Exhaustive Implementation for all Possible Input Combinations, Size grows
Exponentially
Fig-17:
Implementation of
FSM with PROM
 CPLDs/FPGAs – More Suitable for most of FSM Implementations
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Introduction to ASIC Design
30
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Implementation- HW Considerations – Cont’d
Fig-18:
Asynchronous
Inputs to FSM
 Asynchronous Inputs – A Possible Source of Race Condition
 Asynchronous input “A” to FSM, while making transition from “0” to
“1”, as shown above may give rise to a wrong state transition
 SOLUTION: Synchronize all the Asynchronous Inputs to FSM using a
Latch clocked by the FSM clock
Fig-19:
Synchronizing
Asynchronous
Inputs
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Implementation- HW Considerations – Cont’d
 Types of Flip-Flops at Output
 Outputs of Programmable Macro-Cells or LEs of CPLDs/FPGAs
are Configurable
 Inverting/Non-Inverting
 Register or Combinational
 D Flip-Flop, S-R FF, J-K FF, or T-FF, any type is Possible
 T-FF or J-K FF can Produce more Efficient Implementation
(fewer product terms in Boolean Equations)
 Better CAD tools make better choice automatically
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 Algorithmic State Machine (ASM) Chart
 An Alternative Method to Represent FSM based on FlowChart Notation – Popularized by Christopher Clare “ Designing
Logic Systems Using State Machines”
Key Features of ASM:
[a]
 FSM is in one State Block per state
time (Clock Cycle)
 Single Entry Point for each State
Block
 For each combination of inputs,
only one unambiguous exit path
 Outputs asserted high, low, highimpedance until the next clock cycle
NDG-L19-24
[b]
Fig-20: ASM Chart [a] ASM Elements [b]
An ASM Block
Introduction to ASIC Design
33
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 Algorithmic State Machine (ASM) Chart – Cont’d
 ASM Construction Rules
Must Follow these Rules:
 Each State can have one and only
one State Box
 Outputs depending on the Current
State only (Moore Model) are
represented by Square Box
 Outputs depending on the Inputs
(and of course the Current State), as
in Mealy Model, are represented by
Rounded Box
 Decision Box contains the
Conditions for the Input Variables
NDG-L19-24
Fig-21: ASM Multi-Way Decision Block
Simplification
Introduction to ASIC Design
34
FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 Algorithmic State Machine (ASM) Chart – Cont’d
 ASM Advantages over (Bubble) State Diagram
 ASM Chart reflects HW Algorithm
better than (Bubble) State Diagram
Representation of FSM
 Easier to Follow and Understand
 ASM Chart avoids Transition
Conflicts that could Occur in State
Diagram Representation of FSM
EXAMPLE: Inputs I3I2I1I0 = 1101, 1011,
and 1111 all will make both transitions
to be True.
Fig-22: Possible Conflicts in State
Diagram Representation of an FSM
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 Algorithmic State Machine (ASM) Chart – Cont’d
 ASM Representation of Vending Machine
Rs.0
00/00
S0
00/00
00/00
01/10
01/00
Rs.1
Rs.1
Rs.2
Rs.1
10/00
S2
10/10
S1
Rs.2
Inputs/Outputs=
Rs.2:Rs.1/Vend:Change
S3
xx/00
Rs.2
10/11
01/00
[a]
Rs.1
Rs.2
[b]
Fig-23: Mealy Model of Vending Machine [a] State Diagram [b] ASM Chart
NDG-L19-24
Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Using Verilog HDL
 Mealy FSM and Its RTL Coding
Fig-24: Mealy FSM to
be Coded in Verilog
HDL
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Using Verilog HDL – Cont’d
 Mealy FSM and Its RTL Coding – Cont’d
…Cont’d on Next Slide
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FSM Design and Optimization
 Mealy FSM and Its RTL Coding – Cont’d
…Cont’d from Prev. Slide
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Using Verilog HDL – Cont’d
…Cont’d on Next Slide
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Introduction to ASIC Design
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FSM Design and Optimization
 Mealy FSM and Its RTL Coding – Cont’d
…Cont’d from Prev. Slide
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Using Verilog HDL – Cont’d
…Cont’d on Next Slide
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Introduction to ASIC Design
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FSM Design and Optimization
 Mealy FSM and Its RTL Coding – Cont’d
…Cont’d from Prev. Slide
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Using Verilog HDL – Cont’d
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Introduction to ASIC Design
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FSM Design and Optimization
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Using Verilog HDL – Cont’d
 Moore FSM and Its RTL Coding
…Cont’d on Next Slide
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FSM Design and Optimization
 Moore FSM and Its RTL Coding
…Cont’d from Prev. Slide
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Using Verilog HDL – Cont’d
…Cont’d on Next Slide
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FSM Design and Optimization
 Moore FSM and Its RTL Coding
…Cont’d from Prev. Slide
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Using Verilog HDL – Cont’d
…Cont’d on Next Slide
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Introduction to ASIC Design
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FSM Design and Optimization
 Moore FSM and Its RTL Coding
…Cont’d from Prev. Slide
* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06
 FSM Design Using Verilog HDL – Cont’d
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Introduction to ASIC Design
45