Chapter 10
Computer Design Basics
10-1 Introduction
 The specification for a computer consists of a description
of its appearance to a programmer at the lowest level, its
instruction set architecture (ISA).
 From the ISA, a high-level description of the hardware to
implement the computer, called the computer architecture,
is formulated.
 This architecture, for a simple computer, is typically
divided into a datapath and a control.
The datapath is defined by three basic components:
1. a set of register.
2. the micro-operations that are performed on data
stored in the registers, and
3. the control interface.
 The control unit provides signals that control the microoperations performed in the datapath and in other
components of the system, such as memories.
 In addition, the control unit controls its own operation,
determining the sequence of events that occur.
 This sequence may depend upon the results of current
and past micro-operations executed.
 In a more complex computer, typically multiple control
units and datapaths are present.
10-2 Datapaths
 Instead of having each individual register perform its
micro-operations directly, computer systems often employ
a number of storage registers in conjunction with a shared
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operation unit called an arithmetic/logic unit,
abbreviated ALU.
 To perform a micro-operation, the contents of a specified
source registers are applied to the inputs of the shared
ALU.
 The ALU performs an operation, and the result of this
circuit, the entire register transfer operation from the
source registers, through the ALU, and into the
destination register is performed during one clock cycle.
 The shift operations are often performed in a separate
unit, but sometimes these operations are also
implemented within the ALU.
 The datapath and the control unit are the two parts of
the processor, or CPU, of a computer.
 In addition to the registers, the datapath contains the
digital logic that implements the various micro-operations.
 This digital logic consists of buses, multiplexers,
decoders, and processing circuits.
 When a large number of registers is included in a
datapath, the registers are most conveniently connected
through one or more buses.
 Registers in a datapath interact by the direct transfer of
data, as well as in the performance of the various types of
micro-operations.
 A simple bus-based datapath with four registers, an ALU,
and a shifter is shown in Figure 10-1.
 It is useful to have certain information, based on the
results of an ALU operation, available for use by the
control unit of the CPU to make decisions.
 Four status bits are shown with the ALU in Figure 10-1.
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 The control unit for the datapath directs the information
flow through the buses, the ALU, the shifter, and the
registers by applying signals to the select inputs.
 For example, to perform the micro-operation
R1  R2 + R3
Figure 10-1
Block Diagram of a Generic Datapath
 The control unit must provide binary selection values to
the following sets of control inputs:
1. A select, to place the contents of R2 onto A data and,
hence, Bus A.
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2. B select, to place the contents of R3 onto the 0 input of
MUX B; and MB select, to put the 0 input of MUX B
onto Bus B.
3. G select, to provide the arithmetic operation A + B.
4. MF select, to place the ALU output on the MUX F
output.
5. MD select, to place the MUX F output onto Bus D.
6. Destination select, to select R1 as the destination of the
data on Bus D.
7. Load enable, to enable a register --- in this case, R1 --to be loaded.
10-3 The Arithmetic/Logic Unit
Figure 10-2
Symbol for an n-Bit ALU
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 The ALU is a combinational circuit that performs a set of
basic arithmetic and logic micro-operations.
 The ALU has a number of selection lines used to
determine the operation to be performed.
 The selection lines are decoded within the ALU, so that k
selection lines can specify up to 2k distinct operations.
 Figure 10-2 shows the symbol for a typical n-bit ALU.
 The n data inputs from A are combined with the n data
inputs from B to generate the result of an operation at the
G outputs.
 The mode-select input S2 distinguishes between
arithmetic and logic operations.
 The two Operation select inputs S1 and S0 and the Carry
input Cin specify the eight a arithmetic operations with S2
at 0.
 Operand select input S0 and Cin specify the four logic
operations with S2 at 1.
 We perform the design of this ALU in three stages.
 First, we design the arithmetic section.
 Then we design the logic section, and finally, we combine
the two sections to form the ALU.
Arithmetic Circuit
 The basic component of an arithmetic circuit is a
parallel adder, which is constructed with a number of fulladder circuits connected in cascade, as shown in
Figure 5-5.
 By controlling the data inputs to the parallel adder, it is
possible to obtain different types of arithmetic operations.
 The block diagram in Figure 10-3 demonstrates a
configuration in which one set of inputs to the parallel
adder is controlled by the select lines S1 and S0.
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 There are n bits in the arithmetic circuit, with two inputs A
and B and output G.
Figure 10-3
B Input Logic for One Stage of Arithmetic Circuit
 Table 10-1 shows the arithmetic operations that are
obtainable by controlling the value of Y with the two
selection inputs S1 and S0.
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 The B input logic in Figure 10-3 can be implemented with
n multiplexers.
Figure 10-4
B Input Logic for One Stage of Arithmetic Circuit
 The number of gates in the B input logic can be reduced
if, instead of using 4-to-1 multiplexers, we go through the
logic design of one stage (one bit) of the B input logic.
 This can be done as shown in Figure 10-4.
 The truth table for one typical stage I of the logic is given
in Figure 10-4(a).
 The inputs are S1, S0 and Bi, and the output is Yi.
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Figure 10-5
Logic Diagram of a 4-bit Arithmetic Circuit
Figure 10-6
One Stage of Logic Circuit
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Logic Circuit
 The logic micro-operations manipulate the bits of the
operands by treating each bit in a register as a binary
variable, giving bitwise operations.
 There are four commonly used logic operations ----- AND,
OR, XOR (exclusive-OR), and NOT ----- from which
others can be conveniently derived.
 Figure 10-6(a) shows one stage of the logic circuit.
 It consists of four gates and a 4-to-1 multiplexer, although
simplification could yield less complex logic.
 Each of four logic operations generated through a gate
that performs the required logic.
Arithmetic / Logic Unit
 The logic circuit can be combined with the arithmetic
circuit to produce an ALU.
 Selection variables S1 and S0 can be common to both
circuits, provided that we use a third selection variable to
differentiate between the two.
 The configuration for one stage of the ALU is illustrated in
Figure 10-7.
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Figure 10-7
One Stage of ALU
 The ALU specified of Figure 10-7 provides eight
arithmetic and four logic operations.
 Each operation is selected through the variables S2, S1,
S0, and Cin.
 Table 10-2 lists the 12 ALU operations.
 The ALU logic we have designed is not as simple as it
could be and has a fairly high number of logic levels,
contributing to propagation delay in the circuit.
 With the use of logic simplification software, we can
simplify this logic and reduce the delay.
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10-4 The Shifter
 The shifter shifts the value on Bus B, placing the result
on an input of MUX F.
 The basic shifter performs one of two main types of
transformations on the data: right shift and left shift.
 A combinational shifter can be constructed with
multiplexers as shown in Figure 10-8.
 The selection variable S is applied to all four multiplexers
to select the type of operation within the shifter.
 S = 00 causes a right-shift operation and S = 10 causes a
left-shift operation.
 The right shift fills the position on the left with the value on
serial input IR.
 The left shift fills the position on the right with values on
serial input IL.
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 Serial outputs are available from serial output R and serial
output L for right and left shifts, respectively.
 The diagram of Figure 10-8 shows only four stages of the
shifter, which has n stages in a system with n-bit
operands.
Figure 10-8
4-Bit Basic Shifter
Barrel Shifter
 In datapath applications, often the data must be shifted
more than one bit position in a single clock cycle.
 A barrel shifter is one form of combinational circuit that
shifts or rotates the input data bits by the number of bits
positions specified by a binary value on a set of selection
lines.
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Figure 10-9
4-Bit Barrel Shifter
 A barrel shifter with 2n input and output lines required 2n
multiplexers, each having 2n data inputs and n selection
inputs.
 The number of positions for the data to be rotated is
specified by the selection variables and can be from 0 to
2n – 1 positions.
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10-5 Datapath Representation
 The datapath in Figure 10-1 includes the registers,
selection logic for the registers, the ALU, the shifter, and
three additional multiplexers.
 With a hierarchical structure, we can reduce the apparent
complexity of the datapath.
 This reduction is important, since we frequently use this
datapath.
 The use of a hierarchy allows one implementation of a
module to be replaced with another, so that we are not
tied to specific logic implementations.
 A typical datapath has more than four registers.
 Computers with 32 or more registers are common.
 The construction of a bus system with a large number of
registers requires different techniques.
 A set of registers having common micro-operations
performed on them may be organized into a register file.
 The typical register file is a special type of fast memory
that permits one or more words to be read and one or
more words to be written, all simultaneously.
 Functionally, a simple register file contains the equivalent
of the logic shaded in blue in Figure 10-1.
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Figure 10-10
Block Diagram of Datapath Using the Register File and
Function Unit
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10-6 The Control Word
 The selection variables for the datapath control the microoperations executed within the datapath for any given
clock pulse.
 The selection variables control the addresses for the data
read from the register file, the function performed by the
function unit, and the data loaded into the register file, as
well as the selection of external data.
 A block diagram of a datapath that is a specific version of
the datapath in Figure 10-10 is shown in
Figure 10-11(a).
 It has a register file with eight registers, R0 through R7.
 The register file provides the inputs to the function unit
through Bus A and Bus B.
 MUX B selects between constant values on Constant in
and register values on B data.
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 The ALU and zero-detection logic within the function unit
generate the binary data for the four status bits: V
(overflow), C (carry), N (sign), and Z (zero), MUX D
selects the function unit output or the data on Data in as
input for the register file.
 There are 16 binary control units.
 Their combined values specify a control word.
 The 16-bit control word is defined in Figure 10-11(b).
Figure 10-11
Datapath with Control Variables
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Figure 10-12
Simulation of the Micro-operation Sequence in Table 10-7
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