Graduate Computer Architecture I
Lecture 15: Intro to
Reconfigurable Devices
Quick Review Digital Logic
A(Q),B
AND
OR
NAND
NOR
XOR
NOT
0,0
0
0
1
1
0
1
0,1
0
1
1
0
1
1
1,0
0
1
1
0
0
0
1,1
1
1
0
0
1
0
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Typical Circuit (Full-Adder)
Input
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Output
C’
A
B
S
C
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
0
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
NAND
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Full-Adder Using NAND
A B C’
Input
S
C
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Output
C’
A
B
S
C
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
0
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
VLSI Layout of NAND Full-Adder
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Full-Adder Using Array of Logics
Input
C’
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S
Output
C’
A
B
S
C
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
0
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
Programmable Logic (PLA/PAL/PLD)
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More Complex Programmable Logic
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Programmable Logic
Inexpensive One-time
Programmable Devices
BURN it once and use!
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Complex Programmable
Logic Devices
Full Adder Using Memory
Input
3bit Address
Concat(C’,A,B)
Addr
8 by 2-bit
Memory
Data
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2bit Data
Concat(S,C)
Output
C’
A
B
S
C
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
0
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
Simple Wire Switch (4x4 Crossbar)
Input Ports
Output Ports
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Field Programmable Gate Array
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Logic Block (Xilinx Virtex 4000)
SRAM based Logic
(4 input Look-up-table)
Registers
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FPGA Architecture
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Design Flow
DESIGN ENTRY
RTL HDL EDITING
CORE GENERATION
RTL HDL-CORE
SIMULATION
SYNTHESIS
IMPLEMENTATION
TIMING
SIMULATION
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FPGA PROGRAMMING
& IN-CIRCUIT TEST
HDL Design Flow
DESIGN WIZARD
Accessed within
HDL Editor
HDL Module
Frameworks
LANGUAGE ASSISTANT
Language Construct
Templates
HDL EDITOR
RTL HDL Files
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IP Core Generation
Select core and
specify input
parameters
CORE GENERATOR
EDIF netlist for
core_name
HDL instantiation
module for
core_name
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Other core_name files
Functional Simulation
HDL instantiation
module for
core_names
Set Up and Map
work Library
RTL HDL Files
Testbench HDL
Files
Compile HDL Files
EDIF netlists for
core_names
Test Inputs or
Force Files
MODELSIM
Functional Simulate
Waveforms
or List Files
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Synthesis
All HDL Files
Edit FPGA Express
Synthesis Constraints
Synthesis/Implementation Constraints
Select Top Level
EDIF netlists for
core_names
Select Target Device
FPGA
EXPRESS
Synthesize
Gate/Primitive Netlist
Files (EDIF or XNF)
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Synthesis Report
Files
Implementation
Gate/Primitive Netlist
Files (XNF or EDN)
Netlist
Translation
Map
Model Extraction
XILINX DESIGN
MANAGER
Place &
Route
Timing Model Gen
HDL or EDIF for
Implemented Design
Create
Bitstream
BIT File
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Standard Delay
Format File
Timing Simulation
HDL or EDIF for
Implemented Design
Standard Delay Format File
Set Up and Map
work Directory
Testbench HDL Files
Test Inputs,
Force Files
Compile HDL Files
Compiled HDL
HDL Simulate
Waveforms
or List Files
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MODELSIM
Programming FPGA
Bit File
Input Byte
GXSLOAD
GXSPORT
FPGA
Outputs
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Other Inputs
Emergence of FPGA
• Great for Prototyping and Testing
– Enable logic verification without high cost of fab
– Reprogrammable  Research and Education
– Meets most computational requirements
– Options for transferring design to ASIC
• Technology Advances
– Huge FPGAs are available
• Up to 200,000 Logic Units
– Above clocking rate of 500 MHz
• Competitive Pricing
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System on Chip (SoC)
• Large Embedded Memories
– Up 10 Megabits of on-chip memories (Virtex 4)
– High bandwidth and reconfigurable
• Processor IP Cores
– Tons of Soft Processor Cores (some open source)
– Embedded Processor Cores
• PowerPC, Nios RISC, and etc. – 450+ MHz
– Simple Digital Signal Processing Cores
• Up to 512 DSPs on Virtex 4
• Interconnects
– High speed network I/O (10Gbps)
– Built-in Ethernet MACs (Soft/Hard Core)
• Security
– Embedded 256-bit AES Encryption
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Computational Density
Higher number means greater efficiency
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Potential Advantages of FPGAs
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Summary
• Rapidly changing platform
– Ten thousand times in silicon chip capacity
– Cost did not increase that much
• Same designs
– Von Neuman architecture time-multiplexes
– Old processor designs, only smaller
– Not much innovations
• Programmable SW/HW Platforms
– General Computing Systems do not have to look
like traditional processors
– Future?
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