The 24th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference – ASMC 2013
May 13-16, 2013 – Saratoga Hilton, Saratoga Springs, NY
8May 2013
Monday, May 13, 2013
6:30-7:30
Welcome Reception (sponsored by Applied Materials) and registration (Hilton Gallery)
Tuesday, May 14, 2013
7:30-8:30
Registration (Lobby - Saratoga City Center)
8:30
Welcome to the Conference (Russell Dover, Brion and Stefan Radloff, Intel) and 2012 Best Paper Awards
(Room M1)
8:45
Keynote: Assessing theThreats to Semiconductor Growth: Technology Limitations versus Economic Realities
Subramani Kengeri, Vice President, Advanced Technology Architecture, Office of the CTO, GLOBALFOUNDRIES (sponsored by CNW)
Session 1 Advanced Patterning/ Design for Manufacturing (Room M2B)
Chairs: Yayi Wei, GLOBALFOUNDRIES; Jacek Tyminski, Nikon Research
Advanced patterning and design for manufacturing (DFM) are key elements of leading edge
semiconductor fabrication. This session covers a broad spectrum of innovations in these
areas, including source and mask optimization, carbon nanotubes and improved double
patterning.
Session 2 Factory Optimization I (Room M2A)
Chairs: Scott Lantz, Intel Corporation; Jan Rothe, GLOBALFOUNDRIES
Semiconductor equipment and manufacturing is increasingly complex and driven by strict
economic constraints. It is vital for IC production to improve efficiency and control costs.
This session discusses new approaches to factory optimization based on data analysis and
simulation.
9:50
1.1 Cost Effective Application of Advanced Computational Lithography Techniques Using
Flexible Mask Optimization
Gek Soon Chua, Yi Zou, Wei-Long Wang, GLOBALFOUNDRIES; Jianhong Qiu, Taksh
Pandey. Stanislas Baron, Sanjay Kapasi, Russell Dover, Xiaolong Zhang, Bo Yan, ASML
Brion
9:50
2.1 Designing Product Workflow for Logistics – a Hidden Potential for Cycle Time and
Cost Reduction as well as Quality Improvement in High-Tech-Factories
Sophia Keil, Rainer Lasch, Dresden University of Technology; Dietrich Eberts, Infineon
Technologies Dresden
10:20
1.2 Fast and Accurate Design Based Binning Based on Hierarchical Clustering with Invariant
Feature Vectors for BEOL
Katsuyoshi Miura, Yuki Soga, Koji Nakamae, Osaka University; Kenichi Kadota, Toshiyuki
Aritake, Yuichiro Yamazaki,Toshiba Corporation
10:45 Break (sponsored by ASML)
11:00
1.3 Characterization methodology to support process development of advanced patterning
structures
Shailendra Mishra, Alok Vaid, Lin Zhou, Han Taejoon, Hyunchul Jung, Liping Cui, Luo Meng,
Shi Yong Jun, Thaung-Htun Oo, Wen Pin Peng, Yue Hu Jesper, GLOBALFOUNDRIES;
Cornel Bozdog, Paul Isbester, Oded Cohen
Nova Measuring Instruments, Inc.
11:25 (STUDENT)
1.4 Feasible Industrial Fabrication of Thin Film Transistor based on Randomized Network of
Single Walled Carbon Nanotube
Sayed Alireza Mousavi, Patrizia Lamberti, Vincenzo Tucci, University of Salerno; Veit
Wagner, Jacobs University Bremen
11:50
1.5 Investigation of Shape Etching on Multi-layer SiO2/Poly-Si for 3D NAND Architecture
Zusing Yang, Fang-Hao Hsu, Lo Yueh Lin, Hong-Ji Lee, Nan-Tzu Lian,
Tahone Yang, Kuang-Chao Chen and Chih-Yuan Lu Macronix International Co.
10:20
2.2 An Effective Problem Decomposition Method for Scheduling of Diffusion Processes
Based on Mixed Integer Linear Programming
Chihyun Jung, Detlef Pabst, Myoungsoo Ham, Marcel Stehli, Marcel Rothe,
GLOBALFOUNDRIES Inc.
10:45 Break (sponsored by ASML)
11:00
2.3 Optimizing Multi-Station Scheduling in Consideration of Equipment
Flexibility and Loading Balance in Semiconductor Wafer Fabrication
Ya-Tang Chuang, Yi-Hung Chang, Jr-Fong Dang, Ren-Chyi You, Steven M. Chang,
Taiwan Semiconductor Manufacturing Company
11:25
2.4 Lean Manufacturing Improvements - Supercharging Direct Observation with
Ethnography
Matthias H. Giessler, Geraldine Fagan, Dan Jaggers, Intel Corporation
11:50
2.5 Demand Smoothing
Allison Rose Bannister, Jeanne P. Bickford, Karl Swanke, IBM
12:15 Networking Lunch
12:15 Networking Lunch (Room M1)
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Session 3 - 3D/TSV Technology (Room M2B)
Chairs: Hamid Khorram, Nikon; James Lu, RPI; Thuy Tran-Quinn, IBM
This session will cover key innovation in the field of 3D/Through-silicon via technology
(TSV) including TSV processing, interposer, thin-wafer handling, reliability and power
delivery.
1:15 (STUDENT)
3.1 Novel Photodefined Polymer-Clad Through-Silicon Via Technology
Integrated With End Point Detection Using Optical Emission Spectroscopy
Paragkumar A. Thadesar, Ashish Dembla, Gary S. May, Muhannad S. Bakir, Georgia
Institute of Technology; Ja Myung Gu, Sang Jeen Hong, Myongji University
1:40
3.2 Challenges in Thin Wafer Handling and Processing
Stephen Olson, Klaus Hummler, Brian Sapp, SEMATECH
2:05
3.3 Mechanical Characteristics of Thin Dies/Wafers in Three Dimensional Large-Scale
Integrated Systems
Mariappan Murugesan, T. Fukushima, J.C. Bea, K.W. Lee, H. T. Tanaka, M. Koyanagi,
Tohoku University
2:30 BREAK (sponsored by ASML)
2:55 (STUDENT)
3.4 TSV Density Impact on 3D Power Delivery with High Aspect Ratio TSVs
Huanyu He, James J-Q. Lu, Rensselaer Polytechnic Institute; Zheng Xu, Xiaoxiong Gu,
IBM
3:15
3.5 Metrology and Inspection Challenges for Manufacturing 3D stacked IC’s
Sandip Halder, Karen Stiers, Andy Miller, Ingrid de Wolf, Mireille Maenhoudt,
Eric Beyne; IMEC, Stefano Guerrieri, Micron Technology
3:45-5:00
Session 4 – Factory Optimization II (Room M2A)
Chairs: Dave Gross, GLOBALFOUNDRIES; Holly Magoon, Nikon; Patrick Varekamp;
IBM
Semiconductor equipment and manufacturing is increasingly complex and
driven by strict economic constraints. It is vital for IC production to improve
efficiency, control costs, and be good environmental stewards. This session
covers novel solutions for factory and equipment productivity as well as
environmental efficiency.
1:15 (STUDENT)
4.1 Organizational Learning and Capital Productivity in Semiconductor Manufacturing
Charles M. Weber, Jiting Yang, Portland State University
1:40
4.2 Eradicating Human Errors during Preventive Maintenance: Understanding the
psychological reasons we make errors and implementing proactive practices to manage
and reduce human errors
Peter Gaboury, Angeline Ottolini, Bruno Spanu, Gerard Chaix, Laurence Philippon
STMicroelectronics
2:05
4.3 Automation: Key to Cycle Time Improvement in Semiconductor Manufacturing
Amit Sonar, Satyajit Shinde, Susanto Teh, GLOBALFOUNDRIES
2:30 BREAK (sponsored by ASML)
2:55
4.4 Automated Metrology Recipe Creation
Andrew Haskins, Andre Holfeld, GLOBALFOUNDRIES
3:15
4.5 Deploying an Equipment Health Monitoring Dashboard and Assessing Predictive
Maintenance
James Moyne, Jimmy Iskandar, Parris Hawkins, Applied Materials; Toysha Walker,
Micron; David Stark, ISMI; Avi Furest and Bryan Pollard, Intel Corporation
Keynote Tutorial: Computational Lithography: Vivek Singh, Fellow, Technology and Manufacturing Group Director, Intel Corporation (Room M2B)
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5:15-6:45 Session 5 – Interactive Poster Session (sponsored by KLA-Tencor; NY Loves Nanotech, Marcy NanoCenter) (Saratoga Ballroom, Hilton Hotel)
Chairs: Thanas Budri; Texas Instruments; Eric Eisenbraun, CNSE ; Dan Maynard, IBM; Mike McIntyre; Patrick Varekamp; IBM; Paul Werbaneth
This session presents analysis of the effects of enabling technologies, and innovative integrated circuit designs.
1.
The Analysis of Process Queue Time in a Foundry Environment
Michael Alan Retersdorf, Ulf Lederer, GLOBALFOUNDRIES
2.
A Bottom-Up Search Technique of Manufacturing Indicators
Jacques Pinaton, STMicroelectronics; Sara Bouzid, Corine Cauvet, Claudia
Frydman, LSIS laboratory
3.
Cu/Ni Interface Study for Bump Reliability Improvement
Rung-De Wang, Taiwan Semiconductor Manufacturing Company, Ltd.
4.
Design-enabled Manufacturing Enablement using Manufacturing Design
Request Tracker (MDRT)
Akif Sultan, Rao Desineni, Jens Hassmann, Kristina Hoeppner, Eswar
Ramanathan, Carl Babcock, Kok Peng Chua, Edward Teoh, Vito Dai, Sky Yeo,
Colin Hui, Luigi Capodieci, Sarah McGowan, Robert Madge
GLOBALFOUNDRIES
5.
6.
Die Level Defects Detection in Semiconductor Units
Asaad Said, Nital Patel, Intel Corporation
Efficiency In Sealing: A BKM Case Study
Dalia Vernikovsky, Applied Seals North America; Brad Ecker, Seth Urbach,
Microchip Technology
11. Maintaining Abatement Efficiency while Increasing Utility Efficiency Using the
Applied iSYSTM Controller
Monique McIntosh, Applied Materials
12. New Vaporization Sources for H202 for Pre-treatment/Cleaning of ALD
Deposition Surfaces
Dan Alvarez, Jr. Jeff Spiegelman, Andrew Kummel, Tobin Kaufman-Osborn,
Kiarash Kiantaj, Russell J. Holmes, Ed Heinlein, Lita Shon-Roy, Bhuvnesh
Arya, RASIRC
13. The N2 diluted application in PECVD NF3 in-situ chamber cleaning for PFC
reduction
Ming-Huei Chen, C.T. Ni, C.H. Su, Y.L. Chen, TSMC
14. Overlay Mark Contrast Enhancement for Double Patterning
Sohan Singh Mehta, Herrick Matthew, Tsai Huai-Hsuan, Lokesh Subramany,
Michael Anderson, Jeon Bumhwan, Yayi Wei, GLOBALFOUNDRIES
15. Purging of Front Opening Unified Pod for 450 mm Wafer Manufacturing
Chun-Yong Khoo, Shih-Cheng Hu, Tze-Yu Huang, Cheng-Wei Yang, National
Taipei University of Technology
7.
Equipment Automation Framework with embedded Interface-A
Bert Müller Jochen Kinauer, AIS Automation Dresden GmbH
16. Qualification Management and Its Impact on Capacity Optimization
(STUDENT)
Mehdi Rowshannahad, Stéphane Dauzère-Pérès, Ecole des Mines de SaintEtienne; Bernard Cassini, Soitec
8.
Glass Substrates for Carrier and Interposer Applications and Associated
Metrology Solutions
Aric B. Shorey, John T. Keech, Corning Incorporated (Presented by Linh Au
and Joe Canale)
17. Practical aspects of Virtual Metrology and Predictive Maintenance model
development and optimization
U. Schöpka, Lothar Pfitzner, G. Roeder, A. Mattes, M. Schellenberger, M.
Pfeffer, P. Scheibelhofer, ams AG/Graz University of Technology
9.
Improvement of Lithography Process by Using SMO for 14nm FINFET
Application
Jung Yu Hsieh, Yayi Wei, GLOBALFOUNDRIES
18. A Process to Reduce the Occurence of Metal Extrusions in Al Interconnects
Shawn Adderly, IBM Microelectronics
10. A Lean Approach to Human Performance
Michael E. Lombardi, Intel Corporation (presented by Matthias Geissler)
19. Rough Film Wafer Sensitivity Improvement using Light Scattering Inspection
System
Chuanyong Huang, Raymond Chu, Gordana Nešković, KLA-Tencor
20. Simulations of “Atomistic” Effects in Nanoscale Dopant Profiling
Petru Andrei, Mohit Mehta, Florida State University; Mark Hagmann, Newpath
Research
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The 24th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference ASMC 2013
Wednesday, May 15, 2013 (Day Two)
7:30-8:00 Registration
8:00 Keynote:
Fab Materials Next Generation Challenges: Affordability & Quality
Tim Hendry, Vice President, Technology and Manufacturing Group, Director of Fab Materials, Intel Corporation (sponsored by CNW) (Room M1)
Session 6 Yield Enhancement I (sponsored by FEI Company) (Room M2B)
Chairs: Oliver Patterson, IBM; Gary Green, Alphray
Defect inspection, yield analysis and optimization are integral components in the
development and manufacture of semiconductor devices. This session covers a variety
of techniques to improve yield using design, defect, electrical test, bitmap and failure
analysis data. Using two or more of these data sources together intelligently is a
recurrent theme.
9:05
6.1 SpotMe: Effective Co-optimization of Design and Defect Inspection for Fast Yield
Ramp
Yan Pan, Rao Desineni, Jane Lambert, Edward Teoh, Victor Lim, Goh Szu Huat,
Thomas Berndt, GLOBALFOUNDRIES; John Kim, Sagar Kekare, Synopsys
9:30
6.2 Use of Performance Path Test to Optimize Yield
Jeanne Paulette Bickford, Jinjun Xiong, IBM
Session 7 Advanced Metrology I (sponsored by Metryx) (Room M2A)
Chairs: Israel Ne’eman, Applied Materials, Alok Vaid, GLOBALFOUNDRIES
This session details some advanced metrology techniques, including new
ellipsometry, spectrometry, infra-red, e-beam, X-ray and metrology modeling
use cases.
9:05
7.1 Composition Measurement Of Tri-layer SiGe Stack Using Broadband
Spectroscopic Ellipsometry
Michael Anderson, Felipe Tijiwa Birk, Alok Vaid, GLOBALFOUNDRIES; Leander
Haensel, Ronny Haupt, Carlos Ygartua, Frank Shu, KLA-Tencor
9:30
7.2 MBIR for In-line Doping Metrology of Epitaxial SiGe:B and SiC:P Layers
Romain Duru, Delphine Le-Cunff, Thomas Nguyen, David Barge, Yves Campidelli,
STMicroelectronics; Nicolas Laurent, Jonny Hoglund, Semilab
9:55 Break (sponsored by ATMI)
9:55 Break (sponsored by ATMI)
10:15
6.3 Statistical Correlation of Inline Defect to Sort Test in Semiconductor Manufacturing
Uwe Hessinger, Brett Schafman, Wendy Chan, Toan Nguyen, Shiree Burt, Lattice
Semiconductor Corporation
10:40
6.4 Heading Towards Big Data: Building A Better Data Warehouse For More Data, More
Speed and More Users
Raymond Goss, Kousikan Veeramuthuk GLOBALFOUNDRIES
11:05
6.5 Case Studies of Fault Isolation for the Global Failing Patterns on SRAM Bitmap
caused by the Defects in Peripheral Logic Regions
Jianhua Yin, Jian Yu, Sheng Xie, Dapeng Sun, Yong Ern Ling, GLOBALFOUNDRIES;
Zhigang Song, Carl E. Schiller, Genadi Teverskoy, Manuel J. Villalobos, IBM
10:15
7.3 Full Wafer Nanotopography Analysis on Rough Surfaces Using Stitched White
Light Interferometry Images
Dirk Lewke, Martin Schellenberger, Lothar Pfitzner, Fraunhofer Institute of Integrated
Systems and Device Technology (IISB); Thomas Fries, Bastian Tröger, Alexander
Muehlig, FRT GmbH; Frank Riedel, Stefan Bauer, Hubert Wihr, Siltronic AG
10:40
7.4 3D X-Ray Microscopy: A Non-Destructive High Resolution Imaging Technology
That Replaces Physical Cross-Sectioning for 3D IC Packaging
Yuri Andrade Sylvester, Luke Hunter, Bruce Johnson, Xradia; Tulip Chou, TSMC
11:05
TM
7.5 Leveraging Applied Materials TechEdge Prizm for Advanced Lithography
Process Control
Paul Llanos, Roger Cornell, Applied Materials
11:30 Boxed Lunch (sponsored by Synopsys)
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Session 8 – Defect Inspection I (sponsored by Greene Tweed) (Room M2B)
Chairs: Jeff Barnum, KLA-Tencor; Jason Mazzotti, IBM; Kazunori Nemoto, Hitachi HiTech
Defect inspection, yield analysis and optimization are integral components in the
development and manufacture of semiconductor devices. This session will feature a
novel 'virtual' inspection technique, improvements in optical and edge inspection, and
defect sampling methodologies to help drive yield.
12:00
8.1 Optimizing Inspection Recipes by Using Virtual Inspection and Failure Bitmap
Roma Jang, Dongchul Ihm, Byoungho Lee, Samsung Electronics Co. Ltd
Gangadharan Sivaraman, Chang Ho Lee, Jian Wu, Graham Lynch, George Simon, Poh
Boon Yong, KLA-Tencor
12:25
8.2 Leveraging Puma DF wafer inspection to characterize root cause of yield loss on an
advanced 32 nm HKMG SOI technology device
Alisa Blauberg, Tom Timberlake, Andrew Stamper, Daniel Jaeger, MaryJane Brodsky,
Renee Mo, IBM Corporation; Gangadharan Sivaraman, Jeff Barnum, Gary Crispo, KLATencor
12:50
8.3 Defect Sampling Methodology For Yield Learning During 22nm Process
Development
Chen Xu, Vikas Sachan, Oliver D. Patterson, Julie Lee, IBM
1:15
8.4 Systematic edge inspection for defect reduction
Pratik Joshi, R. Van Roijen, J. Coffin, S. Conti, P. Flaitz, J. Eastman, IBM
Session 9 - Advanced Equipment Processes and Materials (Room M2A)
Chairs: Chris Long, IBM; Brett Williams, ONSemiconductor
Both advanced memory, analog and logic manufacturers face daunting challenges as
the next generation device nodes come on line. These challenges are being met by the
development and applications of innovations in equipment, materials, and processes.
This session will focus on solutions to advanced application requirements and will
highlight the latest innovations that are being implemented in leading edge high volume
manufacturing.
12:00
9.1 Advanced Process Control for Furnace Systems in Semiconductor Manufacturing
Amit Sonar, Satyajit Shinde, Yulei Sun, GLOBALFOUNDRIES
12:25
9.2 Pre-Clean Synergy with Poly CMP Process
Lai Kah Keen, Goh, Wooi Cheang; Chen Yan; Peck, Yan Zheng; Park, Won Gyu;
GLOBALFOUNDRIES (Singapore) Pte Ltd
12:50
9.3 Novel Process Strategies for Strip over TiN
Li Diao, Vijay Vaniapura, Robert Mueller, Mattson Technology, Inc.
1:15
9.4 Methods of Removing Solvent-like Residues from Wafer Backside Bevel
Sheng-Yuan Chang, Cheng-Yi Lung, An Chyi Wei, Hong-Ji Lee, Nan-Tzu Lian, Tahone
Yang, Kuang-Chao Chen and Chih-Yuan Lu; Macronix International Co., Ltd.
1:40 BREAK (sponsored by ATMI)
1:40 BREAK (sponsored by ATMI)
Corporate Sponsors:
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Session 10 E-Beam Inspection (Room M2B)
Chairs: Jennifer Braggin, Entegris; Jeanne P. Bickford, IBM
Defect inspection, yield analysis and optimization are integral components in the
development and manufacture of semiconductor devices. This session will feature
papers describing how e-beam inspection is used to rapidly drive yield for both physical
and voltage contrast defects.
2:00
10.1 Early Detection of Systematic Patterning Problems for a 22nm SOI Technology
using E-Beam Hot Spot Inspection
Oliver D. Patterson, Deborah A. Ryan, Mike D. Monkowski, Dominique Nguyen-ngoc,
Bradley Morganfeld, IBM
Chung-ham Lee, Chieh-hung Liu, Chi-ming Chen, Shih-tsung Chen, Hermes
Macrovision Inc.
2:25
10.2 Early Detection of Electrical Defects in Deep Trench Capacitors using Voltage
Contrast Inspection
Brian Donovan, Oliver D. Patterson, W. Chang, N. Arnold, B. Messenger, O. Kwon, J.
Liu, IBM ; Roland Hahn, KLA-Tencor
2:50
10.3 E-beam Inspection for Gap Physical Defect Detection in 28nm CMOS Process
Tsung Chih Chen, Chen Nan Tsai, White Pai,United Microelectronics Corporation;
Curious Wu, Fei Wang ,Luke Lin, Hermes Microvision
3:15
10.4 E-beam Inspection of EUV Programmed Defect Wafers for Printability Analysis
Ravi Bonam, Scott Halle, Daniel Corliss, IBM Research Division; Hung-Yu Tien, Fei
Wang, Wei Fang, Jack Jau, Hermes-Microvision Inc.
Session 11 Advanced Process Control (APC) (Room M2A)
Chairs: Agnés Roussy, EMSE; Raymond Van Roijen, IBM
This session covers innovations for advanced process control, including new
methods in fault detection and classification (FDC), process controls and
virtual metrology for predictive maintenance.
2:00
11.1 Case of Small-Data Analysis for Ion Implanters in the Era of Big-Data
FDC
Keung Hui, Jason Mou, Taiwan Semiconductor Manufacturing Company
2:25
11.2 Characterization and Real Time Fault Detection of Vacuum Leaks in
Plasma Nitridation Tools
Joseph F. Shepard, Jr., Mark L. Reath, IBM Microelectronics; James K.
Wilson, Applied Materials
2:50
11.3 Virtual Metrology for Prediction of Etch Depth in a Trench Etch Process
Georg Roeder, Lothar Pfitzner, Martin Schellenberger ; Fraunhofer Institute
of Integrated Systems and Device Technology (IISB); Sirko Winzer , Stefan
Jank, Infineon Technologies
3:15 (STUDENT)
11.4 Application of PCA for Efficient Multivariate FDC of Semiconductor
Manufacturing Equipment
Alexis Thieullen, Mustapha Ouladsine, LSIS, Aix-Marseille University;
Jacques Pinaton, STMicroelectronics
3:40 Break (sponsored by ATMI)
3:40 Break (sponsored by ATMI)
4:00pm-5:30 Panel Discussion - 450mm Wafers – Supersize Me! (sponsored by DAS Environmental Expert) (Room M1)
Moderator:
Paul Farrar, Director, G450C
Panelists:
Kirk Hasserjian, Corporate Vice President, SSG, Applied Materials
Dr. Brian Trafas, Chief Marketing Officer, KLA-Tencor
Mark Fissel, Vice President, 450 mm Program, Lam Research Corporation
Dr. John Lin, Director of 450mm Project, TSMC
6:30pm-7:30pm
Reception at GLOBALFOUNDRIES Fab 8 Malta (Buses leave from outside City Center – Grove Street)
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The 24th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference ASMC 2013
Thursday, May 16, 2013 (Day Three)
7:00-7:30
Registration
8:00-9:00
3D/TSV Tutorial: Sarasvathi Thangaraju, Package Technology and Integration group, GLOBALFOUNDRIES Fab 8 Malta (Room M2B)
Session 12 Yield Enhancement II (Room M2B)
Chairs: Philippe Campion, STMicroelectronics; Amiad Conley, Applied Materials;
Larry Pulvirent, GLOBALFOUNDRIES
Defect inspection, yield analysis and optimization are integral components in
the development and manufacture of semiconductor devices. This session
covers process engineering work in N2 purge and cleans to minimize
defectivity and improve yield.
9:05
12.1 Defect Reduction by Nitrogen Purge of Wafer Carriers
Raymond Van Roijen, P. Joshi, S. Conti, W. Brennan, P. Findeis, IBM; D. Bailey, PDF
Solutions
9:30
12.2 Single Wafer Cleaning Lessons in Advanced Node Gate Module Development
David F. Hilscher, Daniel Jaeger, Charlotte DeWan, Maryjane Brodsky, Ryan
Rettmann, IBM Semiconductor Research and Development Center
9:55
12.3 Hybrid Clean Approach for Post Copper CMP Defect Reduction
Wei-Tsu Tseng, Vamsi Devarapalli, James Steffes, Adam Ticknor, Mahmoud
Khojasteh, Praneetha Poloju, Colin Goyette, David Steber, Leo Tai, Steven Molis, Mary
Zaitz, Elliott Rill, Surbhi Mittal, Michael Kennett, Laertis Economikos, George Ouimet,
Christine Bunke, Connie Truong, Stephan Grunow, Michael Chudzik, IBM
Session 13 Advanced Metrology II (Room M2A)
Chairs: Franz Heider, Infineon; Dick James, Chipworks
This session details some advanced metrology techniques, including new ellipsometry,
spectrometry, infra-red, e-beam, X-ray and metrology modeling use cases.
9:05
13.1 Scatterometry-based on-product Focus measurement and monitoring
Timothy A. Brunner, Cheuk W. Wong, Pawan Rawat, IBM; Paul Hinnen, Vivien Wang,
Hossein Mardanpour, Jan Beltman, Erica Rottenkolber, Christian Leewis, ASML
19:30
13.2 Advanced Litho-Cluster Control via Integrated In-Chip Metrology
Kaustuve Bhattacharyya, Henk-Jan H. Smilde, Arie den Boef, Andreas Fuchs, Steffen
Meyer, ASML Netherlands B.V.; Chih-Ming Ke, Guo-Tsai Huang, Kai-Hsiung Chen,
Taiwan Semiconductor Manufacturing Company, Ltd.
9:55
13.3 Automated Transmission Electron Microscopy for Defect Review and Metrology of
Si Devices
Mark J. Williamson, Michael Strauss, FEI Company
10:20 Break (sponsored by Xradia)
10:20 Break (sponsored by Xradia)
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Session 14 Defect Inspection II (Room M2B)
Chairs: Mike Sevegney, Pall Corp. Dieter Rathei, DR Yield
Defect inspection, yield analysis and optimization are integral components in the
development and manufacture of semiconductor devices. This session will feature a
number of case studies where key technology limiting defect types are characterized
and eliminated. The final paper is a study of the ability of different tools and tool modes
to measure the size of defects.
10:35
14.1 Gan-On-Si Process Defect Detection and Analysis for HB-LED’s and Power
Devices
Sandip Halder, Karen Stiers, Prem Kumar Kandaswamy, Maarten Rosmeulen, Laureen
Carbonell, Yoga Saripalli, Haris Osman, Erik Rosseel, imec; Antonio Mani, Srinivas
Vedula, Marco Polli, KLA-Tencor
11:00
14.2 Detecting Yield Limiting SiGe Defects for 28nm Ramping
Elston Chen, Wen Pang Lin, Garry Chen, P Y Chiang, White Pai, Ying Chih Lai,
United Microelectronics Corporation; Sam Chen, Mahatma Lin, Frank Jin, Eros Huang ,
Harvey Cheng, Tetsuya Yamamoto, KLA-Tencor
11:25
14.3 On the Generation and Elimination of Lonely Poly-Silicon Crater-Defects and
Their Impacts on Gate Oxide Integrity (GOI) in Dual-Gate Technology
Lieyi Sheng, Paul Porath, Eddie Glines, ON Semiconductor
11:50
14.4 In-situ Detection of Photoresist Failures
Farhad Mirian, Thomas Bitzer, Infineon Technologies AG
12:15 Keynote:
Session 15 Advanced Equipment Processes and Materials (Room M2A)
Chairs: Naomi Yoshida, AMAT; Rob Pearson, RIT
This session provides an overview of the state of advanced memory technology, spin
torque magnetic memory and novel processing techniques. The final paper gives insight
into the status of volume high-purity carbon nanotube production.
10:35
15.1 Recent Advances in Memory Technology
Dick James, Chipworks Inc.
11:00
15.2 Integrating Spin-Torque-Transfer Magnetic Memory in a 65 nm Low Power CMOS
Technology
Douglas Coolbaugh, Michael Liehr, Michelle Pautler, College of Nanoscale Science and
Engineering; Rajiv Ranjanb, Ebi Abedifard, Avalanche Technology
11:25
15.3 Improving Electric Behavior and Simplifying Production of Si-Based Diodes by
Using Thermal Laser Separation
Matthias Koitzsch, Dirk Lewke, Martin Schellenberger, Lothar Pfitzner, Heiner Ryssel,
Fraunhofer Institute of Integrated Systems and Device Technology (IISB); Robert Kolb,
Robert Bosch GmbH; Hans-Ulrich Zühlke, Jenoptik Automatisierungtechnik GmbH
11:50
15.4 Contamination Control and Pilot Manufacturing of Commercial Grade Carbon
Nanotube Colloidal Formulations
Billy Smith, Thomas Kocab, Rahul Sen, David A. Roberts, Nantero Inc.
IC Market Trends and Forecast
Bill McClean, President, IC Insights (Room M2B)
1:00 Closing Remarks
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