A short tutorial on “Gate-Level simulation using a VHDL test bench and ModelSimAltera”
1) The Symbol
2) The VHDL description
See Unit 2.5 for a better understanding of the VHDL style used in this example.
-- Example of a BCD synchronous counter with count enable (CE) and terminal count (TC10)
-- using FSM style (the only one possible in CSD)
LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY ONE_DIG_BCD_counter_style_FSM IS
Port (
CLK
: IN
STD_LOGIC;
CD
: IN
STD_LOGIC;
CE
: IN
STD_LOGIC;
Q
: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
TC10
: OUT STD_LOGIC
);
END ONE_DIG_BCD_counter_style_FSM;
-- Internal desciption in FSM style
ARCHITECTURE FSM_like OF ONE_DIG_BCD_counter_style_FSM IS
CONSTANT Max_Count
: STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001"; -- terminal_count after 10 states
CONSTANT Reset
: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
-- Internal wires --> in this case just the present and future state signals
SIGNAL present_state,future_state: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
------------------------- State register
-- This is the only clocked block, which is essentially a set of D-type flip-flops in parallel
-- The asynchronous reset (Clear Direct) has precedence over the CLK
State_Register: PROCESS (CD, CLK)
BEGIN
IF CD = '1' THEN -- reset counter ( an asynchronous reset which we call "Clear Direct"
present_state <= Reset;
ELSIF (CLK'EVENT and CLK = '1') THEN -- Synchronous register (D-type flip-flop)
present_state <= future_state;
END IF;
END PROCESS State_Register;
-- CC1 ---------- Combinational circuit for calculating next state
-Generally, even for a simple FSM, this circuit will be complicated enough
-for using a process in order to code it easier.
CC1: PROCESS (present_state, CE)
BEGIN
IF CE = '1' THEN
IF(present_state < Max_Count ) THEN
future_state <= present_state + 1 ;
ELSE
future_state <= Reset;
END IF;
ELSE
future_state <= present_state; -- count disable
END IF;
END PROCESS CC1;
--- CC2 ------------Combinational circuit for calculating the outputs
-There will be circuits like ths counter where this circuit will be easily implemented
-just using equations
TC10 <= '1' WHEN ((present_state = Max_count)AND CE = '1') ELSE '0';
Q <= present_state;
--terminal count
END FSM_like;
3) Functional simulation of the code in ModelSim-Altera using a test bench
Let’s start a Quartus-II project to generate the test bench template “*.vht”
Add some stimulus to the test bench (CLK and other signals processes)
clk_signal : PROCESS
BEGIN
CLK <= '0';
wait for 5 us;
CLK <= '1';
wait for 5 us;
-- clock cycle is 10 us
END PROCESS clk_signal;
other_signals : PROCESS
-- code executes for every event on sensitivity list
BEGIN
CD <= '0';
CE <= '0';
wait for 17.5 us;
CD <= '1';
-- Clear direct
CE <= '0';
wait for 16.18 us;
CD <= '0';
CE <= '1';
-- Count enable
wait for 150.67 us;
CE <= '0';
-- Count disable
wait for 50 us;
CE <= '1';
-- Count enable
WAIT;
END PROCESS other_signals;
END ONE_DIG_BCD_counter_style_FSM_arch;
Run a ModelSim-Altera functional simulation
Add waves and run enough time to check the outputs:
4) Quartus II synthesis to generate the “*.vho” and the “*.sdo”
Generate a new project in Quartus II and specify the ModelSim-Altera tool for simulation. Set the output
directory to “./simulation/modelsim”.
Synthesise and check how the EDA netlist writer has produced the “*.vho” and the “*.sdo” files.
5) Gate-level simulation of the code in ModelSim-Altera using the same previous test bench
Use the same test bench from the previous functional simulation to start a new ModelSim-Altera project to
run the gate-level simulation.
Simulate the test bench entity, the “one_dig_bcd_counter_style_fsm_vhd_tst” in this example:
And attach the “ONE_DIG_BCD_counter_style_FSM_vhd.sdo” applied to the “i1” instance:
Add the timing diagram:
And check that the delays at a given input transition correspond or match the ones from the Quartus-II
Classic Timing Analyser tool: