Supplementary Material for “Sign-changing non-monotonic voltage gain of
HfO2/Parylene-C/SrTiO3 field-effect transistor due to percolative insulator to twodimensional metal transition”
Alejandro Schulman1, Ai Kitoh1, Pablo Stoliar* 1,2, and Isao H. Inoue* 1
1
National Institute of Advanced Industrial Science and Technology (AIST), AIST Tsukuba Central 5,
Tsukuba 305-8565, Japan
2
CIC nanoGUNE, Tolosa Hiribidea 76 , 20018 Donostia-San Sebastian, Spain
*To whom correspondence should be addressed. E-mail: [email protected], [email protected]
Capacitive coupling
The channel of our STO FET is highly insulating (the
sheet resistance is larger than 1015) for VG below ~1.5V,
because the STO surface covered by the Parylene-C layer
does not have enough amount of defects to provide carriers
before applying VG. Then, there is no current path
connecting any pairs of electrodes in the highly insulating
channel, all the pairs of electrodes behave as capacitors.
This is called the capacitive coupling. Each capacitance is
negligibly small. However, our electrical instrumentation
to measure the voltage has very large input resistance (1015
Ω), therefore, in order to compensate the small
displacement current for charging the capacitor, a large
voltage must be virtually applied. The time constant of the
charging period is given by a product of the capacitance
and the input resistance of the instrumentation, and is
actually very long (~1000s). Thus, for the voltage sweep
rate of our dc measurements, V1 becomes fairly large when
the channel is highly insulating as shown in Fig. 1b of the
main text. Increasing the gate voltage above ~1.5V, the
sub-threshold current starts flowing, and the effect of
capacitive coupling disappears.
Technical details regarding numerical methods
Integration of Eq. (1) was performed by the Euler method
for the 1D channel divided into 3000 segments. We used
the ‘shooting’ method to match the boundaries conditions,
using ID as a tuning parameter (Newton-Raphson). The
convergence was set as the error in Vx(L) = VD < 0.1% or
ΔID < 0.1pA. We set ID = 0 if n < 10-10 in any segments of
the channel. Otherwise, dVx/dx becomes so large at the
segment that the boundaries conditions will never be
achieved with reasonable ID values.
Hall effect measurements
The Hall voltage VH, i.e., the voltage difference
perpendicular to the current ID (the voltage between V1 and
its counterpart in Fig. 1a of the main text) were measured
in a magnetic field B applied perpendicular to the channel
surface.
In general, ID is kept fixed in Hall effect measurements.
However, since we use the semiconductor parameter
analyser and the resolution of VD is not sufficient, the
constant ID measurement is not appropriate. Instead, we
fixed VD = 0.1V and measured ID. The Hall resistance Rxy
= VH / ID shows a linear dependence of B for all the VG
studied (as shown in Fig. S1). The Hall coefficient RH =
Rxy / B was then obtained directly from the slope of the
Rxy-B plot by a least-squares linear fitting of the data. The
sheet carrier density n□ was deduced from n□ = 1/eRH,
where e is the elementary charge.
Fig S1: Hall resistance Rxy vs. B for different vallues of VG. The
solid lines are the least-squares linear fitting of Rxy, utilized to
deduce the Hall coefficient RH.
An estimation of the capacitance of our gate insulator C is
𝑐
required to compute 𝑛𝑔𝑒𝑜 = (𝑉G − 𝑉x − 𝑉th ). To this end,
𝑒
we fabricated Ti / Parylene-C (3nm) / HfO2 (20nm) / Ti
/Au parallel plate capacitors, and measured quasi-static C
using an Agilent 4155C semiconductor parameter analyser.
As shown in Fig. S2, C is proportional to the area, and is
well fitted by a linear expression.
The parasitic capacitance (the extrapolation of C at the
area of zero) is 4.6pF while the sheet capacitance (slope)
was found to be 0.42μF/cm2. This value of the sheet
capacitance was found to be independent of applied
voltage and magnetic field.
It should be noted here this value of C (0.42μF/cm2) is for
a Parylene-C (3nm) / HfO2 (20nm) double layer. In our
STO FET, the gate insulator is a Parylene-C (6nm) / HfO2
(20nm) double layer. To calculate the actual C of our FET
devices, we use a dielectric constant of 20 for the HfO2
layer, as reported in many literatures, and estimate the one
for Parylene-C from Fig. S2. The obtained value of C was
0.305μF/cm2.
Fig. S4: Experimental results for the voltage gain transfer curve
for different values of VD. The arrow indicates the evolution of
𝑉𝐺𝑚𝑖𝑛 . For VG < 2V capacitive coupling dominates the V1 signal.
Fig S2: Capacitance of Ti / Parylene-C (3nm) / HfO2 (20nm) / Ti
/Au parallel plate capacitors in funcion of the area, obtained by
quasistatic measurement.
The effect of VD
In order to corroborate further our 1D percolation model
with nonlinear conductance, we have examined the effect
of VD as a control parameter. As mentioned in the main
text, we studied the behaviour of our model for different
values of VD and compared it with the corresponding
experimental data. As VD increases, the negative-gain
region shifts towards higher VG in the simulation (Fig. S3).
The same behaviour is indeed observed in our
measurements (Fig. S4), bearing out the validity of our
model.
Fig. S3: Simulations of the voltage gain transfer curve for
different values of VD. The arrow indicates the evolution of 𝑉𝐺𝑚𝑖𝑛 .