Chapter 2
Digital Test Architectures
EE141
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Test Architectures
Ch. 2 – Digital Test Architectures - P. 1
What is this chapter about?
 Introduce
Basic Design for Testability
(DFT) Techniques
 Focus
on Widely Used or Emerging DFT
Architectures
 Illustrate
Basic Test Architectures,
Low-Power Test Architectures, and
Speed Test Architectures
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At-
Ch. 2 – Digital Test Architectures - P. 2
Digital Test Architectures
 Introduction
 Scan
Design
 Logic Built-In Self-Test
 Test Compression
 Random-Access Scan Design
 Concluding Remarks
EE141
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Ch. 2 – Digital Test Architectures - P. 3
Introduction
Scan
Logic
BIST
At-Speed
Delay
Testing
Test
Compression
LowPower
Testing
Fault
Tolerance
Defect and
Tolerance
Evolution
Helloof DFT advances in testing digital circuits
EE141
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Ch. 2 – Digital Test Architectures - P. 4
Introduction

Scan Design
 Replace all selected storage elements with scan cells
 Connect scan cells into multiple shift registers (scan chains)
 Become inefficient to test deep submicron or nanometer
VLSI

Logic Built-In Self-Test (BIST)
 Combine with scan approach at the design stage
 Generate test patterns and analyze the output response
 Crucial for safety-critical and mission-critical applications
EE141
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Ch. 2 – Digital Test Architectures - P. 5
Introduction

Test Compression
 A supplemental DFT technique to scan
 Can reduce test data volume and test application time
 Add some additional on-chip hardware

Random-Access Scan Design
 Randomly and uniquely addressable, similar to RAM
 A promising alternative to Scan design for shift power
reduction
EE141
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Ch. 2 – Digital Test Architectures - P. 6
Scan Design




Widely used structured DFT architecture
Replace all selected storage elements with scan cells
Connect scan cells into scan chains
Operated in three modes:
 Normal mode
– All test signals are turned off.
– The scan design operates in the circuit’s original functional
configuration.
 Shift mode
– to shift data into and out of the scan cells
 Capture mode
– to capture test response into scan cells
EE141
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Ch. 2 – Digital Test Architectures - P. 7
Scan Architectures
DI
SI
0
1
SE
Q
D
Q/SO
X1
X2
X3
CK
Muxed-D Scan Cell
The multiplexer uses a scan
enable (SE) to select
between the data input (DI)
and the scan input (SI).
EE141
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CK
Y1
Y2
Combinational logic
FF1
FF2
FF3
D Q
D Q
D Q
.
.
Sequential circuit example
Ch. 2 – Digital Test Architectures - P. 8
Scan Architectures
PI
X1
X2
X3
Y1
Combinational logic
Y2
Replace FF1, FF2 and
PO FF3 with SFF1, SFF2 and
SFF3.
PPO
PPI
In shift mode, SE is set to
1, the scan cells operate as
a single scan chain.
SI
SE
CK
SFF1
SFF2
SFF3
DI
SI Q
SE
DI
SI Q
SE
DI
SI Q
SE
. .
.
.
.
. .
SO
In capture mode, SE is set
to 0, scan cells are used to
capture the test response
from the combinational
logic.
Muxed-D Scan Design
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Ch. 2 – Digital Test Architectures - P. 9
Scan Architectures
DI
Q/SO
SI
DCK
Input selection is
conducted using two
independent clocks, data
clock DCK and shift
clock SCK.
SCK
Clocked-Scan Cell
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Ch. 2 – Digital Test Architectures - P. 10
Scan Architectures
X1
X2
X3
PI
Y1
PPO
PPI
SI
DCK
SCK
PO
Y2
Combinational logic
SFF1
SFF2
SFF3
DI
SI
Q
DCK SCK
DI
Q
SI
DCK SCK
DI
Q
SI
DCK SCK
. .
.
.
.
DCK and SCK are
used for
distinguishing shift
and capture
operations; while SE
is used to switch the
shift and capture
operations in muxedD scan design.
SO
. .
Clocked-Scan Design
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Ch. 2 – Digital Test Architectures - P. 11
Scan Architectures
D
.
A
+L1
.
C
I
. .
L1
SRL
.
.
L2
.
+L2
.
B
Polarity–hold shift register latch (SRL)
SRL can be used as an LSSD
scan cell. This scan cell
contains two latches, a
master two-port D latch L1
and a slave D latch L2.
Clocks C, A, and B are used
to select between D and +L1
and +L2.
Level-Sensitive Scan Design
(LSSD) can be implemented
using a single-latch design or
a double-latch design.
LSSD Scan Cell
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Ch. 2 – Digital Test Architectures - P. 12
Scan Architectures
X1
X2
X3
Combinational logic 1
Y1
SI
C1
A
B
C2
Combinational logic 2
..
.
SRL1
SRL2
SRL3
D
I +L2
C
A +L1
B
D
I +L2
C
A +L1
B
D
I +L2
C
A +L1
B
Y2
The system clocks
C1 and C2 should
be applied in a
nonoverlapping
fashion.
SO
..
LSSD single-latch design
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Ch. 2 – Digital Test Architectures - P. 13
Scan Architectures
During the shift
X1
X2
X3
Combinational logic
SI
C1
A
C2 or B
Y1 operation, clocks A and
Y2 B are applied in a
..
.
SRL1
SRL2
SRL3
D
I +L2
C
A +L1
B
D
I +L2
C
A +L1
B
D
I +L2
C
A +L1
B
.
..
.
.
LSSD double-latch design
EE141
System-on-Chip
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.
nonoverlapping manner,
and the scan cells, SRL1
~ SRL3, form a single
scan chain from SI to
SO SO.
During the capture
operation, clocks C1and
C2are applied in a nonoverlapping manner to
load the
test response from the
combinational logic into
the scan cells.
Ch. 2 – Digital Test Architectures - P. 14
Scan Architectures

Enhanced-Scan Design
 An alternative at-speed scan design for testing
delay faults; testing of a delay fault requires a pair
of test vectors in an at-speed fashion.
 Enhanced-scan cell can store two bits of data;
achieved by adding a D latch to a muxed-D scan
cell or clocked-scan cell.
 Disadvantages:
– Higher hardware overhead
– May activate many false paths causing an over-test
problem
EE141
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Ch. 2 – Digital Test Architectures - P. 15
Scan Architectures
X1
X2
Xn
..
.
LA1
UPDATE
D
.
LA2
D
Q
C
CK
.
LAs
…
Q
C
.
SFF1
SDI
SE
..
.
Combinational logic
DI
SI Q
SE
.
D
Q
C
SFF2
SFFs
DI
SI Q
SE
DI
SI Q
SE
.
…
…
…
Enhanced-Scan Design
.
. .
EE141
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Y1
Y2
Ym
The first test vector V1 is
shifted into SFF1 ~ SFFs
and then stored into the
additional latches (LA1 ~
LAs) when the UPDATE
signal is set to 1.
Next, the second test vector
V2 is shifted into the scan
cells while the UPDATE
signal is set to 0, in order to
preserve the V1 value in the
latches (LA1 ~ LAs).
Once the second vector V2
is shifted in, the UPDATE
signal is applied, in order to
change V1 to V2 while
capturing the output
response at-speed into the
scan cells by applying CK
after exactly one clock
cycle.
Ch. 2 – Digital Test Architectures - P. 16
Low-Power Scan Architectures

Serial Scan Design
 Advantage:
– Low routing overhead
 Disadvantages:
– Scan cells cannot be controlled or observed without affecting
□ in the same scan chain
the values of other scan cells
– High switching activities during shift and capture can cause
excessive shift (or test) power dissipation

Low-Power Scan Design
 Test power is related to dynamic power, and is proportional
to VDD2f
– VDD is the supply voltage
– f is the switching frequency of the circuit node under test
EE141
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Ch. 2 – Digital Test Architectures - P. 17
Example Low-Power Scan Architectures

Reduced-Voltage Low-Power Scan Design
 Reduce the supply voltage

Reduced-Frequency Low-Power Scan Design
 Slow down the shift clock frequency but increase test
application time

Multi-Phase Low-Power Scan
Design
□
 Split the shift clock into a number of nonoverlapping clock
phases but increase routing overhead and complexity during
clock tree synthesis

Bandwidth-Matching Low-Power Scan Design
 Use pairs of serial-in/parallel-out shift register and parallelin/serial-out shift register for bandwidth matching

Hybrid Low-Power Scan Design
 Combine any of the above-mentioned low-power scan
designs
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Ch. 2 – Digital Test Architectures - P. 18
Multi-Phase Low-Power Scan Design
X1
X2
X3
PI
Y1
PO
Y2
Combinational logic
PPO
PPI
□
SI
SE
CK1
CK2
CK3
.
SFF1
SFF2
SFF3
DI
SI Q
SE
DI
SI Q
SE
DI
SI Q
SE
.
.
.
The clock CK is split into
three clock phases CK1,
CK2, and CK3.
Using this scheme, a 3X
reduction in shift power
can be achieved,
assuming each clock
drives an equal number of
scan cells.
SO
.
EE141
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Ch. 2 – Digital Test Architectures - P. 19
Bandwidth-Matching Low-Power Scan Design
SI1
...
SIm
.
TDDM
Full-Scan
Circuit
...
sm0 sm1 sm2 sm3
...
t13 . . .
□
s10 s11 s12 s13
t10 t11 t12
Each scan chain is
split into 4 sub-scan
ck1
chains with the SI and
Clock
Controller SO ports of each 4
sub-scan chains
connected to a serialck2
in/parallel-out shift
register and a parallelin/serial-out shift
register, respectively.
tm0 tm1 tm2 tm3
TDM
...
SO1
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SOm
Ch. 2 – Digital Test Architectures - P. 20
At-Speed Scan Architectures
 Synchronous
Design
 A scan design if the active edges of all
capture clocks controlling the clock
domains can be aligned
precisely or
□
triggered simultaneously
 Asynchronous
Design
 A scan design if not synchronous
EE141
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Ch. 2 – Digital Test Architectures - P. 21
At-Speed Scan Architectures

Two basic schemes for test multiple clock domain at-speed
 Skewed-load (Launch-on-shift)
– Use the last shift clock pulse followed immediately by a capture
clock pulse to launch the transition and capture the output
response
 Double-capture (Launch-on-capture or Broad-side)
– Use two consecutive capture clock pulses to launch the
transition and capture the output test response

Similarity
 Can test path-delay faults and transition faults. The second capture
clock pulse must be running at the domain’s operating frequency or
at-speed.

Difference
 Skewed-load requires the domain’s SE to switch value between the
launch and capture clock pulses making SE act as a clock signal.
EE141
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Ch. 2 – Digital Test Architectures - P. 22
Launch
Capture
Launch
Capture
Basic At-Apeed Test Schemes
CK
CK
SE
SE
Shift
Shift
Last
Shift
Skewed-load
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Shift
Shift
Shift
Dead
Cycles
Shift
Double-capture
Ch. 2 – Digital Test Architectures - P. 23
Clock grouping
 Can
reduce test application time and
test data volume during automatic test
pattern generation (ATPG)
 Is a process used to analyse all data
paths in the scan design in order to
determine all independent or
noninteracting clocks that can be
grouped and applied simultaneously
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Ch. 2 – Digital Test Architectures - P. 24
Clock grouping example
CD1
CD2 and CD3 are independent
from each other; hence their
related clocks can be applied
simultaneously during test as
CK2.
CK1
CCD1
CCD2
CD2
CD3
CCD3
CCD4
CK2
CCD5
CK3
CD4
CD5
CD6
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CD7
CD4 through CD7 can also be
applied simultaneously during
test as CK3.
Therefore three grouped
clocks instead of seven
individual clocks can be used
to test the circuit during the
capture operation.
Ch. 2 – Digital Test Architectures - P. 25
Clock schemes

One-hot clocking
 Apply only one grouped clock during each capture operation
 Produce the highest fault coverage but generate most test
patterns

Simultaneous clocking
 Mask off unknown values at the originating scan cells or
receiving scan cells across clock domains
 Generate the least number of patterns but may result in high
fault coverage loss

Staggered clocking
 Grouped clocks are applied sequentially
 Generate pattern count close to simultaneous clocking and
fault coverage close to one-hot clocking
EE141
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Ch. 2 – Digital Test Architectures - P. 26
At-speed Clocking Scheme for Testing Two
Interacting Clock Domains
(One-hot clocking)
Shift Window
CK1
CK2
…
Capture Window
C1 C2
…
Shift Window
Capture Window Shift Window
…
…
…
C3 C4
…
GSE
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Ch. 2 – Digital Test Architectures - P. 27
At-speed Clocking Scheme for Testing Two
Interacting Clock Domains
(Simultaneous clocking)
Shift Window
CK1
CK2
…
…
Capture Window
C1 C2
C3 C4
Shift Window
…
…
GSE
EE141
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Ch. 2 – Digital Test Architectures - P. 28
At-speed Clocking Scheme for Testing
Two Interacting Clock Domains
(Staggered clocking)
Shift Window
CK1
CK2
…
…
Capture Window
C1 C2
C3 C4
Shift Window
…
…
GSE
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Ch. 2 – Digital Test Architectures - P. 29
How to Generate Shift and Capture Clocks
 Supplied
from the Tester
 Increase test cost
 Limited high-frequency channels
 Generated
by Phase-Locked Loop (PLL)
 Pipelined Scan Enable (SE) signal
 Test clock controller
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Ch. 2 – Digital Test Architectures - P. 30
Pipelined Scan Enable (SE)
Design
SE1 for positive-edge
scan cells
SE
SE2 for negative-edge
scan cells
D Q
D Q
CK
CK
CK
EE141
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D Q
CK
Ch. 2 – Digital Test Architectures - P. 31
On-Chip Clock Controller
Shift Register
scan_en
D
Q
Q1
Q2
Q3
Q4
Q5
scan_clk
The clock-gating
cell makes sure
that no glitches or
spikes appear on
clk_out.
hs_clk_en
PLL
pll_clk
Clock-Gating cgc_clk_out
0
Cell
clk_out
1
When scan_en is set to 1, scan_clk is directly connected to clk_out;
when scan_en is set to 0, the output of the clock-gating cell is directly
connected to clk_out.
EE141
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Ch. 2 – Digital Test Architectures - P. 32
On-Chip Clock Controller - Waveform
scan_clk
scan_en
pll_clk
hs_clk_en
cgc_clk_out
clk_out
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Ch. 2 – Digital Test Architectures - P. 33
Logic Built-In Self-Test (BIST)
Test Pattern Generator
(TPG)
Logic
BIST
Controller
The logic BIST
controller provides a
pass/fail indication
once the BIST
operation is complete.
Circuit Under Test
(CUT)
Output Response Analyzer
(ORA)
A typical logic BIST system
EE141
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Ch. 2 – Digital Test Architectures - P. 34
Logic Built-In Self-Test

TPG
 Constructed from linear feedback shift register
(LFSR) or cellular automata
 Exhaustive testing – all possible 2n test patterns
 Pseudo-random testing – a subset of 2n test
patterns
 Pseudo-exhaustive testing – 2w or 2k-1 test
patterns, where w < k < n

ORA
 Constructed from multiple-input signature register
(MISR)
EE141
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Ch. 2 – Digital Test Architectures - P. 35
Logic BIST Architectures
 Test-per-Scan
BIST
 Hardware overhead is low
 Test-per-Clock
BIST
 Execute tests faster than Test-per-Scan
BIST
 More hardware overhead
EE141
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Ch. 2 – Digital Test Architectures - P. 36
Example Logic BIST Architectures

Self-Testing Using MISR and Parallel SRSG
(STUMPS)
 Based on test-per-scan BIST
 Integrate with traditional scan architecture
 Linear phase shifter and linear phase compactor is
often used
 Lose some fault coverage

Concurrent Built-In Logic Block Observer
(CBILBO)




Based on test-per-clock BIST
Signature analysis is separated from test generation
Possible to achieve 100% single-stuck fault coverage
Hardware cost is higher than STUMPS
EE141
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Ch. 2 – Digital Test Architectures - P. 37
STUMPS
PRPG
Linear Phase Shifter
PRPG
CUT
CUT
(C)
(C)
Linear Phase Compactor
MISR
MISR
STUMPS
EE141
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A STUMPS-based architecture
Ch. 2 – Digital Test Architectures - P. 38
B1
- 0
1 1
0 1
CBILBO
B2 Operation mode
Normal
Scan
Test Generation and Signature Analysis
Y0
Y2
Y1
B1
Scan-Out
0
D Q
Q
D Q
1D
2D Q
SEL
1D
2D Q
SEL
D
1
1D
2D Q
SEL
1
0
Scan-In
B2
SCK
X0
X1
X2
A three-stage concurrent BILBO (CBILBO)
EE141
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Ch. 2 – Digital Test Architectures - P. 39
CC2
TPG
MISR
CBILBO
CC1
TPG
CBILBO
MISR
MISR
MISR
TPG
CBILBO
Combinational
CUT
TPG
Example CBILBO Applications
CBILBO
(a) For testing a finite-state machine
(b) For testing a pipelined-oriented circuit
CBILBO Architectures
EE141
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Ch. 2 – Digital Test Architectures - P. 40
Coverage-Driven Logic BIST Architectures
 Approaches
to Enhance logic BIST
Fault Coverage
 In-field coverage enhancement
– Weighted Pattern Generation
– Test Point Insertion
– Mixed-Mode BIST
 Manufacturing Coverage Enhancement
– Hybrid BIST
EE141
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Ch. 2 – Digital Test Architectures - P. 41
Weighted Pattern Generation
Employ an LFSR
1
0
0
Insert a combinational
circuit between the output
of LFSR and the CUT
0
Skew the LFSR probability
distribution of 0.5 to either
0.25 or 0.75
X4
X3
X1
X2
Example weighted LFSR as PRPG
EE141
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Ch. 2 – Digital Test Architectures - P. 42
Test Point Insertion
Observation point
Control point
0
1
BIST_mode
(a) Test point with a multiplexer
Observation point
Control point
BIST_mode
(b) Test point with AND-OR gates
Typical test point inserted for improving
a circuit’s fault coverage
EE141
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Ch. 2 – Digital Test Architectures - P. 43
Example of Inserting Test Points to Improve
Detection Probability
X1
X2
X3
X4
X5
X6
Y
1
Min. Detection
= 64
Probability
(a) An output RP-resistant stuck-at-0 fault
EE141
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X1
X2
X3
X4
X5
X6
Y
Control point
Observation point
7
Min. Detection
=
128
Probability
(b) Example inserted test points
Ch. 2 – Digital Test Architectures - P. 44
Test Point Insertion

Test Point Placement
 Use fault simulation
 Use testability measures to guide them

Control Point Activation
 During normal operation
– Deactivated
 During testing
– Random activation
– Deterministic activation
EE141
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Ch. 2 – Digital Test Architectures - P. 45
Mixed-Mode BIST
 ROM
Compression
 Store deterministic patterns in ROM
 LFSR
Reseeding
 Generate deterministic patterns by
reseeding LFSR with computed seeds
 Embedding
Deterministic Patterns
 Transform the “useless” patterns into
deterministic patterns
EE141
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Ch. 2 – Digital Test Architectures - P. 46
Hybrid BIST
 Perform
top-up ATPG for the faults not
detected by BIST
 Store the patterns directly on the tester
 Store the patterns on the tester in a
compressed form and make use of the
existing BIST hardware to decompress
them
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Ch. 2 – Digital Test Architectures - P. 47
Low-Power Logic BIST Architecture
 Low-Transition
BIST Design
 Insert an AND gate and a toggle flip-flop at
the scan input of the scan chain
 Advantages:
– Less design intrusive
– no performance degradation
– Low hardware overhead
 Disadvantages:
– Low fault coverage
– Long test sequence
EE141
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Ch. 2 – Digital Test Architectures - P. 48
Low-Power Logic BIST Architecture
 Test-Vector-Inhibiting
BIST Design
 Inhibit the LFSR-generated pseudorandom patterns which do not contribute to
fault detection from being applied to the
CUT
 Advantages:
– Reduce test power
– No fault coverage loss as the original LFSR
 Disadvantage:
– High hardware overhead
EE141
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Ch. 2 – Digital Test Architectures - P. 49
Low-Power Logic BIST Architecture
 Modified
LFSR Low-Power BIST Design
 Use two interleaved n/2-stage LFSRs
 Advantages:
– Shorter test length
– High percentage of power reduction
– No performance degradation
– No test time increase
 Disadvantage:
– Require constructing special clock trees
EE141
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Ch. 2 – Digital Test Architectures - P. 50
At-Speed Logic BIST Architectures

Single-capture
 One-hot single-capture
 Staggered single-capture

Skewed-load
 One-hot skewed-load
 Aligned skewed-load
 Staggered skewed-load

Double-capture
 One-hot double-capture
 Aligned double-capture
 Staggered double-capture
EE141
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Ch. 2 – Digital Test Architectures - P. 51
One-Hot Single-Capture
Shift Window
Capture Window
Shift Window Capture Window
Shift Window
C1
…
CK1
…
…
d1
d2
C2
…
…
…
CK2
GSE

Advantages:
 No need to worry about clock skews between clock domains
 Can be used for slow-speed testing
 Use a global scan enable (GSE) signal – compatible with Scan

Disadvantage:
 Long test time
EE141
System-on-Chip
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Ch. 2 – Digital Test Architectures - P. 52
Staggered Single-Capture
Shift Window
CK1
CK2
…
d1
…
Capture Window
C1
d2
Shift Window
…
d3
C2
…
GSE

Advantage:
 Can detect inter-clock-domain delay faults within two clock domains

Disadvantage:
 May cause some structural fault coverage loss if the sequence
order of the capture clocks is fixed.
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 53
One-Hot Skewed-Load
Shift Window Capture Window Shift Window Capture Window Shift Window
S1 C1
CK1
…
d1
…
SE1
CK2
…
…
…
S2 C2
d2
…
SE2

Advantage:
 Can be used for at-speed testing of intra-clock-domain delay faults

Disadvantages:
 Cannot be used for testing of inter-clock-domain delay faults
 Long test time
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 54
Aligned Skewed-Load
S
C
S1
S2
S3
C1
Capture Window
S1
CK1
SE1
CK1
SE1
C2
CK2
SE2
CK2
SE2
C3
CK3
SE3
CK3
SE3
Capture aligned skewed-load

Launch aligned skewed-load
Advantage:
 All intra-clock-domain and inter-clock-domain faults can be tested in
synchronous clock domains

Disadvantage:
 Require more complex timing-control diagram
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 55
Staggered Skewed-Load
Shift Window
CK1
…
Capture Window
S1 C1
Shift Window
…
d1
SE1
d3
CK2
…
S2 C2
d2
…
SE2

Advantage:
 All intra-clock-domain and inter-clock-domain faults can be
tested in both synchronous and asynchronous clock
domains.

Disadvantage:
 Complicated physical implementation
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 56
One-Hot Double-Capture
Shift Window
CK1
CK2
…
Capture Window Shift Window
C1 C2
Capture Window Shift Window
…
d1
…
…
…
C3 C4
d2
…
GSE

Advantage:
 Can be used for true at-speed testing of intra-clock-domain delay
faults

Disadvantages:
 Cannot be used for testing of inter-clock-domain delay faults
 Long test time
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 57
Aligned Double-Capture
C1
C
C2
C
C3
C1
CK 1
Capture Window
C4
CK1
C2
CK2
CK 2
C3
CK3
GSE
CK 3
GSE
Capture aligned double-capture
 Advantage:
Launch aligned double-capture
 Can test all intra-clock-domain and inter-clock-domain delay
faults in synchronous clock domains

Disadvantage:
 Require precise alignment capture pulses
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 58
Staggered Double-Capture
Shift Window
CK1
CK2
…
d1
…
Capture Window
C1
d2
Shift Window
…
d3
C2
…
GSE

Advantages:
 Ease physical implementation
 Integrate logic BIST with scan/ATPG

Disadvantage:
 May cause fault coverage loss due to the ordered
sequence of capture clocks.
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 59
Summary of Industry Practices for
At-Speed Logic BIST
Industry Practices
Skewed-load
Double-Capture
Encounter Test
Through service
Through service
ETLogic
√
√
Through service
LBIST Architect
TurboBIST-Logic
EE141
System-on-Chip
Test Architectures
√
√
Ch. 2 – Digital Test Architectures - P. 60
Test Compression

Decompressor
 Add some additional on-chip hardware before the
scan chains to decompress the test stimulus
 Use lossless compression

Compactor
 Add some additional on-chip hardware after scan
chains to compact the response
 The compaction is lossy

Advantages:
 Reduce ATE memory
 Reduce test data volume and test application time
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 61
Test Compression Architecture
Compressed
Low-Cost Stimulus
ATE
D Stimulus
e
c
o
m
p
r
e
s
s
o
r
EE141
System-on-Chip
Test Architectures
Response
Scan-Based
Circuit
(CUT)
C
o
m
p
a
c
t
o
r
Compacted
Response
Ch. 2 – Digital Test Architectures - P. 62
Circuits for Test Stimulus Compression

Linear-Decompression-Based Schemes
 Combinational linear decompressors
 Sequential linear decompressors

Broadcast-Scan-Based Schemes






Broadcast scan
Illinois scan
Multiple-input broadcast scan
Reconfigurable broadcast scan
Virtual scan
Comparison
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 63
Linear-Decompression-Based Schemes

Linear Decompressor Concept
 Consists of only XOR gates and Flip-Flops
 Its output space is a linear subspace that is spanned by a
Boolean matrix.

Combinational Linear Decompressor
 Consists of only XOR gates

Sequential Linear Decompressor
 Consists of XOR gates and Flip-Flops
 Flip-flops provides additional free variables for state encoding.
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 64
Example of
symbolic simulation
for linear
decompressor
X1
X9 X7 X5
+
Z5
Z1
Z10 Z6
Z2
Z11 Z7
Z3
Z12
Z4
Z9
X2
X3
+
X4
X10 X8 X6
+
Z8
Z9 = X1  X4  X9
Z5 = X3  X7
Z1 = X2  X5
Z10 = X1  X2  X5  X6
Z6 = X1  X4
Z2 = X3
Z11 = X2  X3  X5  X7  X8
Z7 = X1  X2  X5  X6
Z3 = X1  X4
Z12 = X3  X7  X10
Z8 = X2  X5  X8
Z4 = X1  X6
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 65
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
1
0
0
0
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
=
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12
System of linear equations for the decompressor
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 66
Combinational Linear Decompressor
 Advantage:
 Simpler hardware and control because only XOR
gates are used
 Disadvantages:
 Low Encoding Efficiency
– Because no free variables are used
– Can be improved by dynamically adjusting the
number of scan chains that are loaded in each
clock cycle.
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 67
Sequential Linear Decompressor

Based on linear finite-state machines
 Examples: LFSRs, cellular automata, ring generators

Advantages:
 Allow free variables from earlier clock cycles
 Much greater flexibility than combinational linear decompressor

Two classes
 Static reseeding
– Drawbacks
 The tester is idle while the LFSR is running in autonomous
mode.
 The LFSR must be at least as large as the number of
specified bits in the test cube.
 Dynamic reseeding
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 68
b Channels
from Tester
L
F
S
R
Combinational
Linear
Decompressor
Typical Sequential Linear Decompressor
Scan Chain 1 ( m bits)
Scan Chain 2 ( m bits)
Scan Chain n (m bits)
Dynamic reseeding calls for the injection of free variables
coming from the tester into the LFSR as it loads the scan
chains
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 69
Broadcast-Scan-Based Schemes
 Broadcast
scan
 Illinois Scan
 Multiple input broadcast scan
 Reconfigurable broadcast scan
 Virtual scan
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 70
Broadcast Scan
Scan_input
SC1
123
…
SC2
N1
123
…
SCK
…
123
N2
…
Nk
…
C1
C2
Ck
- Broadcasting to scan chains driving independent circuit
- Won’t affect fault coverage if all circuits are independent
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 71
Illinois Scan

Consists of two modes of operations
 Broadcast mode
 Serial scan mode

Main Drawback
 No test compression in serial scan mode

Ways to reduce number of patterns
 Multiple-Input broadcast scan
 Reconfigurable broadcast scan
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 72
Illinois Scan Architecture
Scan In
Segment 1
MISR
Segment 2
Segment 3
Scan Out
Segment 4
(a) Broadcast mode
Scan In
Scan Out
Scan Chain
(b) Serial chain mode
Two Mode of Illinois Scan Architecture
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 73
Multiple-input broadcast scan
 Use
more than one channel to drive all
scan chains
 The
shorter each scan chain is, the
easier to detect more faults because
fewer constraints are placed on the
ATPG
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 74
Reconfigurable Broadcast Scan
Reduce the number of required channels
compared to multiple-input broadcast scan
 Provide the capability to reconfigure the set of
scan chains
 Two possible reconfiguration schemes

 Static reconfiguration
 Dynamic reconfiguration
– Need more control information versus static
reconfiguration
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 75
Pin Pin Pin Pin Control Line
1 2 3 4
0
Scan Chain 1
1
0
Scan Chain 2
1
0
Scan Chain 3
1
0
Scan Chain 4
1
Scan Chain 5
0
Scan Chain 6
Scan Chain 7
1
Scan Chain 8
Example MUX Network with Control Line(s) connected only to
select pins of the multiplexers
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 76
Virtual Scan

Use Combinational logic network for stimulus
decompression – called Broadcaster
 Buffers, inverters, AND/OR gates, MUXs, XOR gates

Advantages
 One-Step ATPG – No need to solve linear equations as
required in sequential linear decompressor.
 Dynamic compaction can be effectively utilized during
the ATPG process.
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 77
Example Virtual Scan Broadcaster
Using an XOR Network
External Scan Input Ports
SI1
s10
s11
s12
VirtualScan Inputs
SI2
s13
s20
s21
VI1 VI2
s22
s23
Internal Scan Chain Inputs
Broadcaster using an example XOR network with
additional VirtualScan Inputs to reduce coverage loss
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 78
Example Virtual Scan Broadcaster
Using a MUX Network
External Scan Input Ports
SI1
s10
s11
s12
VirtualScan Inputs
SI2
s13
s20
VI1 VI2
s21
s22
s23
Internal Scan Chain Inputs
Broadcaster using an example MUX network with additional
VirtualScan inputs that can also be connected to data pins of the
multiplexers
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 79
Comparison
100.0
Illinois
MUX-Separate
Percent Encodable
80.0
MUX-Combined
2-input XOR
3-input XOR
60.0
40.0
20.0
0.0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Specified Bits
Encoding flexibility among combinational decompression schemes
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 80
Circuits for Test Response Compaction
 Performed
at the output of scan chains
 To reduce the amount of test response
 Grouped into three categories
 Space compaction
 Time compaction
 Mixed space and time compaction
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 81
Space Compaction
 Space
compactor is combinational
 Inverse procedure of linear expansion
 Compaction Techniques




X-Compact
X-Blocking
X-Masking
X-Impact
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 82
X-tolerant Response Compaction
SC1
SC2
SC3
SC4
XOR
XOR
XOR
XOR
XOR
Out 1
XOR
Out 2
SC5
XOR
XOR
XOR
Out 3
SC6
XOR
SC7
XOR
SC 8
XOR
XOR
Out 4
XOR
XOR
Out 5
An X-compactor with 8 inputs and 5 outputs
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 83
X-compactor

Theorem 2.1
 If only a single scan chain produces an error at any scan-out
cycle, the X-compactor is guaranteed to produce errors at
the X-compactor outputs at that scan-out cycle, if and only if
no row of the X-compact matrix contains all 0’s.

Theorem 2.2
 Errors from any one, two, or an odd number of scan chains
at the same scan-out cycle are guaranteed to produce errors
at the X-compactor outputs at that scan-out cycle, if every
row of the X-compact matrix is nonzero, distinct, and
contains an odd number of 1’s.
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 84
X-Blocking (X-Bounding)
Block X’s before reaching the response
compactor
 Scan design rule checker for identifying
potential X-generators
 Impact





No X’s will be observed
Fault coverage loss
Add area overhead
May impact delay due to the inserted logic
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 85
X-Masking
Mask off X’s right before the response compactor
Scan Out 1
Mask Bit 1
Scan Out 2
Scan Out 3
Mask Bit 2
Compactor
Mask Bit 3
Mask
Controller
An example X-masking circuit
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 86
X-Impact
?
SC1
a
?
?
b
c
1
1
X
?
?
d
e
f
g
h
G1
G3
G4
G5
G2
.
.
G7
p
G8
q
SC2
SC3
f1
SC4
G6
Handling of X-Impact
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 87
X-Impact
?
SC1
a
0
1
b
c
1
1
d
e
f
g
h
G1
G3
f 2 G2
.
G7
p
G8
q
SC2
SC3
G4
G5
SC4
G6
Handling of Aliasing
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 88
Time compaction
 Uses
sequential logic to compact test
response
 No unknown (X) values are allowed to reach
the compactor; otherwise X-bounding, Xmasking must be employed.
 MISR is most widely used
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 89
Mixed Time and Space Compaction
Combine the advantages of a time compactor
and a space compactor but with high area
overhead
 Examples of mixed time and space
compactors

 OPMISR
 Convolutional Compactor
 q-compactor
– No feedback path
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 90
q-compactor
inputs
output
D
D
D
D
D
An example q-compactor with single output
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 91
Low-Power Test Compression Architectures

Low-Power architectures
 The Bandwidth-match low-power scan design can be used
for test compression

An Example – The UltraScan Architecture




Time-Division Demultiplexer (TDDM)
Time-Division Multiplexer (TDM)
Clock Controller
The TDDM/TDM circuit operates at 10 MHz and slow down
the shift clock frequency to 1 MHz resulting in 10X reduction
in shift power dissipation
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 92
UltraScan
ATE
Test Responses
Pass/Fail
Comparator
Expected Responses
Test Patterns
ESI 1
...
TDDM
VirtualScan
Circuit
...
SI 1
VirtualScan
Inputs
ESIn
ck1
Clock
Controller
SI m
Broadcaster
Full-Scan
Circuit
s10 s11 s12 s13
t10 t11 t12
...
...
t13 . . .
sm0 sm1 sm2 sm3
ck2
tm0 tm1 tmm2 tmm3
Compactor
SO1
...
SOm
ck1
TDM
ESO1
EE141
System-on-Chip
Test Architectures
...
ESOn
Ch. 2 – Digital Test Architectures - P. 93
Summary of Industry Practices for
Test Compression
Industry Practices Stimulus Decompressor
Response Compactor
XOR Compression Combinational XOR network XOR network with or
or OPMISR+
or Fanout Network
Without MISR
TestKompress
Ring generator
XOR network
VirtualScan
Combinational logic network XOR network
DFT MAX
Combinational MUX network XOR network
ETCompression
(Reseeding)PRPG
MISR
UtralScan
TDDM
TDM
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 94
Summary of Industry Practices for
At-Speed Delay Fault Testing
Industry Practices
Skewed-Load Double-Capture
XOR Compression or OPMISR+
√
√
TestKompress
VirtualScan
DFT MAX
ETCompression
UtralScan
EE141
System-on-Chip
Test Architectures
√
√
√
√
√
√
√
√
Through service
√
Ch. 2 – Digital Test Architectures - P. 95
Random-Access Scan Design

Eliminate problems in serial scan mode
 Excessive dynamic power during capture
 difficult fault diagnosis

Scan cell randomly and uniquely addressable
 Similar to storage cell in random-access memory
(RAM)

Impacts
 Low shift power dissipation with an increase in
routing overhead
 Combinational logic diagnosis techniques for
locating faults
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 96
Random-Access Scan Architectures

Traditional Random-Access Scan (RAS) Architecture
 All scan cells are organized into a two-dimensional array
 Advantage
– Can reduce shift power dissipation
 Disadvantages
– No guarantee to reduce test application time or test data volume
– High area overhead

Progressive Random-Access Scan Design (PRAS)
 Use a structure similar to SRAM or a grid-addressable latch

Shift-Addressable Random-Access Scan Design (STAR)
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 97
Traditional RAS Architecture
Combinational logic
SC
SC
SC
…
…
SC
…
PO
SC
CK
SC
…
SC
…
Row (X) decoder
SC
…
PI
Access to a scan cell by
decoding a full address with a
row decoder (X) and a column
decoder (Y)
SI
SCK
SO
SC
Column (Y) decoder
Address shift register
EE141
System-on-Chip
Test Architectures
AI
Ch. 2 – Digital Test Architectures - P. 98
Traditional RAS Scan Cell
D
SI
TM
DI Q
0
1
.
Q
DI Q
CK
.
PO
SI
SI
SE
AS
D
Q
SE Q
CK
..
AS
Traditional Scan Cell Design
Broadcast the external SI port to
all scan cells, cause routing
problem
EE141
System-on-Chip
Test Architectures
Toggle Scan Cell Design
Require a clear mechanism to
reset all scan cells prior to testing
Ch. 2 – Digital Test Architectures - P. 99
PRAS Design
In normal mode, RE is set to 0, forcing
each scan cell to act as a normal D
flip-flop.
In test mode, RE is set to 0
and a pulse is applied on clock Φ
SD
RE
SD
Ф
Ф
D
Q
Ф
Ф
Ф
Ф
PRAS Scan Cell Design
EE141
System-on-Chip
Test Architectures
To read out, clock Φ is held at 1,
RE for the selected scan cell is set to 1,
and the content of the scan cell is read
out through the bidirectional scan data
signals SD and SD_.
To write or update a scan value into
the scan cell, clock Φ is held at 1, RE
for the selected scan cell is set to 1,
and the scan value and its complement
are applied
on SD and SD_, respectively
Ch. 2 – Digital Test Architectures - P. 100
PRAS Design
TM
SI/SO
CK
Test
control
logic
SC
SC
…
…
SC
SC
… SC
…
Column line drivers
…
SC
SC
PO
Combinational logic
SC
…
SC
…
…
…
Row enable shift register
Sense-amplifiers & MISR
Rows are enabled in a fixed
order. It is only necessary to
supply a column address to
specify which scan cell in an
enabled row to access.
PI
Column address decoder
CA
PRAS Architecture
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 101
PRAS Test Procedure
for each test vector vi (i = 1, 2, …, N) {
/* Test stimulus application */
/* Test response compression */
enable TM;
for each row rj (j = 1, 2, …, m) {
read all scan cells in rj / update MISR;
for each scan cell SC in rj
/* v(SC): current value of SC */
/* vi(SC): value of SC in vi */
if v(SC)  vi(SC)
update SC;
}
/* Test response acquisition */
disable TM;
apply the normal clock;
}
scan-out MISR as the final test response;
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 102
STAR Design
SO
TM
CK
Test
control
logic
SC
SC
…
…
SC
SC
… SC
…
Column line drivers
…
SC
SC
Combinational logic
SC
PO
…
SC
…
…
…
Row enable shift register
Sense-amplifiers
PI
Use only one row (X) decoder and
support two or more SI and SO ports.
All rows are enabled (selected) in a
fixed order one at a time by
rotating a 1 in the row enable shift
register.
When a row is enabled, all columns
(or scan cells) associated with the
enabled row are selected at the same
time.
Buffers
SI
STAR Architecture
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 103
STAR Test Procedure
for each test vector vi (i = 1, 2, …, N) {
/* Test stimulus application */
/* Test response compression */
enable TM;
for each row rj (j = 1, 2, …, m) {
read all scan cells in rj / update MISR;
/* Update selected rows */
update all scan cells in rj;
}
/* Test response acquisition */
disable TM;
apply the normal clock;
}
scan-out MISR as the final test response;
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 104
Test Compression RAS Architecture
 RAS
design is effective in reducing shift
power dissipation
 RAS is achieved power reducing at the
cost of increased area and routing
overhead
 RAS cannot reduce test data volume
and test application time significantly
 Test compression schemes are
applicable for RAS design
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 105
STAR Compression Architecture
SO
TM
CK
Test
control
logic
SC
SC
…
…
SC
SC
… SC
…
Column line driver
…
SC
SC
Combinational logic
SC
PO
…
SC
…
…
…
Row enable shift register
Compactor
A decompressor is used to
decompress the ATE-supplied
stimuli.
A compactor is used to compact
the test responses.
PI
Decompressor
SI
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 106
Reconfigured STAR Compression
SO
Compactor
TM
CK
Test
control
logic
…
SC
SC
SC
…
SC
… SC
…
Column line drivers
…
SC
0 1
SC
0 1
Combinational logic
SC
…
SC
…
PO
…
Row enable shift register
…
The multiplexer allows transmitting
scan-in stimulus from one column to
another column.
The AND gate enables or disables the
scan-out test response on the column
to be fed to the compactor in serial
scan mode.
PI
0 1
Decompressor
SI
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 107
At-Speed RAS Architectures

Major advantages of RAS design
 Significant shift power reduction
 Facilitating fault diagnosis

Additional benefit for at-speed delay fault testing
 Launch-on-shift (a.k.a. skewed-load)
 Launch-on-capture (a.k.a. double-capture)

Enhanced-scan based at-speed RAS Design
 Maximize delay fault detection capability
 Long vector count problem
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 108
At-Speed RAS Architectures

Approaches to overcoming long vector count problem
 Using Enhanced-scan-based at-speed RAS architecture
 Using Conventional launch-on-capture schemes

Launch-on-capture based at-speed RAS architecture
 Allow multiple transitions on the initialization vector; thereby
reducing the vector count.

Hybrid at-speed RAS architecture
 First generate transition fault tests using launch-on-capture
 Then supplement the tests using enhanced scan

Faster-than-at-speed RAS architecture
 To catch small delay defects that escape traditional transition fault
tests.
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 109
Concluding Remarks




Scan and Logic built-in self-test (BIST) are two most widely
used DFT techniques
ATPG can no longer guarantee adequate product quality;
at-speed delay testing and test compression become a
requirement for 90-nanometer designs and below.
Physical failures can escape detection of ATPG; logic BIST
and low-power testing are gaining more industry
acceptance in VLSI designs at 65-nanometer and below.
Challenges lie ahead whether pseudo-exhaustive testing
will become a preferred BIST pattern generation technique
and random-access scan will be a promising DFT
technique for test power reduction.
EE141
System-on-Chip
Test Architectures
Ch. 2 – Digital Test Architectures - P. 110