Chapter #10: Finite State
Machine Implementation
No. 10-1
Chapter Outline
Implementation Strategies
discrete logic
design with counters, ROMs
programmable logic
PALs
FGPAs: Altera, Actel, Xilinx
No. 10-2
Implementation Strategies
Discrete Gate Logic
Emphasis so far
MSI Logic (e.g., Counters)
Structured Logic (e.g., PLA/PAL, ROM)
Field Programmable Gate Arrays (FPGAs)
Function can be configured "on the fly" or in the field
Flipflops/Registers plus discrete gates on the same chip
No. 10-3
Implementation Strategies
FSM Design with Structured Logic
Com bina tiona l
Logic
Registers
Output
Function
Inputs
Outputs
Block Diagram for
Synchronous Mealy Machine
Nex t State
Function
State
ROM-based Realization
ROM
A0
Registers
D0
Inputs
Outputs
An-1
Dk-1
An
Dk
An+m-1 Dk +m-1
Inputs & Current State
form the address
ROM data bits form the
Outputs & Next State
State
No. 10-4
Implementation Strategies
ROM-based Design
Example: BCD to Excess 3 Serial Converter
Conversion Process
Bits are presented in bit serial fashion
starting with the least significant bit
Single input X, single output Z
BCD Excess 3 Code
0000
0011
0001
0100
0010
0101
0011
0110
0100
0111
0101
1000
0110
1001
0111
1010
1000
1011
1001
1100
No. 10-5
Implementation Strategies
BCD to Excess-3 Converter
Prese nt State
S0
S1
S2
S3
S4
S5
S6
Output
X=0 X=1
0
1
0
1
1
0
1
0
0
1
1
0
-1
Nex t State
X=0 X=1
S2
S1
S4
S3
S4
S4
S5
S5
S6
S5
S0
S0
-S0
State Transition Table
Res et
0/1
S1
0/1
S0
S2
1/0
0/0,
1/1
0/1
0/0,
1/1
S5
Derived State Diagram
S4
S3
0/0,
1/1
1/0
1/0
S6
0/1
No. 10-6
Implementation Strategies
BCD to Excess 3 Converter
ROM-based Implementation
ROM Address
X Q2 Q1 Q0
0
0
0 0
0
0
0 1
0
0
1 0
0
0
1 1
0
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
1
0
0 0
1
0
0 1
1
0
1 0
1
0
1 1
1
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1
ROM Outputs
Z D2 D1 D0
1 0
0 1
1 0
1 1
0 1
0 0
0 1
0 1
1 1
0 1
0 0
0 0
1 0
0 0
X X X X
0 0
1 0
0 1
0 0
1 1
0 0
1 1
0 1
0 1
1 0
1 0
0 0
X X X X
X X X X
1
CLK
1
0
X
co nverter ROM
Z
X
D2
Q2
D1
Q1
D0
Q0
1
0
9
13
12
5
4
CLK
D
C
B
A
175
1 CLR
\Rese t
QD
QD
QC
QC
QB
QB
15
14
10
11
7
6
2
QA
3
QA
Circuit Level Realization
74175 = 4 x positive edge triggered D FFs
Truth Table/ROM I/Os
In ROM-based designs, no need to consider state assignment
No. 10-7
Z
Implementation Strategies
BCD to Excess-3 Converter
LSB
MSB
Timing Behavior for input strings 0 0 0 0 (0) and 1 1 1 0 (7)
0000
LSB
1100
1110
0101
LSB
No. 10-8
Implementation Strategies
BCD to Excess 3 Converter
PLA-based Design
State Assignment with NOVA
0
1
0
1
0
1
0
1
0
1
0
1
0
S0
S0
S1
S1
S2
S2
S3
S3
S4
S4
S5
S5
S6
S1
S2
S3
S4
S4
S4
S5
S5
S5
S6
S0
S0
S0
1
0
1
0
0
1
0
1
1
0
0
1
1
NOVA input file
S0 = 000
S1 = 001
S2 = 011
S3 = 110
S4 = 100
S5 = 111
S6 = 101
NOVA derived
state assignment
9 product term
implementation
No. 10-9
Implementation Strategies
BCD to Excess 3 Converter
D2 = Q2 • Q0 + Q2 • Q0
D1 = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0
D0 = Q0
Z = X • Q1 + X • Q1
1
CLK 9
1
0
X
converte r PLA
X
Q2
Q1
Q0
Z
D2
D1
D0
1
0
13
12
5
4
CLK
175
D
C
B
A
1 CLR
\Res et
15
QD
14
QD
10
QC
11
QC
7
QB
6
QB
2
QA
3
QA
Z
No. 10-10
Implementation Strategies
BCD to Excess 3 Serial Converter
10H8 PAL: 10 inputs, 8 outputs, 2 product terms per OR gate
D1 = D11 + D12
D11 = X • Q2 • Q1 • Q0 + X • Q2 • Q0
D12 = X • Q2 • Q0 + Q1 • Q0
No. 10-11
Implementation Strategies
BCD to Excess 3 Serial Converter
0. Q2 • Q0
1. Q2 • Q0
8. X • Q2 • Q1 • Q0
9. X • Q2 • Q0
16. X • Q2 • Q0
17. Q1 • Q0
24. D11
25. D12
32. Q0
33. not used
40. X • Q1
41. X • Q1
0 1 2 3
45
89
12 13 16 17 20 21 24 25 28 29 30 3 1
X
0
1
D2
8
9
D11
16
17
D12
24
25
D1
32
33
D0
40
41
Z
Q2
Q1
Q0
D11
D12
No. 10-12
Implementation Strategies
FSM Design with Counters
Synchronous Counters: CLR, LD, CNT
0
Four kinds of transitions for each state:
(1) to State 0 (CLR)
CLR
(2) to next state in sequence (CNT)
(3) to arbitrary next state (LD)
(4) loop in current state
CNT
n+1
n
no
signals
as serted
LD
m
Careful state assignment is needed to reflect basic sequencing
of the counter
No. 10-13
Implementation Strategies
FSM Design with Counters
Excess 3 Converter Revisited
Res et
0/1
1
0/1
0
4
1/0
0/0,
1/1
0/1
3
0/0,
1/1
Note the sequential nature
of the state assignments
5
2
0/0,
1/1
1/0
1/0
6
0/1
No. 10-14
Implementation Strategies
FSM Design with Counters
Excess 3 Converter
Inputs/Current
Next
State
State
X Q2 Q1 Q0 Q2+ Q1+
0 0 0 0
0
0
0 0 0 1
0
1
0 0 1 0
0
1
0 0 1 1
0
0
0 1 0 0
1
0
0 1 0 1
0
1
0 1 1 0
0
0
0 1 1 1
X
X
1 0 0 0
1
0
1 0 0 1
1
0
1 0 1 0
0
1
1 0 1 1
0
0
1 1 0 0
1
0
1 1 0 1
1
1
1 1 1 0
X
X
1 1 1 1
X
X
Outputs
Q0+
1
0
1
0
1
1
0
X
0
1
1
0
1
0
X
X
Z CLR LD
1 1 1
1 1 1
0 1 1
0 0 X
1 1 1
0 1 0
1 0 X
X X X
0 1 0
0 1 0
1 1 1
1 0 X
0 1 1
1 1 1
X X X
X X X
EN
1
1
1
X
1
X
X
X
X
X
1
X
1
1
X
X
C
X
X
X
X
X
0
X
X
1
1
X
X
X
X
X
X
B
X
X
X
X
X
1
X
X
0
0
X
X
X
X
X
X
A
X
X
X
X
X
0
X
X
0
1
X
X
X
X
X
X
Should be 1
See
Fig. 10.21
CLR signal has precedence over LD,
which in turn has precedence over EN
No. 10-15
Implementation Strategies
FSM Implementation with Counters
Excess 3 Converter Schematic
CLK
1
0
1
0
excess 3 PLA
X
Rese t
X
Q2
Q1
Q0
Z
\CLR
\L D
EN
C
B
A
7
P
10
163
T
RCO15
2
CLK
6 D
QD 11
5 C
QC 12
4 B
QB 13
3 A
14
QA
9 LOAD
1
D Q
Z
C Q
CLR
Synchronous Output Register
Bad choice for FSM design in this case!
Could be much better if fewer out-of-sequence jumps!
No. 10-16
Implementation Strategies
FSM Design with More Sophisticated PLDs
Programmable Logic Devices = PLD
PALs, PLAs = 10 - 100 Gate Equivalents
Field Programmable Gate Arrays = FPGAs
Altera MAX Family
Actel Programmable Gate Array
Xilinx Logical Cell Array
100 - 1000(s) of Gate Equivalents!
No. 10-17
Implementation Strategies
Design with More Sophisticated PLDs
Xilinx Logic Cell Arrays (LCA)
CMOS Static RAM Technology: programmable on the fly!
All personality elements connected into serial shift register
Shift in string of 1's and 0's on power up
IOB
IOB
CLB
IOB
CLB
IOB
Wiring Channels
CLB
CLB
IOB
General Chip Architecture:
Logic Blocks (CLBs)
IO Blocks (IOBs)
Wiring Channels
IOB
IOB
IOB
No. 10-18
Xilinx CLB architecture
5 general data inputs A, B, C, D, E
Data in (DIN)
2 outputs, X & Y
No. 10-19
Design Case Study
Traffic Light Controller
Decomposition into primitive subsystems
Controller FSM
next state/output functions
state register
Short time/long time interval counter
Car Sensor
Output Decoders and Traffic Lights
No. 10-20
From Chapter 8 …
Traffic Light Controller
Tabulation of Inputs and Outputs:
Input Signal
reset
C
TS
TL
Description
place FSM in initial state
detect vehicle on farmroad
short time interval expired
long time interval expired
Output Signal
HG, HY, HR
FG, FY, FR
ST
Description
assert green/yellow/red highway lights
assert green/yellow/red farmroad lights
start timing a short or long interval
Tabulation of Unique States: Some light configuration imply others
State
S0
S1
S2
S3
Description
Highway green (farmroad red)
Highway yellow (farmroad red)
Farmroad green (highway red)
Farmroad yellow (highway red)
No. 10-21
From Chapter 8 …
Traffic Light Controller
S2 Exit Condition: no car waiting OR long time interval expired
S0
H.HG
H.FR
0
H.ST
1
TL • C
S3
H.HR
H.FY
TS
0
1
H.ST
S1
H.HY
H.FR
0
TS
H.ST
H.ST
1
S2
H.HR
H.FG
0
TL + C
1
Complete ASM Chart for Traffic Light Controller
No. 10-22
From Chapter 8 …
Traffic Light Controller
Compare with state diagram:
TL + C
Rese t
S0: HG
S0
TL•C/ST
S1: HY
TS/ST
TS
S1
S2: FG
S3
TS
TS/ST
S3: FY
TL + C/ST
S2
TL • C
Advantages of ASM Charts:
Concentrates on paths and conditions for exiting a state
Exit conditions built up incrementally, later combined into
single Boolean condition for exit
Easier to understand the design as an algorithm
No. 10-23
Design Case Study
Traffic Light Controller
Block Diagram
Res et
Clk
TS
short time /
long time
counter
TL
F
controlle r fsm
Res et
C (a sync)
ST
Nex t State
Output
Logic
Car
Sensor C (s ync )
Clk
2
2
2
2
Encode d
Light
Signals
Light
Dec oders
3
3
H
State
Register
No. 10-24
Design Case Study
Traffic Light Controller
0
Subsystem Logic
Light
Decoders
Pres ent
D
C
Q
F0
2 A
3 B
F1
1
RQ
\Pre sent
1
FG FY
+
Cin
0
G
Y0
Y1
Y2
Y3
139a
FR
4
5
6
7
1
\Res et
0
0
HG HY HR
+
H0
CLK
H1
Car Detector
1 A
Y0
1
4 B
Y1
3
Y2
1 G
Y3
5
139b
1
1
2
1
09
+
Cf. debouncing switch
in Section 6.6.1
Interval
Timer
CLK
Reset
7 P
10 T 163
1
2 CLK RCO
5
6 D
QD 11
5 C
QC 12
4 B
QB 13
3 A
QA 14
9 LOAD
CLR 1
CLR
TL
TS
ST
No. 10-25
Design Case Study
Traffic Light Controller
Next State Logic
State Assignment: HG = 00, HY = 10, FG = 01, FY = 11 from Section 9.3.1
P1 = C TL Q1 + TS Q1 Q0 + C Q1 Q0 + TS Q1 Q0
P0 = TS Q1 Q0 + Q1 Q0 + TS Q1 Q0
ST = C TL Q1 + C Q1 Q0 + TS Q1 Q0 + TS Q1 Q0
H1 = TS Q1 Q0 + Q1 Q0 + TS Q1 Q0
H0 = TS Q1 Q0 + TS Q1 Q0
F1 = Q0
F0 = TS Q1 Q0 + TS Q1 Q0
PAL/PLA Implementation:
5 inputs, 7 outputs, 8 product terms
PAL 22V10 -- 11 inputs, 10 prog. IOs, 8 to 14 prod terms per OR
ROM Implementation:
32 word by 8-bit ROM (256 bits)
Reset may double ROM size
No. 10-26
Design Case Study
Traffic Light Controller
Next State Logic
Counter-based Implementation
HG
TL
• C / ST
HY
TS / ST
FG
TL+C / ST
TS
TL
\C
TL
C
1 GA
3 A3
4 A2
5 A1
6 A0
13
12
11
10
B3
B2
B1
B0
15 GB
2 x 4:1 MUX
153
YA 7
YB 9
S1 SO
2 14
ST
+
7
10 P 163
T
15
2 CLK RCO
6
5
4
3
D
C
B
A
QD
QC
QB
QA
11
12
13
14
Q1
Q0
9 LOAD
\Res et 1 CLR
FY
TS / ST
TTL Implementation with MUX and Counter
ST = Count
No. 10-27
Design Case Study
Traffic Light Controller
Next State Logic
Counter-based Implementation
Dispense with direct output functions for the traffic lights
Why not simply decode from the current state?
HG HY HR
1
1 G
Q1
Q0
3B
2A
Y3
Y2
Y1
Y0
0
0
FG FY
0
0
FR
1
7
6
5
4
139a
ST is a Mealy Output
Light Controllers are Moore Outputs
No. 10-28
Design Case Study
Traffic Light Controller
Logic Control Arrays (LCA)-Based Implementation
Discrete Gate Method:
None of the functions exceed 5 variables
P1, ST are 5 variable (1 Configurable Logic Block (CLB) each)
P0, H1, H0, F0 are 3 variable (1/2 CLB each)
F1 is 1 variable (1/2 CLB)
4 1/2 CLBs total!
No. 10-29
Design Case Study
Traffic Light Controller
LCA-Based
Implementation
TL C TS
TS
TS
Q0
Placement of
functions selected
to maximize the
use of direct
connections
DI CE A
B
X
C F0
K
Y
E D R
TL
DI CE A
B
X
C
K
Y
E D R
F1
Q0
Q1
Q0
TS
Q1
DI CE A
B
X
C Q1
K
Y
E D R
Q0
Q1
TS
DI CE A
B
X
C
K
Y
E D R
H1
H0
C
Q1
TL
TS
C
Q0
DI CE A
B
X
C ST
K
Y
E D R
DI CE A
B
X
C
K
Y
E D R
No. 10-30
Design Case Study
Traffic Light Controller
LCA-Based Implementation
Counter/Multiplexer Method:
4:1 MUX, 2 Bit Upcounter
MUX: six variables (4 data, 2 control)
but this is the kind of 6 variable function that can be
implemented in 1 CLB!
2nd CLB to implement TL • C and TL + C'
But note that ST/Cnt is really a function of TL, C, TS, Q1, Q0
1 CLB to implement this function of 5 variables!
2 Bit Counter: 2 functions of 3 variables (2 bit state + count)
Also implemented in one CLB
Traffic light decoders: functions of 2 variables (Q1, Q0)
2 per CLB = 3 CLB for the six lights
Total count = 5 CLBs
No. 10-31
Chapter Summary
Optimization and Implementation of FSM
State Reduction Methods: Row Matching, Implication Chart
State Assignment Methods: Heuristics and Computer Tools
Implementation Issues
Choice of Flipflops
Structured Logic Methods
ROM based
PLA/PAL based
Jump Counter Methods
Sophisticated Programmable Logic Devices (PLDs):
Altera, Actel, Xilinx
No. 10-32