Generation of signals in Matlab using Xilinx blocks
HTE - 07.11.2014
1. Basics
There are a number of ways to extract the signals generated in Matlab into the physical world as
electrical signals. The two basic ones are
A. Use of external (A/D) cards connected to PC outputs (such as USB). One example is NI USB6259 from National Instruments
B. Use of additional software that will work with Matlab, make designs in the form of Simulink
blocks utilizing this facility and finally download it into (for instance) an FPGA (Field
Programmable Gate Array) card to obtain the electrical version.
In this course, we concentrate on option B and use the related Xilinx software, since it also allows
complete system design possibilities. The steps to create such a platform and implement designs in
Matlab are summarized below ;
a) Installation of Xilinx ISE or Vivado to interact with Matlab, and start of Matlab via System
Generator thus created.
b) Implement designs as model files using Xilinx as well as Simulink blocks, ensuring the correct
functionality of design with the help of Simulink Scope and / or hardware co-simulation.
c) Generating the (VHDL) code via System Generator button in the model file.
d) Test of code in ISE or Vivado, output pin assignment, conversion to bit file and downloading
it into FPGA card.
e) Verification of correct functionality by observing outputs on actual scope instrument.
Some screen shots for a) and b) above are given in Figs. 1.1 and 1.2. As seen from Fig. 1.1, the
appearance of Matlab after being started with System Generator is no different from the
conventional Matlab, but it allows the access to Xilinx blocks shown on the right hand side. A model
file constructed with combination of Xilinx and Simulink blocks is available in Fig. 1.2. There the Xilinx
blocks are coloured blue and labelled with the sigma (  ) sign. The properties of Xilinx blocks are
quite similar to Simulink blocks. The main difference is that Xilinx blocks operate in binary arithmetic.
The objective in the model file of Fig. 1.2 is to generate sinusoidal signals, downloadable into the
Virtex-5 (or Virtex-6, 7) Xilinx FPGA cards. This is accomplished by Xilinx “CORDIC SINCOS” block in
the middle. This block needs to be driven by an input ranging in  to   . To provide such an
input, we employ a “Counter”, situated on the far left hand side. To seen the adjustable parameters
of this counter, just like we do in the case of Simulink blocks, we double click on the “Counter”,
acquiring the menu panel given in Fig. 1.3. We expect from this counter a cyclic behaviour, that can
later be confined to the range of  to   . We choose a signed four bit counting, which means, if
the “Step” is chosen as 1, then the counter will count from 8 to  7 .
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Fig. 1.1 The screen shot of Matlab after being started from
following the installation of ISE.
(System Generator)
Fig. 1.2 Model file for sinusoidal signal generation with the combined use of Xilinx and Simulink
blocks.
The decimal and binary intepretations of this counting are as follows
8 :1: 7   8  7  6  5  4  3  2  1

Binary


01 2 3 4 5 6
7



1000 1001 1111 0000  0110 0111
(1.1)
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Fig. 1.3 Menu panel of Counter in the model file of Fig. 1.2.
As seen from (1.1), the vectorial length of the present count is 16. But for a beter representation of
sinusoidal signals, we prefer within one cycle (one period) higher number of samples than 16. This
can be by lowering the step size. Since we are operating in binary environment, it is more convenient
to select the step size in powers of 2, rather than in decimal increments. If the step size is set to 1/16,
then we will need a total of 8 bit representation with four bits for the integer part (three bits to
magnitude, one bit to sign) and the remaining four bits for the fractional part. This way, (1.1) will turn
into
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8 :1/16 : 7.9375   8   1.0625  0.0625  7.9375 

Binary





10000000  1 110 1111  00000001  01111111
sign integer part fractional part


(1.2)
Note that the binary representation in (1.2) in the the two’s complement notation.
The range in (1.2) can be reduced to  to   in the manner described by the following function
“HTESIN”.
function sca = HTESIN(ip)
%%% Assigning a difference to change the range from -8 to 7.9375 to -7.9688
to +7.9688
ekle = xfix({xlSigned, 5, 5, xlRound, xlWrap}, 1/32);
%%% Representing the pi / 7.9688 ~ 0.394239 in 21 fractional binary digits
%%% (binary point)
mul = xfix({xlSigned, 21, 21, xlRound, xlWrap}, 0.394239);
%%%% Finding the output
sca = (ip + ekle)*mul;
%%%% Converting to signed binary, where number of bits = 20, binary point =
21
sca = xfix({xlSigned, 25, 21, xlRound, xlWrap}, sca);
Above code is a typical m function, where the commands, functions are a somewhat different. Here
“xfix” is used to convert a (floating point) decimal value to a binary representation of a specified
format. This way, in
xfix({xlSigned, 5, 5, xlRound, xlWrap}, 1/32)
xlSigned means that our numerical value has (negative and positive) sign and wish to express it with 5
bits (in total) and all 5 digits are to be reserved to binary (fractional) points. This is reasonable, since
21 22 23 24 25
1/ 32  0 0 0 0 1
Decimal
: 5 digits
(1.3)
Binary
Similar arrangement is valid for other declerations of “xfix”. Note that the next “xfix” command, that
is
mul = xfix({xlSigned, 21, 21, xlRound, xlWrap}, 0.394239);
requires some explanation. In (1.3) the conversion of the decimal numeral, 1/32 to 5 binary digits of
00001 was exact. But it is clear that the same will not happen for 0.394239. Lets assume that in this
particular conversion, we demand an accuracy up to six digits as written in 0.394239 or an error in
the order of 107 . Then a liitle execise proves that such an accuracy is possible with 21 binary
(fractional) points.
In summary, the function “HTESIN” accepts through the input argument, “ip”, the range of
8 to 7.9375 numeric values and converts them into a range of  to   with an accuray of six
digits and supplies the output via the parameter “sca”. Note that this function is labelled as “MCode”
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block in Fig. 1.2. Such facility is resorted to whenever a readily built Xilinx block of this functionality is
not available. The MCode block refers to the relevant function as shown in Fig. 1.4.
Fig. 1.4 The menu panel of MCode, where the related function is specified.
In Fig. 1.2, the yellow coloured “GateWay Out” are the interface blocks from Xilinx to Simulink.
Similarly, there is “GateWay In” block to connect a Simulink block to that of Xilinx.
Finally we should point out that model files containing Xilinx blocks need, the red coloured, marked
in sigma symbol, “System Generator” token for running. In Fig. 1.2, this is placed in the upper left
hand corner.
With the arrangements made, running the model file, we obtain the waveforms displayed in Fig. 1.5.
As seen from Fig. 1.5, the output of Mcode varies between  and   as required. In line with this
variation, the block “CORDIC SINCOS” provides cos and sine outputs as seen on the second and third
lines of Fig. 1.5.
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Fig. 1.5 The waveforms obtained after running the model file of Fig. 1.2.
2. Code generation and downloading into FPGA
Now we come to automatic generation of VHDL codes. Eventually these codes will be converted into
bits which will then be downloaded into the FPGA card so that we can get the same functionality in
real signal, i.e. the generation of sine and cos waveforms in this case.
There are two ways to achieve this. One is performing the actual implementation via ISE or Vivado
and observing the output by connecting a physical external scope to the FPGA card. The other is the
running Simulink model file and the code on Xilinx card simultaneously, but viewing and verifying the
signal outputs of the two cases on separate scopes in Simulink model file.
To implement the first option, we double click on the red coloured “System Generator” token to get
the menu panel given in Fig. 2.1. Here on the second line, the “Part” defines the type of Xilinx card to
be used, as seen it is set to “Virtex 5 xc5vtx50t-1ff1 136”. Target directory refers to the path where
the relevant files (including the VHDL code) is to be dumped, in the present case, this seems to be
“C:/Program Files/MATLAB/R2012a/work/SinGen/SinGenGen”. Finally we need to adjust the period
or the frequency of the waveforms upon the download into the FPGA card. For this, we click on the
button, “Clock” on the menu panel of Fig. 2.1, to arrive at the panel displayed in Fig. 2.2. Here we
determine the physical frequency on the FPGA card as follows
Physical frequency on FPGA card, f p 
Simulink system period (sec)
FPGA clock period (ns)
(2.1)
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Fig. 2.1 Menu panel of System Generator token.
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These notes are based on
1) MATLAB m files.
2) My own Lecture Notes.
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