ECE 4110–5110 Digital System Design
Lecture #28
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Agenda
1. Counters
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Announcements
1. HW#14 due Wed 11/27
2. Next: Quiz#3
Lecture #28
Page 1
Counters
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Counters in VHDL
- strong type casting in VHDL can make modeling counters difficult (at first glance)
- the reason for this is that the STANDARD and STD_LOGIC Packages do not define
"+", "-", or inequality operators for BIT_VECTOR or STD_LOGIC_VECTOR types
Lecture #28
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Counters
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Counters in VHDL
- there are a couple ways that we get around this
1) Use the STD_LOGIC_UNSIGNED Package
- this package defines "+" and "-" functions for STD_LOGIC_VECTOR
- we can use +1 just like normal
- the vector will wrap as suspected (1111 - 0000)
- one catch is that we can't assign to a Port
- we need to create an internal signal of STD_LOGIC_VECTOR for counting
- we then assign to the Port at the end
Lecture #28
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Counters
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Counters in VHDL using STD_LOGIC_UNSIGNED
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- call the package
entity counter is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Direction : in STD_LOGIC;
Count_Out : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
Lecture #28
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Counters
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Counters in VHDL using STD_LOGIC_UNSIGNED
architecture counter_arch of counter is
signal count_temp : std_logic_vector(3 downto 0);
begin
process (Clock, Reset)
begin
if (Reset = '0') then
count_temp <= "0000";
elsif (Clock='1' and Clock'event) then
if (Direction='0') then
count_temp <= count_temp + '1';
else
count_temp <= count_temp - '1';
end if;
end if;
end process;
Count_Out <= count_temp;
-- Notice internal signal
-- count_temp can be used on both LHS and RHS
-- assign to Port after the process
end counter_arch;
Lecture #28
Page 5
Counters
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Counters in VHDL
2) Use integers for the counter and then convert back to STD_LOGIC_VECTOR
- STD_LOGIC_ARITH is a Package that defines a conversion function
- the function is:
conv_std_logic_vector (ARG, SIZE)
- functions are defined for ARG = integer, unsigned, signed, STD_ULOGIC
- SIZE is the number of bits in the vector to convert to, given as an integer
- we need to keep track of the RANGE and Counter Overflow
Lecture #28
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Counters
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Counters in VHDL using STD_LOGIC_ARITH
use IEEE.STD_LOGIC_ARITH.ALL;
-- call the package
entity counter is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Direction : in STD_LOGIC;
Count_Out : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
Lecture #28
Page 7
Counters
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Counters in VHDL using STD_LOGIC_ARITH
architecture counter_arch of counter is
signal count_temp : integer range 0 to 15;
begin
process (Clock, Reset)
begin
if (Reset = '0') then
count_temp <= 0;
elsif (Clock='1' and Clock'event) then
if (count_temp = 15) then
count_temp <= 0;
else
count_temp <= count_temp + 1;
end if;
end if;
end process;
Count_Out <= conv_std_logic_vector (count_temp, 4);
-- Notice internal integer specified with Range
-- integer assignment doesn't requires quotes
-- we manually check for overflow
-- convert integer into a 4-bit STD_LOGIC_VECTOR
end counter_arch;
Lecture #28
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Counters
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Counters in VHDL
3) Use UNSIGNED data types #'s
- STD_LOGIC_ARITH also defines "+", "-", and equality for UNSIGNED types
- UNSIGNED is a Data type defined in STD_LOGIC_ARITH
- UNSIGNED is an array of STD_LOGIC
- An UNSIGNED type is the equivalent to a STD_LOGIC_VECTOR type
- the equality operators assume it is unsigned (as opposed to 2's comp SIGNED)
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Pro's and Cons
- using integers allows a higher level of abstraction and more functionality can be included
- easier to write unsynthesizable code or code that produces unwanted logic
- both are synthesizable when written correctly
Lecture #28
Page 9
Counters
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Ring Counters in VHDL
- to mimic the shift register behavior, we need access to the signal value before and after clock'event
- consider the following concurrent signal assignments:
architecture ….
begin
Q0 <= Q3;
Q1 <= Q0;
Q2 <= Q1;
Q3 <= Q2;
end architecture…
- since they are executed concurrently, it is equivalent to Q0=Q1=Q2=Q3, or a simple wire
Lecture #28
Page 10
Counters
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Ring Counters in VHDL
- since a process doesn't assign the signal values until it suspends, we can use this to model the
"before and after" behavior of a clock event.
process (Clock, Reset)
begin
if (Reset = ‘1') then
Q0<='1'; Q1<='0'; Q2<='0';
elsif (Clock'event and Clock='1') then
Q0<=Q3; Q1<=Q0; Q2<=Q1;
end if;
end process
Q3<='0';
Q3<=Q2;
- notice that the signals DO NOT appear in the sensitivity list. If they did the process would
continually execute and not be synthesized as a flip-flop structure
Lecture #28
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Counters
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Johnson Counters in VHDL
process (Clock, Reset)
begin
if (Reset = ‘1') then
Q0<='0';
Q1<='0';
elsif (Clock'event and Clock='1') then
Q0<=not Q3;
Q1<=Q0;
end if;
end process
Q2<='0';
Q3<='0';
Q2<=Q1;
Q3<=Q2;
Lecture #28
Page 12
Counters
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Linear Feedback Shift Register Counters in VHDL
process (Clock, Reset)
begin
if (Reset = ‘1') then
Q0<=‘1';
Q1<='0';
elsif (Clock'event and Clock='1') then
Q0<=Q3 xor Q2;
Q1<=Q0;
end if;
end process
Q2<='0';
Q3<='0';
Q2<=Q1;
Q3<=Q2;
Lecture #28
Page 13
Counters
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Multiple Processes
- we can now use State Machines to control the start/stop/load/reset of counters
- each are independent processes that interact with each other through signals
- a common task for a state machine is:
1) at a certain state, load and enable a counter
2) go to a state and wait until the counter reaches a certain value
3) when it reaches the certain value, disable the counter and continue to the next state
- since the counter runs off of a clock, we know how long it will count between the start and stop
Lecture #28
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