Digital Logic
CpE 412
BIST machine Implementation to
test SRAM using MARCH Y
algorithm
Krutik Patel
SID# 12322322
Instructor: Dr. Al-Assadi
11/12/2009
Purpose:
The purpose of the project is to design a BIST machine to test a SRAM of 32 words each of 8bits. The algorithm to be used for BIST is MARCH Y Algorithm. The design should be implemented in
verilog and simulated using Modelsim.
Description of MARCH Y algorithm:
March Y algorithm: ↕ (W0); ↑(R0,W1,R1); ↓(R1,W0,R0); ↕ (R0)
The basic notations used in algorithm are as follows:
 ↑: address 0 to n-1
 ↓: address n-1 to 0
 ↕: either way
 W0: Write 0 to the word
 W1: Write 1 to the word
 R0: Read a cell whose value should be 0
 R1: Read a cell whose value should be 1
BIST machine Specifiactions:
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The FSM should have a START state and be activated by an external signal RUN_BIST.
The design should have an input signal BIST_COMP feedback from the SRAM such that when
BIST_COMP=1 means there is a fault, 0 no fault. If BIST-COMP=1, the simulation should be
terminated and the FSM goes to END state. The address lines should read the failing address.
Output pins Read_En to be activated during the Read operation, and Write_En to be activated
during the write operation.
A Compare state follows each Read operation, during which NO Read or Write operations are
activated
An output signal called Error is activated when the FSM goes to END state corresponding to
failure.
The machine should produce the address and data output signals to feed the array.
You should provide a test fixture file to run the machine.
Use 500MHZ clock.
Design Methodology:
The BIST March Y algorithm is implemented using a Finite State Machine. The state diagram used to
design the BIST is shown below:
BIST_COMP=1
Idle
0000
Yes
No
Addr=31?
No
RUN_BIST=1
Yes
Yes
Addr=Addr+1
Error
Compare with 0
1110
Write 0
0001
Read 0
1101
Addr=Addr-1
No
Addr=0?
Insert Delay
1100
Yes
Read 0
0010
No
Yes
Error
Write 1
0100
Yes
No
Read 0
1010
No
Yes
Compare with 1
0110
Write 0
1001
Error
Compare with 1
1000
Error
Addr=31?
Addr=Addr-1
Compare with 0
1011
STOP
1111
Read 1
0101
No
Addr=0?
Error
Compare with 0
0011
Addr=Addr+1
No
No
Yes
Read 1
0111
Fig. FSM based implementation of the MARCH Y BIST algorithm
The finite state machine of the BIST March Y algorithm has 16 states, hence the state are represented
using 4 bits. The March Y algorithm representation is as below:
March Y algorithm: ↕ (W0); ↑(R0,W1,R1); ↓(R1,W0,R0); ↕ (R0)
The controller starts the BIST algorithm if the RUN_BIST signal is asserted, and otherwise it stays in
the idle state. If the RUN_BIST=1, then initially write-0 operation is performed on all the words
sequentially and then a read-0 is performed and compared with 0. If the result is correct then we write-1
on the same cell. If the comparison is incorrect then the machine goes to STOP state. Again, a read-1
operation is performed on the same cell and compared with-1. If the comparison result is correct, it
increases the address and if the comparison is incorrect, the machine goes to STOP state.
Similar to the above process, initially read operation takes place; this read is followed by a
comparison operation. And then write-0 is performed and again read and comparing with 0 takes place.
In the end, read 0 operation is performed and compared with 0. In all the above comparisons, if the
result s incorrect then the machine goes to idle state otherwise the machine goes to the corresponding
state.
The state transitions are shown in the above figure. After each comparison the machine goes to either
write state or to the STOP state if the FSM generates an error. The FSM is easily designed using case and
if statements in the verilog. In each state the corresponding Read enable(RE) and Write enable(WE)
signals are asserted.
If the machine is in STOP state the Finish is always asserted and if the error is found, the Error signal
is also asserted. At the end of the STOP state the program is exited using the $finish command.
The Verilog Implementation Of BIST March Y Algorithm:
The BIST is hierarchically implemented in verilog, with the top module as BIST and then BIST
controller and SRAM modules are the sub modules in the top BIST module.
Clock
BIST
RUN_BIST
Data
Addr
BIST Controller
8-bit 32 word
SRAM module
WE
RE
FINISH
Error
Fig. Module hierarchy in the verilog implementation of BIST March Y algorithm
Since this is simulation, error in SRAM will not appear as unless intentionally introduced, we will
have one SRAM module which has random bit sequences at some registers which will work as an error in
SRAM.
Since in the simulation using Modelsim, the error cannot be introduced during simulation hence a
separate SRAM module is designed which has an error. According to this the top module is modified to
invoke the SRAM file with error and without error.
In the following text, verilog codes for all the modules (BIST module, BIST controller, SRAM,
SRAM with Error and Test-bench) are given.
BIST Top Module:
module BIST(clk,Run_BIST,error);
input Run_BIST;
input clk;
wire Run_BIST;
wire clk;
output error;
wire
wire
wire
wire
wire
[7:0] data_read;
[7:0] data_write;
[4:0] address;
WE;
RE;
BIST_FSM
bist_controller(clk,Run_BIST,address,data_read,data_write,WE,RE,error);
SRAM sram_module(WE,RE,address,data_read,data_write);
endmodule
BIST Controller:
module BIST_FSM(clk,Run_BIST,address,data_read,data_write,WE,RE,error);
input clk,Run_BIST;
wire clk,Run_BIST;
input wire [7:0] data_read;
//inout[7:0] data;
output reg WE,RE;
output reg[4:0] address;
output reg error;
output reg [7:0] data_write;
reg[7:0] tempdata1;
reg[7:0] tempdata2;
`define
`define
`define
`define
`define
`define
`define
`define
`define
`define
`define
`define
`define
`define
`define
`define
S_idle 4'b0000
S1 4'b0001
S2 4'b0010
S3 4'b0011
S4 4'b0100
S5 4'b0101
S6 4'b0110
S7 4'b0111
S8 4'b1000
S9 4'b1001
S10 4'b1010
S11 4'b1011
S12 4'b1100
S13 4'b1101
S14 4'b1110
S_stop 4'b1111
reg [3:0] state;
initial
begin
state = 4'b0000;
address=5'b00000;
error=0;
end
always@(posedge(clk),Run_BIST)
begin
if(Run_BIST==0)
state=`S_idle;
else
begin
case(state)
`S_idle:
begin
if(!Run_BIST)
begin
address=5'b00000;
error=0;
state = `S_idle;
end
else
begin
address=5'b00000;
error=0;
state = `S1;
end
end
`S1:
//write 0
begin
WE<=1;
RE<=0;
#20
for(address=5'b00000;address<=5'b11111;address=address+1)
// begin
data_write=8'b00000000;
#10
address=address+1;
if(address>=5'b11111)
begin
state=`S2;
end
else
//
state=`S1;
end
end
`S2:
//Read 0
begin
RE<=1;
WE<=0;
#20
tempdata1=data_read;
state=`S3;
end
`S3:
//compare with 0
begin
RE<=0;
WE<=0;
if(tempdata1==8'b00000000)
state<=`S4;
else
begin
error=1;
state<=`S_stop;
end
end
`S4:
//Write 1
begin
RE<=0;
WE<=1;
#20
data_write=8'b11111111;
state=`S5;
end
`S5:
//Read 1
begin
RE<=1;
WE<=0;
#20
tempdata2=data_read;
#20
state=`S6;
end
`S6:
//compare with 1
begin
RE<=0;
WE<=0;
if(tempdata2==8'b11111111)
begin
if(address==0)
state=`S7;
else
begin
address=address-1;
state=`S2;
end
end
else
begin
error=1;
state<=`S_stop;
end
end
`S7:
//Read 1
begin
RE<=1;
WE<=0;
#20
tempdata1=data_read;
state=`S8;
end
`S8:
//Compare with 1
begin
RE<=0;
WE<=0;
if(tempdata1==8'b11111111)
begin
state=`S9;
end
else
begin
error=1;
state<=`S_stop;
end
end
`S9:
//Write 0
begin
RE<=0;
WE<=1;
#20
data_write=8'b00000000;
state=`S10;
end
`S10:
//Read 0
begin
RE<=1;
WE<=0;
#20
tempdata1=data_read;
state=`S11;
end
`S11:
//Compare with 0
begin
if(tempdata1==8'b00000000)
begin
if(address>=31)
state=`S12;
else
begin
address=address+1;
state=`S7;
end
end
else
begin
error=1;
state<=`S_stop;
end
end
`S12:
//Delay 100 clk cycle
begin
#100
state=`S13;
end
`S13:
//Read 0
begin
RE<=1;
WE<=0;
#20
tempdata1=data_read;
state=`S14;
end
`S14:
//compare with 0
begin
if(tempdata1==8'b00000000)
begin
if(address==0)
begin
state=`S_stop;
end
else
begin
address=address-1;
state=`S13;
end
end
else
begin
error=1;
state<=`S_stop;
end
end
`S_stop:
//Stop state
begin
end
endcase
end
end
endmodule
SRAM Module without Error:
module SRAM(WE,RE,address,data_read,data_write);
//Inputs
input WE;
input RE;
input [7:0] data_write;
input [4:0] address;
//Inputs as wires
wire WE;
wire RE;
wire [4:0] address;
wire [7:0] data_write;
output reg [7:0] data_read;
reg [7:0] RAM[0:31];
//RAM of 32 bytes
always @(WE or RE or address or data_write)
begin
if(WE==1 && RE==0)
begin
RAM[address]=data_write;
end
if(WE==0 && RE==1)
begin
data_read=RAM[address];
end
end
endmodule
SRAM Module with Error:
module SRAM_error(WE,RE,address,data_read,data_write);
//
//Inputs
input WE;
input RE;
input [7:0] data_write;
input [4:0] address;
//Inputs as wires
wire WE;
wire RE;
wire [4:0] address;
wire [7:0] data_write;
output reg [7:0] data_read;
reg [7:0] RAM[0:31];
//RAM of 32 bytes
always @(WE or RE or address or data_write)
begin
if(WE==1 && RE==0)
//check
begin
if(address==15)
//error injected at location 15
RAM[address]=8'b10101010;
else
RAM[address]=data_write;
end
if(WE==0 && RE==1)
begin
if(address==25) //error injected at location 25
data_read=8'b11111010;
else
data_read= RAM[address];
end
end
endmodule
Test Bench:
module BIST_tb();
reg clk;
reg Run_BIST;
wire error;
initial
begin
clk<=0;
#5 Run_BIST=1;
#200 Run_BIST=0;
#250 Run_BIST=1;
end
always
begin
forever #5 clk=~clk;
end
BIST BIST_tb(clk,Run_BIST,error);
endmodule
Simulation Results by invoking SRAM module without error:
The BIST is first run by invoking SRAM without error and later it is tested with an SRAM module with
error. The following snap shots show the output waveforms over the timeline.
Simulation results after invoking SRAM with error:
Conclusion:
In this project, 32 word SRAM is tested using BIST March Y algorithm. The design is done in
verilog and the simulation results are tested using Modelsim. Initially the BIST is made to run on correct
SRAM module which resulted in Error =0 signal at the end of test. Later, the BIST was made to run on an
SRAM module with error. For this, signal generated at the end is Error = 1, which shows that error in the
SRAM was correctly detected as correct address where error was located. In both the cases the BIST
machine is functioning properly. The verilog code and the simulation results are given.