Analysis on Performance Controllability
under Process Variability:
A Step Towards Grid-Based Analog
Circuit Optimizers
Seobin Jung, Sangho Youn, Jaeha Kim
Mixed-Signal IC and System Group
Seoul National University, Korea
July/2011
1
Status of Analog Circuit Optimization

Absence of systematic design flow


One of reasons is long execution time



Most analog circuit designers do not use the optimizer
Finding a solution in a continuous, high-dimensional design
space
Most optimizers employ numerical techniques
(e.g., simulated annealing, convex optimization)
Challenge

Process variability and device uncertainty worsen the situation
by accompanying complex physical phenomena
2
Common Issues with Continuous Optimizers

Continuous optimizers can waste computational efforts


When refining the solution to the irrelevant precision
When making unsuccessful escape attempts to search for
other local optimas
The optimum is
32.4974384!
Thanks. I’ll just use 32;
that’s close enough
3
Leveraging Process Variability


In presence of variation and uncertainty, designers have
limited control over the precision in performance metrics
Two design points must be sufficiently different to be
distinguished by their performance metrics
4
How Much Different Should They Be?

Shannon’s channel capacity theorem tells us how much
signal swing (DX) is required to convey N-bit of information
in presence of noise

For sending 1-bit of information (distinguishing two points):
5
Minimum Design Change Required (DDmin)

We can consider a circuit as an effective channel medium
that yields a certain performance with finite precision in
response to the design parameter values

To tell two design points apart by their performance (P):
6
DDmin in Ring Oscillator

Performance P = oscillation period

Design parameter D = Wload

Fixed value : Wring = 20λ
7
DDmin in Differential Amplifier

Performance P = DC gain

Design Parameter D = W

Fixed values : R = 10kΩ, Wtail = 20λ
8
DDmin in Real Circuit Examples

To our surprise, the minimum change required is > 20%!

This motivates a coarse grid-based optimization approach

With 20% log-scale grid, 1:10 range requires only 13 points!
9
Potentials for Grid-Based Optimizers
Unlike continuous ones, coverage can be defined
Avoids evaluating similar design points during local search
Knows which space is less explored during global search


Performance P = TP [psec]

90
Wp
80
Wn
The optimum is 32
70
Thanks! It’s
reasonable
60
50
0
30
60
90
Design Parameter D = Wp [λ]
10
Challenges for Grid-Based Optimizers

Defining the discrete grid for the design space


Navigating the grid for local search



For Cartesian grids, the number of points in the space grows
exponentially with the dimension N
Compare the current design with the neighbors and update
But the number of neighbor points grows exponentially
Making comparisons between two design points


Must be done in statistically sense
Involves costly Monte-Carlo simulations
11
Conclusion

In presence of process variability and uncertainty, gridbased analog circuit optimizer may be a viable approach


The continuous design space can be transformed into the
discrete design space
For a few common circuits, the minimum grid spacing required
was quite coarse (~20%)
12