Beyond Transistor Scaling:
New Devices for Ultra‐Low‐Energy
Information Processing
Prof. Tsu‐Jae King Liu
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley, CA 94720
April 28, 2009
6th US‐Korea Nano Forum (Las Vegas, NV, USA)
The CMOS Power Crisis
The CMOS Power Crisis
• Due to off‐state leakage, VTH cannot be scaled down
aggressively. Thus, the supply voltage (VDD) has not been
scaled down in proportion to the MOSFET channel length.
Æ CMOS power density has increased with transistor scaling!
VDD
VDD – VTH
VTH
Power Density with CMOS Scaling
Power Density (W/cm2)
CMOS Voltage Scaling
1E+03
Active Power Density
1E+02
1E+01
1E+00
1E-01
1E-02
1E-03
1E-04
Passive Power Density
1E-05
0.01
0.1
1
Gate Length (μm)
Source: P. Packan (Intel),
2007 IEDM Short Course
Source: B. Meyerson (IBM)
Semico Conf., January 2004
3
Parallelism
100
uP‐Chip Power DensityTrend
1000
100
Sun’s Surface
Rocket Nozzle
Nuclear Reactor
80
Norm alized Energy/op
Power Density (W/cm2)
10000
Core 2
8086 Hot Plate
10 4004
P6
80088085 386
Pentium® proc
286
486
8080
1
1970
1980
1990
2000
2010
Year
Source: S. Borkar (Intel)
60
Operate at a lower
energy point
40
20
Run in parallel to recoup
performance
0 0
10
1
10
2
10
10
1/throughput (ps/op)
3
10
• Parallelism is the main technique to improve system
performance under a power budget.
4
4
Minimizing Operation Energy
CMOS Energy per Operation
CMOS Energy vs. Delay
Etotal
Eleakage
Edynamic
Normalized Energy/op
100
80
60
40
20
0 1
10
10
2
3
10
10
1/throughput (ps/op)
4
10
5
• Edynamic + Eleakage = αLdCVdd2 + LdIOFFVddtdelay
•
tdelay = LdCVdd/(2ION)
Æ CMOS has a fundamental lower limit in energy per operation,
due to subthreshold leakage.
5
The Need for a New Switch
CMOS Energy vs. Delay
(normalized)
Today:
Parallelism
lowers E/op
Future: Parallelism doesn’t help
Delay
• When each core operates at the minimum energy,
increasing performance requires more power.
6
New Switching Devices
MOSFET Subthreshold Swing
MOSFET
Structure:
Electron Energy Band Profile
log ID
ION
Gate
Source
Drain
increasing E
n(E)∝exp(‐E/kT)
S
IOFF
Substrate
distance
VDD
VG
 qV 
• In the subthreshold region (VGS < VTH), I D ∝ exp  GS 
 nkT 
Æ S ≥ 60mV/dec at room temperature
• S must be reduced in order to achieve the desired ION/IOFF
with smaller VDD
8
Tunnel FET (TFET)
Si TFET I‐V Characteristics
Structure:
Gate
p+ Source
n+ Drain
Substrate
Energy‐band
Diagrams:
OFF STATE:
EC
Drain Current (A/µm)
W. Y. Choi et al. (Seoul Nat’l U. & UC Berkeley)
IEEE‐EDL vol. 28, pp. 743‐745, 2007
VD =1 V
10-5
VD = 0.1 V
10-6
SS = 52.8 mV/dec
T = 300 K
LG = 70 nm
tox = 2 nm
tSOI = 70 nm
10-7
10-8
10-9
W = 10 µm
10-10
EV
0.0
0.2
0.4
0.6
0.8
1.0
Gate Voltage (V)
bandgap (Eg)
EC
ON STATE:
EV
tunneling current
I D = aξ exp( −b / ξ )
ξ=
VGS + Vtunnel
κTox
a ∝ A m * / Eg
b ∝ m * / E g3
9
Energy‐Performance Comparison
H. Kam et al. (UCB, Stanford U.), 2008 IEDM
1.E-15
]
J
[ 1.E-16
y
g
r
e
n
E1.E-17
• Si TFETs appear
promising for
sub‐1GHz
applications
CMOS
TFET
1.E-18
1.E-02
1.E-01
1.E+00
Performance (GHz)
1.E+01
30-stage 65nm CMOS inverter chain
(transition probability=0.01, capacitance per stage=2.4fF)
10
TFET Technology Challenges
• Increased ION to expand range of applications
– Advanced semiconductor materials to achieve smaller
effective Eg
• VTH control
• TFET‐based integrated‐circuit design
11
MOSFET‐Inspired Relay
F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD
OFF‐state
|VGB| < VTH
ON‐state
|VGB| ≥ VTH
• The mechanical gate is electrostatically actuated by a voltage applied
between the gate and body electrode, to bring the channel into
Plan‐View Micrograph
contact with the source and drain electrodes.
Measured I‐V
V = 0.5V
• Ideal switching behavior:
1.E-2
IDS (A)
DS
– Zero off‐state leakage
– Abrupt turn‐on
→ low VTH (and VDD) possible!
VBody=0V
Gate:
W =2µm
L=20µm
H =200nm
actuation gap = 400nm
1.E-6
1.E-10
1.E-14
0
5
10
VGB(V)
15
20
L
12
Relay Scaling
F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD
• Scaling has similar benefits for relays as for MOSFETs.
Pull‐in Voltage with Beam Scaling
• Measured pull‐in voltages
scale linearly
{W,L,tgap} = {90nm,2.3um,10nm}
Æ Vpi = 200mV
• Mechanical delay also scales
linearly (~10ns @ 90nm)
13
Relay‐Based Circuit Design
F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD
• Relays have small RC delay but large mechanical delay
Æ Complete all logic in a single complex (pass transistor) gate
Example of
CMOS to Relay
Logic Mapping:
Energy vs. Delay
Comparison:
(32‐bit adders,
90nm technology)
CMOS
fundamental limit:
10x reduction
• A relay adder can be
~10x more energy
efficient at the same
delay as a CMOS adder.
14
Relay Technology Challenges
• Surface adhesion force
• Mechanical contact resistance
• Reliability
Relay I-V Characteristic
IDS hysteresis due
to surface force
Vrel Vpi
VGS
15
Summary
Summary
• Due to subthreshold leakage, CMOS technology has a
fundamental limit in energy efficiency.
• New switching devices with steeper switching
behavior are needed to achieve lower energy per
operation.
– Examples: tunnel FET, relay
– Note: Such devices may have very different characteristics
than the MOSFET. Thus, they will require new circuit and
system architectures to fully realize their potential energy‐
efficiency (and hence performance) benefits.
17
Acknowledgements
• Collaborators:
– Faculty: Elad Alon (UCB), Dejan Markovic (UCLA), Vladimir Stojanovic (MIT)
– Students: Hei Kam, Fred Chen (MIT)
• Research funding:
» DARPA STEEP Program
» DARPA/MARCO Focus Center Research Program:
• Center for Circuits and Systems Solutions (C2S2)
• Center for Materials, Structures, and Devices (MSD)
• UC Berkeley Microfabrication Laboratory
18