Multiple Gate CMOS and
Beyond
Dept. of EECS, KAIST
Yang-Kyu Choi
Outline
1. Ultimate Scaling of MOSFETs
- 3nm Nanowire FET
- 8nm Non-Volatile Memory Device
2. Multiple Functions of MOSFETs
3. Summary
2
CMOS Evolution Scenario
G
S
G
D
S
D
Fin
Fin
Fin
Double gate
Ω-gate
All-around
Buried Oxide
Bulk-single gate
SOI single gate
No report for
Sub-50nm
LG=4nm
NEC
IEDM 2003
LG=8nm
IBM
IEDM 2003
LG=10nm
AMD/Berkeley
IEDM 2003
3
LG=10nm
LETI
VLSI 2005
This
Work
ITRS Roadmap
2006
LG (nm)
28
Bulk SG 1.1
EOT
(nm)
DG
Bulk SG 0.15
Isd,leak
(µA/µm)
DG
Bulk SG 1130
Id,sat
(mA/mm)
DG
2008 2011 2013 2020
5
22
16
13
0.9
0.5
0.6
0.8
0.5
0.2
0.32
0.1 0.11 0.11
1570 2490
1899 2220 2981
Source: ITRS 2005 roadmap
Solution exist
Solution being pursued
No known solution
4
All-Around Gate (AAG) FinFET
• AAG-FinFET
Source
– LG=3nm
– WFin=3nm
– EOT(HfO2)=1.2nm
Gate
Gate
Drain
• To fabricate sub-5nm silicon transistor,
All-Around Gate (AAG) FinFET was proposed.
5
Process Flow of AAG-FinFET
•
•
•
•
•
•
•
•
•
•
•
(100) SOI wafer
Silicon body thinning
Fin patterning (dual-resist)
Sacrificial oxidation
Gate dielectric (HfO2)
Poly-silicon deposition
Gate patterning (dual-resist)
Spacer formation
Source/Drain implantation
Spike annealing (1000oC)
Forming gas annealing
(450oC)
6
3nm AAG FinFET: Silicon-Fin
Silicon
fin
HfO2
S
Source
Gate
Gate
20nm
Poly-si
3nm
Drain
Buried oxide
5nm
3nm
Y.-K. Choi et al., VLSI, 2006
7
5nm
3nm AAG FinFET: Gate
5nm
Poly-si
HfO2
IFO
5nm
5nm
Source
Gate
Gate
Poly-si
Gate
Si
Poly-si
3nm
HfO2
Drain
IFO
5nm
Silicon fin
8
Si
Drain Current [A/µm]
Simulated
Measured
VD=1.0V
140
-4
10
VD=0.2V
-5
10
DIBL=230mV/V
SS=208 mV/dec
HfO2 =1.4nm
LG=3nm
WFin=3nm
-6
10
-7
10
-1.0
-0.6
-0.2
0.2
Gate Voltage [V]
0.6
120
100
80
60
40
20
0
1.0
Transconductance [µS/µm]
160
-3
10
Drain Current [µA/µm]
I-V of 3nm AAG FinFET
350
HfO2 =1.4nm
LG=3nm
250 W =3nm
Fin
200
300
0.4V
150
VG=0.2V
100
50
0
0.0
0.2
0.4
0.6
0.8
Drain Voltage [V]
• Large DIBL and SS due to thick EOT
– ITRS requirement: 0.5nm EOT for DG
9
0.6V
1.0
Fundamental Limit of Scaling
• Device scaling limit (Operating at 300K)
– Heisenberg’s uncertainty principle
– Shannon - von Neumann - Landauer (SNL) expression
SCALING
LIMIT
1.5
xmin
h
h
h
=
=
=
∆p
2mc Ebit
2mc k B T ln 2
= 1.5nm (T = 300 K )
Fabricated 3nm all-around gate
FinFET is approaching to this
fundamental limit.
10
Nanowire Structure
• Silicon nanowire non-volatile memory
structure for ultimate scaling
Poly-silicon
Blocking oxide
Nitride trap layer
Tunneling oxide
Si
Buried Oxide
8nm Non-Volatile Memory
Omega-shape gate
ONO-structure
11
8nm Si Nanowire NVM
Poly-silicon Gate
O
S
N
O
S
Silicon
Nanowire
(7/10nm)
etrap
sites
BOX
Gate
Tunneling oxide
Nitride trap layer
Blocking oxide
10nm
Poly-silicon
Y.-K. Choi et al., VLSI, 2007
12
8nm Si Nanowire NVM
8nm
Gate
7/10nm
3.8nm
6.4nm
5.1nm
Oxide
Nitride
Silicon
TONO=15nm > LG=8nm
5.1nm
6.4nm
3.8nm
13
8nm Silicon Nanowire NVM with ONO
-4
-4
-5
1x10
1x10
Drain Current [A/µm]
Drain Current [A/µm]
1x10
ONO=3.8/6.4/5.1nm
tProgram=80µsec
1x10
-6
10
-7
10
8V 10V
Initial
VPG=12V
-8
10
LG=8nm
W NW=7nm
HNW=10.5nm
-9
10
-10
10
-4
-3
-2
-1
-5
0
1
Gate Voltage [V]
2
ONO=3.8/6.4/5.1nm
tErase=80µsec
-6
10
-7
10
VER=-12V
-10 -8V
-8
10
LG=8nm
W NW=7nm
HNW=10.5nm
-9
10
-10
3
10
-3
Initial
-2
-1
0
1
Gate Voltage [V]
• 8nm LG with 7nm WNW using ONO-structure
- Acceptable electrical performance by omega-gate
- Wide hysteresis shows the probability of multi-level NVM
14
2
3
8nm Si Nanowire Memory
4.0
3.0
L =8nm
3.0 G
WNW=7nm
2.5
VPG=12V
2.5
2.0
VPG=10V
1.5
1.0
VPG=8V
0.5
0.0
∆VT [V]
∆VT [V]
3.5 ONO=3.8/6.4/5.1nm
-8
-7
-6
-5
-4
10 10 10 10 10 10
-3
-2
-1
0
LG=8nm
WNW=7nm
HNW=10nm
2.0
1.5
VER=-8V
1.0
-10V
0.5
1
10 10 10 10
0.0
VER=-12V
-8
-7
-6
-5
-4
10 10 10 10 10
Program Time [sec]
-3
-2
Erase Time [sec]
• 8nm NVM: VT window = 2V
– Program @ +12V/1msec, Erase @-12V/1msec
15
-1
0
10 10 10 10 10
1
Scaling Limit in NVM
• Ultimately scaled NVM
• Nanowire + SONOS
TO/N/O=15nm > Lg=8nm
Scaling
Limit !
Y.-K. Choi et. al., VLSI 2007
• Close to end-point of semiconductor memory
16
Where to Go?
Do
wn
MultiFunctioning
Multi-Bit
Sc
al
in
g
We are here
17
This
Work !
Example of Fusion Memory
(System in Package)
DRAM
NVM
SRAM
..
.
Wafer level
fusion !!
• Increased volume
• Complexity in assembly
• Chip-to-chip interference
18
Principal of SONOS Flash Memory
control oxide
nitride
⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ tunnel oxide
S
⊖⊖⊖⊖
D
⊕⊕⊕⊕
⊕⊕
⊕⊕
S⊕ ⊕
⊕⊕
D
Substrate
Substrate
< program >
< erase >
Gate
Gate
⊖⊖⊖⊖⊖⊖⊖⊖
S
Gate
D
⊕⊕⊕⊕
S⊕ ⊕ ⊕ ⊕
Substrate
Substrate
< read ‘0’ >
< read ‘1’ >
19
Drain current
Gate
‘1’
‘0’
Gate voltage
D
Features of flash
• High density ↑
• Non-volatile ↑
• Speed ↑
Principal of Capacitorless DRAM
Gate
S
⊖
⊖
⊕
⊕⊕⊕⊕
Buried oxide
D
S
⊕⊕D
⊕⊕⊕
Buried oxide
Substrate
Substrate
< program >
< erase >
Gate
Gate
⊕⊕⊕⊕
Buried oxide
D
S
Buried oxide
Substrate
Substrate
< read ‘1’ >
< read ‘0’ >
Drain current
S
Gate
D
‘1’
‘0’
Time
20
Source : IEEE spectrum Dec. 2008
Features of 1T-DRAM
• High speed ↑
• 2x denser than 1T/1C
DRAM ↑
• 5x denser than SRAM ↑
• Volatile ↓
Basis of URAM Operation (1)
Gate voltage
flash program
capacitorless
1T-DRAM
program
capacitorless
1T-DRAM
erase
Drain voltage
Flash Memory Mode
- Program : FN tunneling/HEI
- Erase : FN tunneling/HHI
(High gate & drain voltage)
Capacitorless 1T-DRAM Mode
- Program : Impact ionization
- Erase : Forward junction
current
(Low gate & drain voltage)
Disturbance Issue
flash erase
- Periodical refresh
21
Multi-Function (URAM) Operation
Flash Memory
electron
DRAM
hole
Gate
Oxide
Nitride
Oxide
Drain
드레인
Source
Quantum Barrier
22
Family of URAM
S. Okonin et.al.,
SOI conf., 2001
R. Ranica et.al.,
VLSI symp., 2004
23
Process Flow (1)
SOC Substrate
SOI Substrate
Si
Si
Buried oxide
Si:C
Si substrate
Si substrate
• Initial SOI substrate
• Initial bulk substrate
• Si:C epitaxial growth
• Si epitaxial growth
SON Substrate
SOG Substrate
Si
Si
n-well
Si:Ge
Si substrate
Si substrate
• Initial bulk substrate
• Initial bulk substrate
• Buried n-well implantation • Si:Ge epitaxial growth
• p-body implantation
• Si epitaxial growth
24
Process Flow (2)
Puntch stop implantation
fin
Active fin lithography
Hole barrier layer
Si substrate
Fin patterning
HDP oxide deposition
fin
SiO2
Photoresist trimming
SiO2
Hole barrier layer
Si substrate
Oxide CMP
Oxide recess formation
25
Process Flow (3)
Gate
O/N/O formation
fin
Poly-Si deposition
SiO2
SiO2
Hole barrier layer
Si substrate
Gate
S/D implantation
fin
SiO2
Gate patterning
SiO2
Hole barrier layer
Si substrate
Activation
Forming gas annealing
26
URAM on SOI
27
Cross sectional view of URAMs
URAM
on SOI
URAM
on SiC
URAM
on
Buried N-well
28
URAM
On SiGe
Drain current, V
IDD (A)
ID-VG Characteristics
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
VD = 1V
-1.0
SOI
SOC
SOG
SON
-0.5
0.0
0.5
1.0
1.5
2.0
Gate voltage, VG (V)
• Superior device performances are result of the 3D nature.
29
ID-VD Characteristics (Kink)
SOI
SOC
SON
SOG
30
P/E in NVM
Program
Erase
• P/E sensing windows are acceptable.
31
Reliability in NVM
Retention
Endurance
• Data retention and endurance are acceptable.
32
Capacitorless 1T-DRAM in SOI
PD URAM
0.8V
0.7V
0.6V
80
Source current, IS (µA)
FD URAM
70
60
∆Is=20µΑ
50
SOI URAM
40 ∆Is=7µΑ
30
20
80msec
Conventional
FinFET SONOS
10
0
0
50
100
150
200
Time, t (msec)
< Measurement Results >
< Potential Profile >
• Proposed SOI URAM exhibits wider sensing current window.
Y.-K. Choi et. al., IEDM 2007
33
Capacitorless 1T-DRAM in SON
bulk MOSFET
Y.-K. Choi et. al., VLSI 2008
32
Sensing current, IS (µA)
28
VSUB=0.5V
24
20
SON URAM
16
12
∆IS=4µA
8
4
∆IS=7µA
VSUB=0.3V
VSUB=0V
0
1
2
3
Time, t (msec)
4
5
< Measurement Results >
< Excess Hole Concentration >
• Capacitorless 1T-DRAM works in SON floating substrate.
34
Capacitorless 1T-DRAM at SOC
Y.-K. Choi et. al., VLSI 2008
SON URAM
SOC URAM
Source current, IS (µA)
28
24
20
∆IS=11µA
16 V =0.3V
SUB
12
∆IS=7µA
8
VSUB=0V
4
0
0
1
2
3
4
Time, t (msec)
5
< Measurement Results >
< Excess Hole Concentration >
• Capacitorless 1T-DRAM works in SOC floating substrate.
35
6
Summary
IT only
NT only
N
IT
⊗
T
• 3nm MOSFET and 8nm non-volatile memory device were
demonstrated.
→ Close to scaling limit.
• Multi-function URAM was demonstrated.
→ Continuously increased density
36
Built-in Potential for Buried n-well
SIMS profile of the buried n-well
Simulation Result of Energy Band
0.9 eV
• Built-in potential confines excess holes.
37
Band-Offset for Si:C & Si:Ge (2)
C-V for Band Engineered Substrate
Energy Band Diagram
Normalized capacitance
1.0
0.8
0.6
0.4
Si/Si0.7Ge0.3/Si
Si/Si0.94C0.06/Si
∆EV= 200 meV
∆EV=-180 meV
0.2
0.0
-3.0
-2.5
-2.0 -1.5 -1.0 -0.5
Gate voltage, VG (V)
0.0
0.5
• Double slopes appear in weak accumulation region.
38
Scaling Issue
(Why capacitorless DRAM?)
µ-processor
Cache memory
SRAM (32F2)
Cache portion
50% in 2006
83% in 2008 90% in 2011
Is this memory or µ-processor ?
• Cell capacitance in DRAM > 25fF (non-scalable)
Cell area (~8F2) is continuously reduced.
• Capacitorless DRAM is a promising candidate for
embedded memory.
39
Soft-Program Issue
Gate voltage
flash program
capacitorless
1T-DRAM
program
capacitorless
1T-DRAM
erase
Disturbance Issue
- Periodical refresh
Drain voltage
1T-DRAM mode
Set VT of all cells to 0.2V by
adjustment of trapped charges
Capacitorless
1T-DRAM operation
Verification
VT=0.2V?
yes
refresh
Initialization :
no
40
GIDL Program Method
2
Gate voltage
1
0 Drain voltage
-1
100 nsec
-2
GIDL
Threshold voltage, VT (V)
Source current, IS (µA)
Bias (V)
Impact ionization
100 nsec
40
20
12µA
0
0
200
400
600
Time, t (µsec)
800
0.6
0.5
Impact ionization
program
VG=1, VD=2V
GIDL
program
VG=-2V, VD=2V
0.4
0.3
10
1000
< 1T-DRAM Measurement >
0
10
1
2
3
4
10
10
10
Stress time, t (sec)
10
5
< Soft-program test >
• GIDL program method mitigates soft-programming.
[J.-W. Han et. al., EDL, Apr. 2009]
41
G-to-S/D Underlap Structure
Gate
S
⊖
⊕
⊖
D
Buried oxide
50nm
Substrate
G-to-S/D Overlap
junction
Gate
S
⊖
⊖
⊕
Buried oxide
D
Gate
D
S
Buried oxide
Substrate
G-to-S/D Underlap
[J.-W. Han et. al., EDL, May 2009]
42
3
2 VG
1
0 V
D
-1
-2
0.45
50 nsec
50 nsec
G-to-S/D underlap
50
40
30
8 µA
G-to-S/D overlap
20
10
0
0.0
11 µA
Threshold voltage, VT (V)
Source current, IS (µA/µm) Bias (V)
G-to-S/D Underlap Structure
0.40
1.0
G-to-S/D overlap
0.35
0.30
0.25
0.20
0.15
0.5
Time, t (msec)
Stress bais : VG=1V, VD=2.5V
G-to-S/D underlap
0
10
1
2
3
10
10
10
Stress time, t (sec)
10
4
10
< Soft-program test >
< 1T-DRAM Measurement >
• G-to-S/D underlap structure mitigates soft-programming.
[J.-W. Han et. al., EDL, May 2009]
43
5
Issue and Solution of G-to-S/D
Underlap Device Structure
S
Buried oxide
SiO2
D
Substrate
SiO2 Spacer
Gate
S
Buried oxide
Substrate
High-k Spacer
High-k
D
overlap with
SiO2 spacer
100
Source current (µA/µm)
Gate
120
80
∆IS=11µA
60
underlap with
HfO2 spacer
40
20
∆IS,SiO2=20µA
0
underlap with
-20 SiO2 spacer
-40
10
∆IS,HfO2=55µA
hold
read
20
erase
30
40
Time (nsec)
hold
50
read
60
< Simulation Results >
• High-k spacer countervails the parasitic series resistance
[J.-W. Han et. al., EDL, May 2009]
of the G-to-S/D underlap.
44