Ultimately Scaled CMOS: DG FinFETs?
Jerry G. Fossum
SOI Group
Department of Electrical and Computer Engineering
University of Florida
Gainesville, FL 32611-6130
J. G. Fossum / 1
Outline
❋ Introduction - CMOS Scaling
❋ Thin-BOX FD/SOI MOSFETs
❋ Pragmatic Nanoscale FinFETs
❋ Conclusions
J. G. Fossum / 2
Projected HP CMOS Gate-Length Scaling*
[Intel: bulk-Si MOSFETs]
7nm
[6nm in 2020!]
*2003 SIA ITRS
J. G. Fossum / 3
Contemporary Bulk-Silicon MOSFET
NB(x,y)
Substrate/Well Body
Has been scaled a la Moore’s (and now, “More than Moore”) Law, but with
increasingly complex boosters and body/channel doping density N B, which can
no longer (i.e., for Lg < ~30nm) be adequately controlled.
J. G. Fossum / 4
Continued Scaling to Lg < 10nm: Undoped UTBs/Channels
(n)FinFET on SOI?
FD/SOI (n)MOSFET w/ thin BOX and GP?
Gate
Gf
n+
STI
p-
n+
BOX
p+
STI
GP
Si Substrate
NO.
n+
Source
n+
Drain
Complex processing/layout.
BOX
Selective GPs, w/ biasing.
YES.
Tuned dual-metal gate work functions.
Quasi-planar.
High inherent Vt:
Conventional processing, w/o NB.
V t ( long ) = ( 1 + r )φ c ∼ 0.6V .
Two gates: good SCE control.
Can be pragmatic.
J. G. Fossum / 5
2-D Numerical Simulations: Projected Scaling Limits
Taurus-predicted LP and HP scaling limits (Leff, which, with G-S/D underlap, can
be 5-10nm longer than Lg), defined by tSi = 5nm, for thin-BOX/GP nMOSFETs
and DG nFinFETs. The devices have been designed for Ioff ~ 10pA/µm and
~100nA/µm for LP and HP applications, respectively, with DIBL ≤ 100mV/V. The
18nm limit for the HP thin-BOX/GP device with VGP is questionable due to the
very large ∆ΦGf (gate work-function tuning below midgap) needed; the scaling
limit of 25nm without VGP is more realistic.
LP
Thin-BOX/GP Thin-BOX/GP
DG FinFET
w/ VGP
w/o VGP
Leff (nm)
28
18
25/15
∆ΦGf (mV)
0
450
0/-450
HP
Thin-BOX/GP Thin-BOX/GP
w/ VGP
w/o VGP
DG FinFET
Leff (nm)
25
18?
15
∆ΦGf (mV)
0
850
0
Pragmatic FinFET-CMOS can be scaled to the end of the SIA ITRS.
J. G. Fossum / 6
Nanoscale Pragmatic-FinFET CMOS
❋ On SOI (no isolation, S-D leakage complexities).
❋ Undoped fin-UTB/channel (no RDF effects).
❋ DG, not TG (a top gate is virtually ineffective).
❋ One ~midgap metal gate (for nMOS and pMOS).
❋ No channel strain (mobilities are high without it).
❋ No high-k dielectric (relatively thick SiON is OK).
❋ G-S/D underlap (L eff(weak) > Lg, L eff(strong) ≅ L g).
❋ S/D processing for V t control (and underlap).
J. G. Fossum / 7
The optimal number of gates is 2!
Davinci (3-D): Undoped Leff = 28nm TG fin size for SCE control; tox = 1.1nm
2.0
S = 80mV
DIBL = 100mV/V
hSi/Leff
1.5
1.0
hSi = wSi = Leff
DG
hSi = wSi (⇒ easier fin)
1/5 ~ hSi(FD)/Leff
0.5
Design
Space
FD/SOI
0.0
0.0
0.5
1.0
1.5
2.0
wSi/Leff
wSi(DG)/Leff ~ 1/2
Two gates (DG) give good control of electrostatics (i.e., SCEs) with thicker
UTB than that needed for one-gate (FD/SOI) device.
J. G. Fossum / 8
A third (top) gate is not very beneficial ...
Davinci (w/o QM): Leff = 25nm, wSi = 13nm, tox = 1.2nm
100
60
40
TG FinFET
80
DG FinFET
∆Ion/Ion(DG) (%)
IDS (µA)
50
Rf ≡ hSi/wSi = 3
30
20
60
40
20
10
VDS=1.0V
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VGS (V)
Weff-implied
[wSi/(2hSi)]
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Rf
(Note that the effective width (per fin) Weff = 2hSi + wSi is not appropriate.)
J. G. Fossum / 9
... due to strong bulk inversion in the undoped fin-UTB/channel.
DG FinFET
TG FinFET
DG FinFET w/o top gate stack
1019
Gate
SiO2
n (cm-3)
Rf = 39nm/13nm = 3
z
VGS=VDS=1.0V
1018
Buried SiO2
Si Substrate
0
5
10
15
20 25
z (nm)
30
35
The predicted electron density in the bulk of the undoped fin-UTB shows
substantial (strong) inversion, irrespective of the top-surface condition.
Activating the third gate is not beneficial nor practical.
J. G. Fossum / 10
The bulk inversion also underlies the use of thick SiON.
* Bulk (a.k.a. volume) inversion is not good, but is unavoidable.
* For strong inversion, it reduces the effective gate capacitance CG:
C ox
– Q i = 2 ----------------------- ( V GS – V t )
ε ox x i
1 + ------------ε Si t ox
(via integration of Poisson’s equation)
where xi is the average depth(s) of the inversion carriers, which
is increased by bulk inversion. The deeper xi reflects lower
inversion-layer capacitance, and yields lower CG and Qi.
* The quantization effect further increases xi and reduces CG.
* Because of the deeper xi, increasing tox is not so detrimental to CG
(which is less than Cox = εox/tox), and hence to Qi and current.
* Further, the thicker SiON (tox) reduces the parasitic G-S/D (fringe)
capacitance, which improves speed performance significantly.
J. G. Fossum / 11
The underlap is effected by engineering of the lateral doping-density
profile in the S/D fin-extension.
1021
Lg
Lext
1020
1019
y 2

-----N SD ( y ) ∝ 10 exp –
 σ L
20
Lext
1nm
NSD(y) [cm-3]
1018
1017
10nm
1016
Medici:
Lg=18nm, Lext=30nm, wSi=12nm
15nm
σL=5nm
σL
[nm]
DIBL
[mV/V]
S
[mV]
1013
1 (abrupt)
180
94
1012
5
35
62
10
46
66
15
79
71
1015
1014
Leff(weak)
1011
1010
20
30
40
50
60
y [nm]
70
80
90
100
Leff(strong) ≅ Lg
Straggle defines Leff(weak) > Lg.
Optimal straggle and extension length define best SCE (Ioff) vs. RS/D (Ion) tradeoff;
further, Vt can be adjusted for different applications via controlled S/D dopants in
channel, with reasonable sensitivity to process variations.
J. G. Fossum / 12
Very high mobilities can be achieved in undoped FinFETs.
Low transverse electric field (⇐ Qi/2) yields high carrier mobilities:
UFDG calibrations to long-Lg FinFETs
pMOSFETs ⇒ hole mobilities
nMOSFETs ⇒ electron mobilities
250.0
450.0
{110} DG pFinFET - UFDG
{110} DG pFinFET - measured
{100} DG pMOSFET - measured
{100} bulk pMOSFET - measured
{110} bulk pMOSFET - measured
(low NB)
400.0
200.0
µp(eff) [cm2/V-s]
µn(eff) [cm2/V-s]
350.0
300.0
250.0
µ0 = 565cm2/V-s
θ = 0.20
(wSi = 26nm)
≅x2
200.0
100.0
0.5
1.0
1.5
13
-2
Ninv [10 cm ]
100.0
≅x3
50.0
{110} DG nFinFET - UFDG
{100} DG nMOSFET - measured
{100} bulk nMOSFET - measured
150.0
µ0 = 250cm2/V-s
θ = 0.10
(wSi = 30nm)
150.0
2.0
0.0
0.0 0.2
0.4
0.6
0.8
Ninv
1.0
1.2
1.4
1.6
[1013cm-2]
J. G. Fossum / 13
1.8
2.0
But ....
UFDG calibrations to nFinFETs with varying Lg
Lg=1µm: UO=585, Θ=0.32
Lg=75nm: UO=400, Θ=0.2
Lg=32nm: UO=125, Θ=0.2
330
µn(eff) (cm2/V-s)
280
230
180
130
80
5.0e+12
1.0e+13
1.5e+13
Ninv
2.0e+13
2.5e+13
(cm-2)
Scaling Lg degrades µeff, which implies excessive scattering centers near the source/drain,
or perhaps significant remote S/D Coulomb scattering.
Recent work suggests that this problem can be resolved via optimal S/D engineering.
J. G. Fossum / 14
UFDG/Spice3: Pragmatic nanoscale DG-FinFET CMOS can give
good speed performance (with very low Ioff).
Lg = 18nm DG CMOS unloaded RO delays
8.0
Abrupt NSD(y) w/ G-S/D overlap (0.1Lg)
G-S/D underlap (3.4nm); tox = 1.0nm
G-S/D underlap (3.4nm); tox = 1.5nm
Delay/Stage [ps]
7.0
6.0
5.0
4.0
3.0
2.0
0.7
32% speed improvement
with pragmatic FinFET design*
0.8
0.9
1.0
1.1
VDD [V]
*The underlap and the thicker tox reduce the parasitic G-S/D fringe capacitance, which is
very significant in nanoscale CMOS devices.
J. G. Fossum / 15
Conclusions
❋ Pragmatic nanoscale DG-FinFET CMOS is
viable, and is potentially scalable to the end of
the SIA ITRS (where L g < 10nm).
❋ Source/drain engineering for G-S/D underlap, Vt
adjustment, and high carrier mobilities must be
optimized; and tall, thin fins must be controlled.
❋ Further, SOI enables embedded FBC (e.g., 1T)
DRAM, which can be viable.
J. G. Fossum / 16
UFDG: A Process/Physics-Based Predictive Compact Model
Applicable to Generic UTB DG MOSFETs
Wg Gf
ΦGf
Gf = Gb
S
n+
Leff p
tSi
n+
D
ΦGb
tSi = wSi
Gb
Gate
Wg = hSi
UFDG is applicable to SG FD/
SOI MOSFETs, as well as
symmetrical-, asymmetrical-,
and independent-gate DG
MOSFETs, including FinFETs.
n+
Source
Lg
n+
Drain
J. G. Fossum / 17
Short-Channel Effects Modeling in UFDG
(or, how two gates give good control of the electrostatics)
y
2-D Poisson equation (for weak inversion),
2
2
∂ φ ∂ φ qN B
--------- + --------- ≅ ---------- ,
2
ε Si
∂x
∂y
ΦGf t
oxf
x
Leff
is solved in (rectangular) body/channel (UTB) region,
defined by tSi and Leff ≠ Lg, by assuming
φ ( x, y ) ≅ α 0 ( y ) + α 1 ( y )x + α 2 ( y )x
Gf
S
2
in Poisson, and applying the (four) boundary conditions
(including surface-state charge at both interfaces). The derived
potential (with QM shift) defines the integrated (in x-y, over tSi) inversion
charge (Qi) and an effective channel length (Le < Leff averaged over tSi)
for predominant diffusion current (in y), and thus accounts for:
UTB tSi
ΦGb toxb
Gb
* S/D charge (impurity and/or carrier) sharing [Vt(Leff) & S(Leff)] ,
* DIBL (throughout UTB) [∆Vt(VDS)] .
J. G. Fossum / 18
D
Quantization Effects Modeling in UFDG
UFDG is actually a compact Poisson-Schrödinger solver:
Classical PE
Eigenfunction Ψ0 (104 m-1/2)
(charge coupling,
inversion-charge
distribution)
potentials,
electric fields
(classical Qi & Ich)
Model
SCHRED
2.0
0.6V
SWE
(eigenfunctions,
eigenvalues,
2-D DOS, F-D)
in UTB/channel
QM Qi & Ich
1-D SWE analytical solution is
derived using a variational
approach, then coupled to PE
and Qi(VGfS, VGbS) via
Newton-Raphson iteration, all
with dependence on tSi and Si
orientation, as well as Ex.
tSi = 5nm
1.0V
1.5
VGS = 1.5V
SDG nMOSFETs:
n+ poly gates
tSi = 20nm tox=1.5nm
NB=1017cm-3
1.0
0.5
1.5V
0.0
updated potentials,
electric fields
0.0
0.2
0.4
0.6
0.8
Normalized Position x/tSi
1.0
The QM modeling is also
the basis for a physical
mobility model for the
UTB carrier transport.
J. G. Fossum / 19