Nanostructures for Tera-bit Level
Charge Trap Flash Memories
Byung-Gook Park, Il Han Park, Jung-Hoon Lee,
Gil Sung Lee, Jang-Gn Yun
Inter-University Semiconductor Research Center
School of Electrical Eng. and Computer Sci.
Seoul National University
NanoForum'09
Outline
I.
Introduction
II. NAND Cell Structure
III. NOR Cell and Array Structure
IV. AND Cell and Array Structure
V. STAR NAND Flash Structure
VI. Conclusions
NanoForum'09
SNU SoEECS & ISRC
Flash Memory and Mobile Equipments
32
NanoForum'09
SNU SoEECS & ISRC
Expedited Growth Theory - NAND Flash
1000
ITRS (2008)
Hwang’s law
100
10
Capacity (Giga Bit)
Technology Node (nm)
100
10
2002 2004 2006 2008 2010 2012 2014 2016 2018
Year of Development
q Expedited growth theory of NAND flash memories
è Year 2011 1Tb capacity with 20nm feature size
NanoForum'09
SNU SoEECS & ISRC
Hard Disk Drive and Flash Memory
NanoForum'09
SNU SoEECS & ISRC
Growth of Storage Capacity
HDD
ODD
FGF
CTF
FeRAM
MRAM
PRAM
10T
1T
Capacity (bit)
100G
10G
1G
100M
10M
1M
100k
10k
1k
1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010
Year
NanoForum'09
SNU SoEECS & ISRC
Floating Gate vs. Charge Traps
Floating Gate
structure
SONOS
structure
ONO
Composite
Dielectrics
Gate
Gate
n+
n+
n+
n+
Ø No floating gate
- FG-FG space
- FG-active space
- Single gate structure
P-Si
P-Si
Tunnel
Blocking
3.1
3.8
1.85
3.8
NanoForum'09
8.0
e e e
h h h
Poly Si
SiO2
1.05
3.1
Si SiO2 Si3N4
Ø Defect immunity
- Non-conductive trap layer
- Discrete trap storage
Ø 3D structure compatibility
- Insulating storage node
- Simple fabrication
SNU SoEECS & ISRC
Outline
I.
Introduction
II. NAND Cell Structure
III. NOR Cell and Array Structure
IV. AND Cell and Array Structure
V. STAR NAND Flash Structure
VI. Conclusions
NanoForum'09
SNU SoEECS & ISRC
Arch Structure (1)
q Utilization of curved surfaces for field enhancement
- fast “program” and “erase”
- increased effective area
r2
r1
Poly
Arch type
Planar type
SiO 2
Si
Electric Field (V/cm)
ONO
12.0M
10.0M
8.0M
6.0M
4.0M
2.0M
0.0
Top Oxide
0
2
4
Silicon Nitride
6
8
10
12
Bottom
Oxide
14
Position (nm)
NanoForum'09
SNU SoEECS & ISRC
Arch Structure (2)
q Fabrication procedure
Hard
mask
Si
Si
SiO2
Si
NanoForum'09
SNU SoEECS & ISRC
Arch Structure (3)
q Utilization of HSQ mask characteristic
q Planarization by TEOS, HSQ and etch back
NanoForum'09
SNU SoEECS & ISRC
Arch Structure (4)
<Programming characteristics>
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
-5.5
-6.0
∆Vth (V)
∆Vth (V)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
20V
1.5
22V
1.0
24V
0.5
0.0
-0.5
-7
-6
-5
-4
-3
-2
-1
0
1
Initial
10 10 10 10 10 10 10 10 10
Time(s)
<Erase characteristics>
-18V
-20V
-22V
-24V
-7
-6
-5
-4
-3
-2
-1
0
1
Initial
10 10 10 10 10 10 10 10 10
Time(s)
q Radius of Si channel = 15 nm
NanoForum'09
SNU SoEECS & ISRC
Outline
I.
Introduction
II. NAND Cell Structure
III. NOR Cell and Array Structure
IV. AND Cell and Array Structure
V. STAR NAND Flash Structure
VI. Conclusions
NanoForum'09
SNU SoEECS & ISRC
Cone Structure (1)
q Utilization of field and current concentration
- field concentration in the horizontal direction
- current concentration in the vertical direction
Cut line
Drain junction
Cut line
Drain junction
ONO layer
Gate
Gate
ONO layer
Electric field
high flux density
r2
ER
r1
Er Drain
high flux density
flux
O N
Gate
Source
low flux density
NanoForum'09
Si
O
low flux density
SNU SoEECS & ISRC
Cone Structure (2)
q Simple array structure
- common source architecture
- word line connection through small spacing of cones
NanoForum'09
SNU SoEECS & ISRC
Cone Structure (3)
<Plan view>
NanoForum'09
<Cross-sectional view>
SNU SoEECS & ISRC
Cone Structure (4)
q Electrical characteristics
<Program/erase characteristics>
4.0
4.0
CHEI Program( VG: 6 V, VD:4 V)
3.5
VTH ( V)
2.5
CHEI Program( VG: 6 V, VD:3 V)
2.363 V
2.160 V
1.5
1.5
1.0
1.0
0.5
FN Erase ( V B : 11 V)
1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1
Time (s)
NanoForum'09
Retention Characteristics(150
C)
2.5
2.0
2.0
0.5
o
program state
3.0
3.0
VTH (V)
3.5
<Retention characteristic>
1
10
0.0 0
10
Erase state
1
10
2
10
3
10
4
10
5
10
6
10
7
10
Time (s)
SNU SoEECS & ISRC
8
10
Outline
I.
Introduction
II. NAND Cell and Array Structure
III. NOR Cell and Array Structure
IV. AND Cell and Array Structure
V. STAR NAND Flash Structure
VI. Conclusions
NanoForum'09
SNU SoEECS & ISRC
Conventional Flash Memory Structures
< NAND >
< NOR >
< AND >
LSL
LBL
Active
W/L
F-Poly
Schematic
Top View
NAND
NOR
AND
program efficiency
high
Low
high
sensing speed
low
high
high
density
high
low
low
NanoForum'09
SNU SoEECS & ISRC
Vertical AND Structure (1)
q Memory cell device with vertical and double gate structures
- vertical structure, S/D junctions connected by diffusion layer
à High integration density.
- double gate structure.
à High device performance, high sensing speed.
N
N
N
P
P
P
N
N
N
P
NanoForum'09
SNU SoEECS & ISRC
Vertical AND Structure (2)
q Fabrication procedure
N
N
N
N
N
N
N
P
P
P
P
N
N
N
P
N
N
N
N
P
N
N
N
N
N
N
P
N
N
N
N
P
P
P
P
P
P
P
P
P
P
N
N
N
N
N
N
N
N
N
N
P
P
P
(a)
(b)
(c)
N
N
N
N
P
P
(d)
N
N
N
N
N
P
P
P
P
N
N
N
P
N
N
N
N
N
P
N
N
N
N
N
P
N
N
N
P
P
P
P
P
P
P
P
P
P
P
P
N
N
N
N
N
N
N
N
N
N
N
N
P
P
(h)
NanoForum'09
P
P
(g)
P
N
(f)
(e)
SNU SoEECS & ISRC
Vertical AND Structure (3)
q Program/erase characteristics
<Program characteristics>
<Erase characteristics>
7
V G = 13 V
V G = 15 V
V G = 17 V
6
Threshold Voltage [V]
Threshold Voltage [V]
7
5
4
3
2
6
5
4
VG = 13 V
VG = 15 V
VG = 17 V
3
2
-7
10
-6
10
10
-5
-4
10
-3
10
10
-2
Programming Time (sec)
NanoForum'09
10
-1
10
-5
-4
10
-3
10
-2
10
10
-1
0
10
Erasing Time (sec)
SNU SoEECS & ISRC
Outline
I.
Introduction
II. NAND Cell Structure
III. NOR Cell and Array Structure
IV. AND Cell and Array Structure
V. STAR NAND Flash Structure
VI. Conclusions
NanoForum'09
SNU SoEECS & ISRC
STAR NAND Flash Structure (1)
WL direction
q Stacked bit-lines
à high density
gate
oxide
gate
ONO dielectrics
Si
cylindrical channel
Si
q Cylindrical channel and
gate-all-around cell
structure
à high performance
body
oxide
q Single-crystal Si channel
à high performance,
uniformity, reliability
Si substrate
NanoForum'09
SNU SoEECS & ISRC
24
STAR NAND Flash Structure (2)
q Fabrication procedure
mask
a>b
nitride
nitride
nitride
SiGe
SiGe
Si
Si
SiGe
SiGe
SiGe
Si
Si
Si
SiGe
SiGe
Si substrate
SiGe
Si
SiGe
Si substrate
Si substrate
SiGe
SiGe
nitride
nitride
nitride
a>b
SiGe
Si
Si
Si
SiGe
Si
Si
Si
SiGe
Si substrate
NanoForum'09
Si substrate
Si substrate
SNU SoEECS & ISRC
STAR NAND Flash Structure (3)
q Fabrication procedure
(continued)
WL direction
gate
gate
SiGe
nitride
ONO
oxide
gate
Si
Si
Si
ONO dielectrics
Si
cylindrical channel
Si
Si
ONO
Si substrate
NanoForum'09
Si substrate
Si
body
oxide
Si substrate
SNU SoEECS & ISRC
STAR NAND Flash Structure (4)
q Components of stack and nanowire implementation
<Selectively etched SiGe>
NanoForum'09
<Rounded Si nanowire>
SNU SoEECS & ISRC
27
Conclusions (1)
q Charge trap flash memory including SONOS structure is
a promising candidate for the next generation high
density flash memories.
q For NAND application, arch SONOS flash memory is
proposed for field concentration and suppression of
back tunneling and is successfully demonstrated.
q For NOR application, cone SONOS flash memory is
proposed for field and current concentration, and the
fabricated cell shows superb electrical characterics.
NanoForum'09
SNU SoEECS & ISRC
Conclusions (2)
q For AND application, vertical AND structure is proposed
for drastic reduction of cell size and the feasibility is
demonstrated.
q For further increase of density, STacked ARray (STAR)
NAND array is proposed.
NanoForum'09
SNU SoEECS & ISRC