The Sixth U.S.-Korea Forum on Nanotechnology, April 28-29, 2009, Las Vegas, NV
Opportunities and Challenges for
Nanoelectronic Devices and Processes
Yoshio Nishi
Professor, Electrical Engineering, Material Science and Engineering
Director of Research, Center for Integrated Systems
Director, Stanford Nanofabrication Facility
Stanford University
[email protected]
Status Quo for “Moore” and “More Moore”
•
CMOS Scaling is not coming to an end
• 45 nm is happening
• 32 nm well on its way
• 22 nm will happen
•
Major ongoing transformation of scaling caused by power and
power/density
•
End of frequency scaling of single core processor
• No “10 GHz” microprocessor (with the ~100 W cooling limit)
•
System performance based on multi-low-power cores and accelerators
• Move away from frequency scaling
•
How many “Moore” generations?
• As long as we have affordable lithography
G. Shahidi, IBM
Paradigm Shift: Hitting the Cooling Limit
• Moving a high power chip to the next node (with limitation
on cooling and maximum T rise), actually will slow it down
1400
Performance
1300
1200
Peak Frequency
(100W/cm2 cooling @ max T 85C)
With Performance Scaling
50 W
72 W
40 W
65 W
1100
80 W
1000
No Perf. scaling
(Only Shrink)
100 W
50 W
25 W
900
800
90nm
65nm 45nm
32nm 22nm
Technology
End of frequency scaling @ ~4 GHz (with 100 W cooling)?
System Performance from Multi-Cores
14
Module Heat Flux(watts/cm2)
IBM ES9000
Prescott
12
10
Squadrons
8
IBM GP
IBM 3090S
6
Pentium 4
4
IBM 3090
2
0
Vacuum IBM 360
Merced
IBM 370
Pentium II(DSIP)
Bipolar
CMOS
NMOS / PMOS
/CMOS
1950
1960
1970
1980
1990
Low-Power
Performance
Multi-Core
Density
CMOS
2000
CMOS
2010
“Beyond Moore” On-going Trends
• Nanoelectronics: Ge, III-V channel to
nanowire/nanotubes and more
• Nano-bio/medical: Bio-sensing, imaging
• Energy: nanowire solar, nanotube hydrogen
storage
• Environmental sensing: Sensor network,
gaseous molecules sensing, ocean, air…
• Fusion of nanoelectronics and
nanomechanical: New switches and memories
Year
06
Optimistic scenario
07 08 09 10 11 12 13 14 15 16 17 18 19 20
Strained channel
New channel materials, Ge, III-V
65nm
SOI , FD, UTB
Nanowire devices/nanotubes
45nm
Molecular devices
32nm
Spintronics
22nm
Flash
15nm
PCRAM
FERAM
10nm
7nm?
5nm?
ReRAM
MRAM?
Organic/Molecular?
Emerging Bio/Medical Chips
2D chip+3D package
3D chip
193nm+liquid immersion
EUV?
Self-assembly/bottom up?
High mobility channel Ge and its
issues
•
Advantages
–
–
–
–
•
High electron/hole mobility
Compatibility to Si LSI
Lower temperature process
Possible Vdd scaling
Process and device Issues
1.
1600
3900
Hole µ (cm2/Vs)
430
1900
Band gap (eV, 300K)
1.12
0.66
Dielectric constant
11.9
16
Loss of Qch and m degradation
Increase contact resistance
Small electron mobility gain
•
4.
5.
Electron µ (cm2/Vs)
Strong Fermi-level pinning at
metal/Ge contact
•
3.
Ge
Poor interface property of Ge
MOS gate
•
2.
Si
Require mobility booster
Poor N-type dopant activation
Band-to-band tunneling leakage
S
Ge
G
2
1
3 5 D4
Si or SiO2
4
NMOS Performance Comparison Simulation
8
15
10nm
5nm
3nm
6
vinj (107cm/s)
Qi (1012#/cm2)
Injecion Velocity (Vinj)
10
5
On current (ION)
6
10nm
5nm
3nm
5
ION (mA/µm)
Channel Charge (Qi)
4
2
10nm
5nm
3nm
4
3
2
1
0
Si GaAs InP
S
Ge InAs InSb
G
Gate
dielectric
Channel
D
G
0
LG=15 nm
TOX=0.7 nm
VG=0.7V
Si GaAs InP
Ge InAs InSb
0
Si GaAs InP
Ge InAs InSb
ƒ Si high Qi low Vinj
ƒ III-V low Qi high Vinj
ƒ Ge reasonably high Qi and Vinj has
highest ION
ƒ Effect of strain is being modeled
Kim, Krishnamohan & Saraswat, IEEE DRC 2008
Non-silicon high mobility channel
approaches
• It will fulfill the needs for “higher speed and lower power
consumption”
• High mobility materials-gate insulator interface is the
biggest issue
• Ge option may provide an opportunity for on-chip optical
interconnect; at least for detector, and maybe for
transmitter
• Integration density would stay with Si VLSI trend line
(ITRS)
• Preferential application on top of the Si platform looks
rational option to go
ON/OFF & Bandgap vs. width for
GNRs
7
0.5
10
6
10
0.4
5
I on /I off = exp( E g / k BT )
Eg(eV)
10
4
Ion/Ioff
10
3
10
E g (eV ) =
0.3
0 .8
W (nm )
0.2
2
10
0.1
1
10
0
10
0
10
20
30 40
W (nm)
50
0.0
0
10
20
30 40
W (nm)
50
• All (> 40) sub-10nm GNRs measured thus far are
semiconducting with high on/off switching at 300K
H. Dai, Stanford, 08
Graphene ribbon vs. Carbon
Nanotube
16
14
Ion(µΑ)
12
d~1.6nm, L~100nm
10
GNR w~3nm L~100nm
GNR w~2nm L~236nm
SWNT d~1.6nm L~102nm
SWNT d~1.6nm L~254nm
SWNT d~1.3nm L~110nm
SWNT d~1.1nm L~254nm
8
6
d~1.6nm, L~250nm
4
d~1.3nm, L~100nm
2
d~1.1nm
0
10
2
10
4
10
Ion /Ioff
6
10
™ High on/off GNR comparable to~1.2nm SWNT FETs
™ GNR FETs comparable to high performance SWNT FETs
(d~1.4-1.5nm) remains illusive
H. Dai, Stanford, 08
Integration Challenges of CNT, GNR
etc
• Enough performance advantage over other options as
individual devices
• A large variety of tunability for the band structure for a
number of applications
• Questions for controlled growth for nanowires and
nanotubes still remain without sacrificing integration
density
• No top down lithographic technology for the geometry
ranges of GNR
• Variability
Integration of Electronics into Cells
Adhesion force
• nanoscale-functionalized probes
at the end of AFM cantilever tips
that can directly integrate into a
cell membrane.
• “stealth electrodes” do not cause
membrane damage, and
specifically attach to the core of
the lipid bilayer.
• future work will involve fabrication
of planar arrays of the devices for
on-chip electrophysiological
measurements.
Professor Nicholas Melosh,
Department of Materials Science and
Engineering, Stanford University
AFM force
measurements of the
tip interaction with the
bilayer.
Si
10 nm
A nanoprobe tip.
Au
Nanowire Dye-Sensitized Solar-Cells
Dye-sensitized solar cell is one of the most promising third
generation solar cells. Using semiconductor nanowires array,
as the electron conducting material to replace nanoparticle film,
can achieve both a large surface area and a low intrinsic
resistance as well as an improved energy conversion efficiency.
The idea of this project is: First, using templated Sol-Gel
method to grow high aspect ratio and high density TiO2
nanowire array; Secondly, providing bonding of the wire array
to a transparent and conductive layer by “after-growth”
deposition of materials like ITO onto the back of the nanowire
array; Then, dissolving the template following attaching the
sample onto a substrate; Finally, this substrate can serve as
the anode of the dye-sensitized solar cell.
The above nanowire fabrication method can exceed VLS or
CVD in aspect ratio and density, and exceed powder based
porous array deposition in minimized grain boundaries existing
in the electron diffusion paths.
ITO
Template
Nanowires
Sputtering ITO
Ying Chen and Yoshio Nishi
After Dissolving
Template
Scale bar: 2um
Summary
• A large variety of opportunities in
revolutionary “nano” spaces, from
traditional electronics to bio/medical,
energy and environment
• Manufacturing strategy is still missing and
challenges in “variability”, “reproducibility”,
“cost” and “reliability” requires strong
attentions