2nd US-Korea NanoForum, LA
Fabrication and Characterization
of bulk FinFETs for Future NanoScale CMOS Technology
Jong-Ho Lee
[email protected]
School of EECS and National Education Center for Semiconductor Technology
Kyungpook National University, Daegu, 702-701 Korea
2nd US-Korea NanoForum, LA
Jong-Ho Lee
Contents
Introduction
Simulation Study
Fabrication of Bulk FinFETs
by Spacer Technology
by Selective Si3N4 Recess
Device and SRAM Cell Characteristics
Summary
2nd US-Korea NanoForum, LA
Jong-Ho Lee
Introduction: Technology Roadmap Beyond Bulk LDD CMOS
TG
TG
S/D
S/D
Performance
Double/Triple-Gate
G
BG
BG
S/D
Double-Gate CMOS
G
SOI/SiGe
S/D
SOI PD/FD CMOS
Halo
Si
S/D
S/D
Fin Double/Triple-Gate FET
G
SiGe
S/D
SiGe CMOS (high mobility)
G
Bulk
Bulk LDD CMOS (Halo)
2004
2nd US-Korea NanoForum, LA
2006
2008
Jong-Ho Lee
2010
Time
Introduction
‹ Driving Force of CMOS Scaling-down:
Æ High Performance and High Integration Density
‹ A Promising Device Structure
Æ Double/Triple-Gate MOSFETs (or FinFETs)
‹ Why Double/Triple-Gate Transistor?
G
Æ Robustness against SCE
Æ Higher Current Drivability
Æ Good Subthreshold Swing
2nd US-Korea NanoForum, LA
Jong-Ho Lee
D
S
Si film
G
Current- Carrying
Plane
Z
Y
X
Top Gate
Current- Carrying
Plane
Introduction: Types of Double-Gate Transistors
Z
Y
Left Gate
Bottom Gate
(a) Type I
X
current
direction
D
S
D
Right Gate
S
Silicon Wafer
Silicon Wafer
(b) Type II
S current
direction
Right Gate
D
CurrentCarrying
Plane
Left
Gate
Z
Y
X
(c) Type III
Process technology of FinFET is
easy and compatible with
conventional fabrication process
Silicon Wafer
∗ H. P. Wong et al., IBM, vol. 87, no. 4, p.537, 1999, Proceedings of the IEEE
2nd US-Korea NanoForum, LA
Jong-Ho Lee
Types of Double/Triple-Gate Transistors
Type
Type I
(Planar DG
FETs)
Type II
(Vertical DG
FETs)
Type III
(FinFETs)
Gate
Position
Top/Bottom
Left/Right (or
Cylinder)
Left/Right
Left/Right/Top
Body
Shape
Horizontal
Vertical
Vertical
Vertical
Horizontal
Surfaces
Side Surfaces
Side Surfaces
Side Surfaces
Horizontal
Vertical
Horizontal
Horizontal
Key
Geometry
Current
Carrying
Plane
Current
Flow
Direction
2nd US-Korea NanoForum, LA
Jong-Ho Lee
(Triple-Gate
MOSFETs)
Double-Gate Transistor (SOI FinFET)
‹ FinFET
à simple, self-aligned double-gates
à good process compatibility
Ä thickness control of fin body
Ä RIE damage on the channel, high S/D resistance
∗ D. Hisamoto et al., UC Berkeley, p.1032, IEDM 1998
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Jong-Ho Lee
Body-Tied Double/Triple-Gate MOSFET Using
Bulk Wafer (Bulk FinFET)
S/D
‹ Low wafer cost
te
a
G
0
S/D
Body
Ox
ide
Si
Su
bs
t ra
t
HFin
‹ Low defect density
‹ Less back-bias effect
xj
WFin
‹ High heat transfer rate
to substrate
‹ Good process compatibility
TFOX
e
World 1st Cost-Effective
Double/Triple-Gate MOSFETs
Schematic 3-D View
∗ J.-H. Lee., Korea/Japan/USA patent
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Jong-Ho Lee
Cross-Sectional Views (Body Structure) for 3Dimensional Device Simulation
Fin body
Gate
SiO2
SiO2
Si sub
Si sub
SOI FinFET
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Gate
Bulk FinFET
Jong-Ho Lee
Fin body
3-D Simulation Results
180
LG=25 nm
0.4
150
TOX=1.5 nm
VT (V)
Bulk
SOI
0.3
19
Na=1x10 cm
0.1
60
-3
HFin=70 nm
xj,S/D=66 nm
10
20
30
90
30
40
50
0
DIBL (mV/0.9V)
120
0.2
100
Subthreshold Swing (mV/dec)
0.5
95
LG=25 nm
TOX=1.5 nm
85
Bulk
SOI
VDS=0.05 V
80
75
19
Na=1x10 cm
70
10
20
30
HFin=70 nm
-3
xj,S/D=66 nm
40
VT and DIBL versus Fin Width
Subthreshold Swing versus Fin Width
for fully depleted body
∗ J.-H. Lee et al., KNU, p. 102, Si Nanoelectronics Workshop 2003
2nd US-Korea NanoForum, LA
50
Fin Width (nm)
Fin Width (nm)
qN sub t b
V T = Φ MS + 2φ B +
2 C ox
VDS=0.9 V
90
Jong-Ho Lee
3-D Simulation Results
S/D
te
a
G
Ox
ide
Si
Su
bs
tra
te
HFin
Body
S/D
0
xj
WFin
TFOX
Device Temperature (K)
475
450
LG=30 nm
425
TOX=1.5 nm
400
VDS=0.9 V
substrate electrode
@ temperature=300 K
SOI
375
∆T~130 °C
350
Bulk
325
300
Heat
0.0
0.2
0.4
0.6
0.8
1.0
Gate Voltage (V)
3-D Schematic View of Heat
Transfer from Body to Substrate
Device Temperature versus Gate
Voltage
∗ J.-H. Lee et al., KNU, p. 102, Si Nanoelectronics Workshop 2003
2nd US-Korea NanoForum, LA
Jong-Ho Lee
Fabrication Steps by Using Spacer Technology
SiN 80 nm
SiO2 30 nm
SiN 25 nm
SiO2 30 nm
Si
4 Stack Layer Growth and Deposition
Poly-Si Spacer
30 nm
SiN Removal Using Phosphoric Acid
Poly-Si Spacer
Si
Photo Lithography, SiN Etching,
Poly-Si Depo., and Dry Etching
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Jong-Ho Lee
Fabrication Steps
Fin Dry Etching
SiO2, SiN, and SiO2 Dry Etching
Top Si Width 25 nm
Bottom Si Width 100 nm
Si Fin Height 230 nm
Fin body
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Jong-Ho Lee
Fabrication Steps
SiO2
Wet Etch-back
Thin Ox., Filling, and Densification
Field Oxide Thickness 80 nm
SiO2
Chemical Mechanical Polishing (CMP)
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/ 27
First Body-Tied Triple-Gate MOFET (Bulk
FinFET)
Gate Poly-Si Etching
40 nm
Poly-Si
Drain Current (A)
As+, 20 keV 3x1015/cm2, 2 Fin
10
-7
V DS = 0.1 V
25 nm
10
-8
50 nm
10
10
-9
Vbs = 0 V
Vbs = -1 V
Vbs = -2 V
40 nm
-10
-0.5
0.0
0.5
1.0
Gate Voltage (V)
1.5
ID-VGS Characteristics of 40 nm bulk NFiNFET
∗ T. Park et al., SNU/KNU, Nanomes03 2003
∗ T. Park et al., SNU/KNU, Physica E19, p.6, 2003
2nd US-Korea NanoForum, LA
Jong-Ho Lee
Modified Structure of Bulk FinFET
Thick SiN liner formation &
SiN liner only recessed
CMP and
partial etch-back
Top Si Width 25 nm
Bottom Si Width 100 nm
Si Fin Height 230 nm
unclear
t
Ga
Oxide
lec
E
e
e
d
o
tr
SiO
Si
Fin
2
SiO
2
SiN
‹ Clear Sidewall Open
S
‹ Planarization of the Top Surface of Poly-Si Gate
ƒ Easy nano-scale patterning of gate poly-Si
∗ E. Yoon, J.-H. Lee, and T. park, Korea/Japan/USA/Germany patent
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ub
S
i
te
a
r
st
Key Process Steps of Modified Bulk FinFET
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Jong-Ho Lee
SEM Views of Key Process Steps
SiN
SiO2
SiN
Active Fin
Gate
Si Substrate
Si Substrate
SiN Liner Deposition
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SiN Recess Etch
Jong-Ho Lee
SEM Views of Key Process Steps
Gate Etch Profiles
Gate Stack
SiN
SiO2
SiN
Poly-Si
Gate Stack
Mask SiN Width = 70 nm, Poly-Si Neck Width = 47 nm
Poly-Si Bottom Width = 64 nm
Fins
Si Substrate
Si Substrate
Along Gate Line
Across Gate Line
∗ T. Park et al., Samung/SNU/KNU, Symp. on VLSI Tech., 2003
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Jong-Ho Lee
SEM and TEM Views of Key Process Steps
Si Fin
30 nm
SiN Liner Deposition
99 nm
82˚
Gate P
oly-Si
fin
Poly-Si
61 nm
SiN
181 nm
SiN
SiO2
Si Substrate
Along Gate Line
12 nm fin body
∗ T. Park et al., Samung/SNU/KNU, IEDM., 2003
2nd US-Korea NanoForum, LA
Jong-Ho Lee
Bulk FinFET Measurement
ID-VGS plot: ID, DIBL, SS, and Isub
-4
10
-5
10
-6
10
-4
VBS = 0 V
-1 V
1V
|ID |, |ISUB| (A)
-7
10
-9
10
-10
10
-11
10
-7
-14
10
ID
ISUB
-8
10
ISUB
10
-11
10
-12
10
-13
0.05 V 10
-0.05 V
-14
-2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
Gate Voltage (V)
2nd US-Korea NanoForum, LA
10
TOx,top=1.8 nm
-9
10
TOx,top=5.5 nm
-10
VDS=1 V
VDS=-1 V
10
-13
LG=100 nm
W Fin=25 nm
HFin=100 nm
-12
10
-5
10
VDS=0.05 V 10-6
VDS=-0.05 V
10
-8
10
Jong-Ho Lee
10
2.0
‹ Measured ID-VGS of N
and P type bulk FinFETs
with drain bias
ƒ high Ion(~200 µA/µm
@ VGS=1.5 V) compared
to that of first lot devices
ƒ low Ioff (<0.2 nA/µm
@ VDS=1.0 V)
ƒ Isub/ID < ~10-7
Static Noise Margin (SNM)
Bulk FinFET
Planar MOSFET
Pass
Load
Pull-Down
2nd US-Korea NanoForum, LA
W/L
Load: 35 nm/90 nm
Pass: 35 nm/90 nm
Pull-Down: 50 nm/90 nm
Jong-Ho Lee
Summary
™ Briefly introduced key features of double/triple-gate
FinFETs
™ Bulk FinFETs were compared with SOI FinFETs
ƒ Nearly the same device scalability
ƒ Better wafer quality
ƒ Better characteristics regarding the body connected to sub.
™ Bulk FinFETs have been demonstrated experimentally
ƒ First nano-scale bulk FinFET realized by using spacer technology
ƒ Modified bulk FinFETs realized by adopting selective Si3N4 recess
™ Good device characteristics were achieved and SNM of
280 mV was obtained from SRAM cell at VCC of 1.2 V
2nd US-Korea NanoForum, LA
Jong-Ho Lee
3-D Device Structure for Simulation
LG=25 nm
Gate
S/D
S/D
S/D
S/D
body
SiO2
Si substrate
Si substrate
body
2nd US-Korea NanoForum, LA
TOX=1.5 nm
Jong-Ho Lee
Key Process Steps for Thinning of the Fin Body
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Jong-Ho Lee