.
Seyed-NematAllah Ahmadyan
R
CE D
,D
S
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ce.sharif.edu/~ahmadyan
[DSL],
ahmadyan@{ce.sharif.edu,gmail.com}
,S
Tel: (+ )
Objective: Doctorate in Computer Engineering specializing in VLSI and Embedded Systems, and research
in the said fields either in academia or an appropriate industrial environment.
Research area
Reliability and Fault Tolerance
Embedded System Design
VLSI
Education
-C
M.Sc. student in Computer Architecture from Sharif University of Technology, Tehran, Iran. [Current
GPA= 18/20 ] (expected: Spring 2011)
Thesis: ”Analytical Approaches for Soft Error Rate Estimation of Digital Cir-
cuits at Circuit Level”, under supervision of Prof. Miremadi.
-
B.Sc. student in Computer Engineering from Sharif University of Technology, Tehran, Iran. with major
in Computer Hardware Engineering [GPA= 16.25/20, Major=17.1/20]
Thesis: ”Fault Injection Using Behavioral Model of Faults”, under supervision of Prof.
Miremadi.
Diploma in Math & Physics, Shahid Beheshti High school, Amol, Iran. Affiliated with the National
Organization for the Development of Exceptional Talents (NODET), GPA=19.90/20
publications
DATE-
M. Fazeli, S.N.Ahmadian, S.G. Miremadi, ”Soft Error Rate Estimation of Sequen-
tial Circuits in the Presence of Multiple Event Transients, to appear in Design,
Automation and Test in Europe Conference (DATE), 2011.
BMAS-
S.N.Ahmadian, S.G. Miremadi, ”Fault Injection in Mixed-Signal Environment
Using Behavioral Fault Modeling in Verilog-A”, e IEEE Beharvioral Modeling and
Simulation Conference, Sep. 2010. San Jose, USA.
DSN-
M. Fazeli, S. G. Miremadi, H. Asadi, S.N.Ahmadian, ”A Fast and Accurate Multi-
Cycle Soft Error Rate Estimation Approach to Resilient Embedded Systems
Design”, the 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
(DSN-2010), 28 June-1 July 2010, Chicago, USA.
HASE-
M. Fazeli, S.N.Ahmadian, S.G. Miremadi,
”A Low Energy Soft Error-Tolerant
Architecture for the Register File in Embedded Processors”, e 11th IEEE High
Assurance Systems Engineering Symposium, 2008.
.
Awards and Recognition
Ranked 8th in national entrance exam for graduate students in Computer Architecture
Iran Ministry of Education, Kharazmi Award on Computer
Granted the Exceptional Talents advantage (due to Kharazmi award) to enter under-graduate level without taking the usual entrance exam, 2005, Sharif University.
Ranked 1st in 3rd Sharif FPGA Design Contest
Membership
Member of Sharif Dependable System Lab [DSL].
IEEE member
ACM member
Teaching Experience
TA,CE D.,S
Advance Programming [ Java ], Spring 2006 by Dr. Habib Rostami.
Introduction to Programming [ C/C++ ], Fall 2005 & Spring 2006, by Dr. Ehsan Nazerfard.
Internet Engineering, Fall 2008, by Dr. Habib Rostami.
Hardware Description Languages (Graduate Course), Fall 2008-2010, by Dr. Mahdi Modaressi.
Digital System Design [Verilog], Spring 2009, Fall 2009 by Dr. Alireza Ejlali.
TA,EE D.,S
VLSI Digital Design (Graduate Course), Fall 2009, by Dr. Mohamad Sharifkhani.
L, AXXON
Computer Architecture, Fall 2010.
Research Projects
A S E R E
As part of my M.Sc. thesis, I’m working on analytical approaches to estimate soft error
rate in presence of SETs and METs. My objective is to develop an efficient and accurate soft error rate estimation technique to identify the
most vulnerable gates in a design. My work is based on error probability propagation in the circuits. For this, I’ve developed a novel fault
modeling system and a fully automated circuit analyzer CAD tool to implement my ideas. This tool consists of static circuit analyzer (at gate
and layout level) and timing driven Monte Carlo simulator (for reference model for fault injection). My circuit model was graph-based and I
implemented (and sometimes developed) variety of graph algorithms to use here. Our works yield to an interesting results. I’ve published the
result of our work at many well-known conferences and journals. Right now, I’m working on developing placement-aware model for Multiple Event
Transient, So I can develop MET-Aware placement and routing algorithms for MET-Mitigation in digital circuit. (“Placement-Aware Multiple
Event Transient Modeling and Error-Rate Estimation “[unpublished]). I am also interested in the effects of the circuit or microprocessor
inputs on soft error rate or as we call it application derating factors (“Application-Aware SER Modeling of Irregular Structures in Advanced
Microprocessors [unpublished]”). Right now, my approach works at circuit level, however I hope by considering application derating, I can
move up in the abstraction chain!).
FPGA-B F I
I am interested in Reliability evaluation of systems, either using analytical approach or fault injections. I
worked on FPGA-based fault injection platforms (which we widely used the platform for reliability evaluation of industrial project like
FT-Sparc processor). The FI platform was based on Altera Stratix-IV FPGA with TCL-based interface for controlling and observing.
R-P T   R F
I worked on low power / fault tolerant register file architectures. For example, We proposed
register caching technique for register files to enhance register file reliability of ARM processor. I am interested in the interplay of
power and reliability to find the optimum solution. I've also worked on low power register file architectures by exploiting register file
partitioning and narrow-width registers.
B F M  I
I’ve designed and developed fault injection platforms and analyze framework. For example, for
my B.Sc. thesis I’ve worked on behavioral fault injection (using verilog-A) in mixed-signal environment. I proposed using behavioral model
(implemented in behavioral modeling languages such as Verilog-A ) for fault injection purpose in mixed-signal environemnt. Using this
approach, I implemented a model for various faults like SETs, Power Supply faults, EMIs and temperature variations.
I  AES /   FPGA
I have design explored variety of ways for implementing AES. it's
like one of my hobbies. [fips-197 standard, rijndael algorithm] Later, I ported the design to ASIC (45nm standard cell) as part of my Advance
VLSI design course project. I have done Synthesize (Synopsys DC&PC), P&R(Cadence SoC-Encounter), DRC (Mentor Calibre) & Post-Layout and
IR-Drop verification (Synopsys HSIM/Mentor Modelsim CoSimulation), Power (PrimePower), Timing (PrimeTime) and Reliability analysis (in-house
tool).
D       
I design and implemented an embedded video processing platform on
FPGA, as the input, we captured SD or HD video stream from standard video source (like PAL) and after several processing IPs and filtering,
we could process it on embedded CPUs and produce processed SD/HD output video stream. I used DDR2 memory for buffering. The whole design
fit into one Stratix-III 150K fpga. This design won 1st award in 3rd sharif FPGA design contest.
.Professional
Experience
C/
I'm a share-holder in Sorbon Industrial Group and Sorbon Private Holding.
Research Assistant. ‚ÄéDependable System Lab, CE Department, Sharif University of technology
Behravesh Inc. Senior R&D Engineer. Design and Implementation of fully-automated, On-Line
multi-platform multi-core Massive Data Acquisition and Signal Processing System (Hardware, Software
and Protocols). is platform is currently under beta test for mass production at Iranian's major power
plants.
-
Hamkaran System Group R&D, J2EE Developer
I was member of a team that worked on enterprise java solutions.
C/
Design & Implementation of a Tester machine for Prima Automated Car door handler (primary used in
buses and vans machines). e tester was programmable and supported both normal test & burn-in test.
C/
Design and Implementation of a Digital Music Player ( Mp3, WMA ) .is product is now widely used
in iran’s embedded market
Technical skills
P. L
Pro cient in C/C++, Java/J2SE/J2EE and related technologies, Matlab
HDL
Verilog, SystemVerilog, Verilog-A, VHDL, SystemC
O S
Unix/Linux based OS and Linux Kernel. Embedded system like uClinux/RTEMS/Erika/OS-II/eCoS,
Windows, Mac OS X
CAD
I'm the maintainer of Sharif Digital VLSI Flow (complete RTL-to-GDSII ow) used by default inside
Sharif CE & EE departments, it gained popularity even outside of Sharif for industrial use.
M 
Expert on Mixed-Signal simulation,
S
Modelsim-Hsim Mixed-mode simulatiom, Questa, Hspice, Eldo, Spectre, ActiveHDL, Riviera-PRO,
ModelSim, FPGA Advantage, Altium Designer ,DXP, Protel , Orcad Pspice
S 
Synopsys Design Compiler (+Power Compiler, +DFT Compiler), Synopsys IC Compiler, Synopsys Synplfy Pro, Altera Quartus II, Xilinx ISE, Leonardo Spectrum( FPGA & ASIC ), Tanners EDA LEdit ,
HW/SW CoDesign tools
-
Cadence SoC Encounter, IC Compiler, Mentor Calibre, Synopsys HSIM (post-layout veri cation. IRDrop and Cross-talk analyse), Critic, Hanex
P  FPGA
NoisII , ARM v7 and V9 (I synthesized & veri ed an ISA & Cycle-accurate Verilog Description of ARM
A
core ), Leon (I ported to FPGA) & OpenSparc T1( Sparc V9 ), OpenRisc1200 (did synthesize and
reliability analysis), alpha ,80x86
Altera Stratix and Cyclone Family, Xilinx Spartan and Virtex Family
V
VmWare vSphere and vCenter Server
A
SimpleScalar( ARM, Alpha, x86(zesto), NiosII ISS, or1kSim(OpenRisc1200) ,TSIM(Leon2), AVRStu-
S
dio. (AVR)
L
Farsi(native), English ( uent) (TOEFL=106/120), Arabic(intermediate)
Interests & activities
Social philosophy
Hardware Hacking
Chess
Alternative Music
‚Äé
‚Äé
references available upon request