Digital System Design
Lecture 3: ASIC Design
Amir Masoud Gharehbaghi
[email protected]
Table of Contents
{
{
{
Microelectronic Industry
Rapid Prototyping
ASIC Design
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Microelectronics Market
{
Primary Market
z
z
z
{
Information Systems
Telecommunications
Consumer
Secondary Market
z
z
Systems (e.g. Transportation)
Manufacturing (e.g. Robots)
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Electronic Market
Systems
Electronic Sub-Systems
Integrates Circuits
EDA
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Trends in Microelectronics
{
Improvement in Device Technology
z
z
z
{
Smaller Circuits
Higher Performance
More Devices on a Chip
Higher Degree of Integration
z
z
z
More Complex Systems
Lower Cost
Higher Reliability
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Moore’s Law
{
Every 18 Months:
z
z
Gate Count Doubles
Frequency Increases 50%
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Integration-Scale Limitations
{
{
Intrinsic physical scaling limits
Capital investment for fabrication
z
{
Use of appropriate design styles
Large-scale design management
z
Use of CAD tools for design
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Microelectronic Design Problems
{
Use most recent technologies
z
{
Reduce design cost
z
{
Higher performance
Lower price
Speedup design time
z
Shorten time-to-market
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Rapid Prototyping
{
Prototype:
z
z
{
The original or model on which
something is based or formed
Something that serves as an example
of its kind
Rapid:
z
z
Occurring within a short time
Happening Speedily
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Why Rapid Prototyping?
{
{
{
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{
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Avoid high non-recurring engineering (NRE) costs
Avoid long construction time for "real" system
Reduced time allowed from concept to product
Can quickly react to changing customer
environment or requirements
Systems are too complex to simulate real-world
operation in "bounded" time (need to build to
test)
Customers won’t put up with unreliable products
Sometimes the prototype is the product
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Why Not Rapid Prototyping?
{
{
{
{
Not the same performance as final
product (slower)
Not the same size as final product
(bigger or more ICs required)
Prototype more expensive than final
production unit
More design time required to complete
engineering of both prototype and final
system
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VLSI Market
ASIC
Application Specific
Integrated Circuits
ASSP
Application Specific
Standard Part
Standard (Commodity) Part
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Implementation Technologies
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ASIC
{
{
Dedicated to single function, or limited
range of functions
Not ASIC:
z
z
z
{
CPUs, Microprocessors
Memories: DRAM, SRAM, ROM, …
Standard Components (e.g. 74 Series)
ASIC:
z
z
z
Toy Chips
Mpeg Decoder/Encoder ICs
DSP Processors
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Design Aspects
{
Shorter product life-time
z
z
z
Shorter time-to-market
More parallel design flow
Better communication between
different design groups
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Design Aspects (cont.)
{
More complex systems
z
z
z
z
More efficient design methods need to
be used
Design automation is a necessity
More tool-dependant design and
optimization
More difficult to ensure correct functionality
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Design Aspects (cont.)
{
Not fixed system specification when
starting the design entry
z
z
z
More emphasis on high level design aspects
Flexible and very rapid design flow
Easy testability through the whole design
flow
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Structures ASIC Design
{
{
{
{
Hierarchy: Subdivide the design into
many levels of sub-modules
Regularity: Subdivide to max number of
similar sub-modules at each level
Modularity: Define sub-modules
unambiguously & well defined interfaces
Locality: Max local connections, keeping
critical paths within module boundaries
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ASIC vs. Standard IC
Standard IC
{
{
{
{
{
{
Typically low
component cost
Parts available off the
shelf
Low or insignificant IC
design cost
Proven component
reliability
Multiple sourcing
System house not
required to have inhouse experts in chip
design
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ASIC
{
{
{
{
{
{
{
Good security of intellectual
property
Optimum system design
Relatively efficient use of board
space (smaller systems)
Reliability enhanced at system level
(fewer components)
Performance may be better than
comparable standard ICs (unique
features and lower power
consumption)
Possibility to optimize component cost
Design cost is high and design cycle
is long
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ASICs
{
{
{
{
Advantages
Efficient use of board
space (lower final
system cost)
Product security
Unique features and
fine-tuning the
product
Optimized system
performance
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{
{
{
Disadvantages
Potential for design
failure
Not off-the-shelf
available
(specification, design,
testing and
documentation phases
are needed)
High unit cost of IC
(higher initial costs of
development)
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Types of ASIC
{
{
Full Custom
Semi Custom
z
z
{
Cell based
Gate Array
Programmable Logic
z
z
FPGA (Field Programmable Gate Array)
PLD (Programmable Logic Device)
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Full Custom ASICs
{
Some (or all) logic cells are customized
z
{
{
{
{
Demands longer design cycle
All mask layers are customized
Involves an implementation of a
completely new chip
Designer must be an expert in VLSI
design
It is used when:
z
z
z
existing cell libraries are not fast enough
logic cells not small enough or consume too
much power
technology migration (mixed-mode design)
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Examples of Full Custom ICs
{
{
{
{
Analog (e.g. Sensor, Actuator)
Mixed Analog/Digital (e.g.
Telecommunication)
High Voltage (e.g. Automobile)
Low Power (e.g. PDA, Mobile)
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Cell Based ASICs
{
{
Use predesigned logic cells (standard
cells) in combination with larger cells
(megacells)
Standard Cells
z
z
z
{
Primitive Gates (and, or, …)
Multiplexers
Registers
Mega cells (full-custom blocks, systemlevel macros, fixed blocks, cores,
functional standard blocks, or IP)
z
z
Microcontrollers, Microprocessor, MPEG
decoder
RAM, ROM
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Cell Based ASICs (cont.)
{
{
{
{
Designers save time, money, and
reduce risk
Each standard cell can be optimized
individually
All mask layers are customized
Custom blocks can be embedded
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Gate Array Based ASICs
{
Gate array (or prediffused array)
z
z
z
{
Masked gate array (MGA)
z
z
{
Transistors are predefined on the silicon wafer
Base array: the predefined pattern of transistors
Base cell: the smallest element that is replicated to
make the base array
Only the top few layers of metal are defined by the
designer using custom masks
The designer chooses from a gate-array library of
predesigned logic cells (macros)
Types of MGA ASICs
z
z
z
Channeled gate arrays
Channel-less gate arrays
Structured gate arrays
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Channeled Gate Array
{
{
Only the
interconnect is
customized
The interconnect
uses predefined
spaces between
rows of base cells
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Channel-less Gate Arrays
{
{
Also known as
sea-of-gate
(SOG)
only some mask
layers are
customized- the
interconnect
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Structured Gate Array
{
{
{
Combine some of
the features of
CBICs (Cell-Based
ICs) and MGAs
Only the
interconnect is
customized
Custom blocks can
be embedded
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