Digital System Design
Lecture 2: Design
Amir Masoud Gharehbaghi
[email protected]
Table of Contents
{
{
{
{
Design Methodologies
Overview of IC Design Flow
Hardware Description Languages
Brief History of HDLs
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Design Methodologies
{
Ad-hoc
{
Structured
z
z
z
Top-Down
Bottom-Up
Mixed
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Ad-hoc Design
{
Small Scale Designs
z
z
z
z
{
Come up with a block diagram
Place chips on board
Wire parts and components
Hope or Pray it works
Large Scale Designs
z
z
z
z
z
z
z
z
Partition Design
Develop Library
Configure Design
Test Partial Design
Develop More Libraries
Configure More Designs
...
Complete Design
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Why Structured Design?
{
Over a million-transistor designs
cannot be done easily
z
z
z
{
Today’s designs require better tools
Today’s designs require better planning
Today’s designs require better strategy
How to manage
z
z
z
Step-by-step design
Use of Simulation
Use of Synthesis
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Design Methodologies (cont.)
{
Top-Down
z
z
z
z
Refine Specification successively
Decompose each component into small
components
Lowest-level primitive components
Over-sold methodology - only works
with plenty of experience
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Design Methodologies (cont.)
{
Bottom-Up
z
z
z
Build-up from primitive components
Combined to form more complex
components
Risk wrong interpretation of
specifications
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Design Methodologies (cont.)
{
Mixed
z
z
Mostly top-down, but also bits of
bottom-up
Reality: need to know both top level
and bottom level constraints
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Overview of IC Design
Concept
From Concept
to Silicon
Algorithm Design
Architecture Design
Verification must be
done at each phase
Logic/Circuit Design
Physical Design
Tape-out
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Overview of IC Design (cont.)
{
Concept
z
{
Novel Idea or Product Concept
Algorithm Design
z
z
z
Proving Idea
Behavior Analysis
Algorithm Optimization &
Transformations
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Overview of IC Design (cont.)
{
Architecture Design
z
z
{
Design of Hardware Components
Optimization for Minimum Resource
Logic/Circuit Design
z
z
z
Design of Hardware Components
Tradeoffs among Area/Delay/Power
Further Improvements from logic-level
to circuit level
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Overview of IC Design (cont.)
{
Physical Design
z
z
z
z
Target to a Foundry Process
Layout according to Routing Layers
RC Model for Transistors
Initial Floorplan
Estimate Die Size
{ Estimate Routing Complexity
{
z
Finial Floorplan
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Overview of IC Design (cont.)
{
Tape-out
z
Fabrication Period
{
Gate Array
z
{
Full-Custom or Cell-Based
z
z
Routing Layers and Contacts are required
All Masks must be designed
A lot of test after manufacturing is
needed before design is ready for
market
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Overview of IC Design (cont.)
{
Verification
z
Validation of Design in each Phase
Formal
{ Simulation
{
z
z
Equivalence Checking between two
phases
Physical Design Verification
DRC: Design Rule Check
{ ERC: Electrical Rule Check
{ LVS: Layout vs. Schematic
{
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Hardware Description Languages
(HDLs)
{
{
Describe Hardware at different
levels of abstraction
Structural
z
z
{
Netlist of modules (hierarchical)
Textual replacement of Schematic
Behavioral/Functional
z
z
Describe what module does, not how
Use Synthesis to generate Hardware
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HDLs Specifications
{
Timing
Concurrency
{
Simulation Semantics
{
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Why Using HDLs?
{
{
Very difficult to design directly on
hardware
Exploring different design options
z
z
{
{
Easier
Cheaper
Lower time and cost than prototyping
CAD support from concept to silicon
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Key Features of HDLs
{
{
{
{
HDLs have high-level programming
language constructs
HDLs allow designers to describe
their designs at different levels of
abstraction
HDLs allow designers to describe
functionality as well as timing
HDLs are concurrent languages in
nature
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A Brief History of HDLs
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CDL
{
{
Computer Design Language
Developed in 1965
z
{
Simulator in 1975
Features:
z
z
z
z
Some high-level statements, condition
Simple logical and arithmetic
operations
Academic language (not industrial)
Data-flow level (no hierarchy support)
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ISPS
{
{
Instruction Set Processor Specification
First Idea in 1971
z
z
{
Single level of abstraction
z
z
{
ISPL in 1976
ISPS in 1981
Upper than data-flow
Processor instruction set
No hierarchy support
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AHPL
{
{
A Hardware Programming Language
Three versions:
z
z
z
{
AHPL-I:
AHPL-II:
AHPL-III:
1970
1978
1979
Features:
z
z
z
Data-flow and structural level
Full EDA tool support
Unfamiliar syntax
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VHDL
{
{
{
{
VHSIC HDL: Very High Speed
Integrated Circuit Hardware Description
Language
Initiated by DARPA (research center of
DoD) in a workshop in 1981
DARPA documentation released in 1983
VHDL 7.2 released in 1985
z
ITAR restrictions were lifted from VHDL
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VHDL (cont.)
{
IEEE Standard in 1987
z
{
{
ANSI Standard in 1988
Added Support for RTL Design
z
{
VITAL: VHDL Initiative Towards ASIC Library
Revised version in 1993
z
{
IEEE Std-1076-1987
IEEE Std-1076-1993
Final review added mixed-signal support
to VHDL in 2001 -> VHDL-AMS
z
IEEE Std-1076.1-2001
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Verilog
{
{
Verifying Logic
Phil Moorby from Gateway Design
Automation in 1984 to 1987
z
{
{
{
Absorbed by Cadence
Verilog-XL simulator from GDA in
1986
Synopsis Synthesis Tool in 1988
In 1990 became open language
z
OVI: Open Verilog International
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Verilog (cont.)
{
IEEE Standard in 1995
z
{
Last revision in 2001
z
{
IEEE Std-1364-1995
IEEE Std-1364-2001
Ongoing work for adding
z
z
Mixed-signal constructs: Verilog-AMS
System-level constructs: SystemVerilog
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VHDL vs. Verilog
{
{
{
{
All abstraction
levels
Designed for
documentation
ADA based
constructs
NO PLI
(Programming
Language
Interface)
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{
{
{
{
All Abstraction
Levels
Designed for
hardware design
C and ADA based
constructs
Powerful PLI
27
VHDL vs. Verilog (cont.)
{
{
{
{
{
Complex Grammar
Hard to learn for
beginners
Describe a system
(everything)
Lots of data types
High-level data
types
z
z
Pointer
Alias
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{
{
{
{
{
Easy Language
Easy to learn for
beginners
Describe digital
systems
Few data types
Hardware related
types
z
z
Wire
register
28
VHDL vs. Verilog (cont.)
{
{
{
{
User-defined
package and library
Reuse code from
package
Full design
parameterization
More easier to
handle large
designs
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{
{
{
{
No user-defined
packages
Reuse using
include
Simple
parameterization
No language
construct for
design file
handling
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VHDL vs. Verilog (cont.)
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