Automated Calibration, Test, and Burn-in System
Project Design Report
Design Team 10
Jonathan Adams
Mark Demko
Judicael Briand Djoko
Michael Kyagaba
Faculty Advisor: Dr. Carletta
Senior Design Coordinator: Gregory A. Lewis
12/20/2013
Table of Contents List of Figures ..................................................................................................................... ii List of Tables ..................................................................................................................... iii Abstract ............................................................................................................................... 1 Problem Statement .............................................................................................................. 2 Need ................................................................................................................................ 2 Objective ......................................................................................................................... 2 Background ..................................................................................................................... 3 Marketing Requirements ................................................................................................. 4 Objective Tree ................................................................................................................. 4 Design Requirements Specification .................................................................................... 6 Accepted Technical Design ................................................................................................ 7 Hardware ......................................................................................................................... 7 Software ........................................................................................................................ 20 Budget ............................................................................................................................... 29 Project Schedules .......................................................................................................... 30 Design Team Information ................................................................................................. 33 Conclusions and Recommendations ................................................................................. 34 References ......................................................................................................................... 35 i
List of Figures
Figure 1: Objective Tree ..................................................................................................... 4 Figure 2: Hardware Block Diagram Level 0....................................................................... 7 Figure 3: Hardware Block Diagram Level 1....................................................................... 9 Figure 4: Hardware Level 2: Input Analog Signal Processing ........................................... 9 Figure 5: Programmable Gain Amplifier .......................................................................... 10 Figure 6: Peak Hold Circuit .............................................................................................. 11 Figure 7: Peak Hold Circuit Frequency Response ............................................................ 12 Figure 8: Low Pass Filter Circuit ...................................................................................... 13 Figure 9: Frequency Response of Low Pass Filter ........................................................... 14 Figure 10: Master Schematics ........................................................................................... 18 Figure 11: Software Block Diagram Level 0 .................................................................... 20 Figure 12: Software Block Diagram Level 1 .................................................................... 21 Figure 13: Calibration Function ........................................................................................ 22 Figure 14: THD Test Function.......................................................................................... 24 Figure 15: Generate and Sample Function........................................................................ 24 Figure 16: Frequency Response Test Function ................................................................. 26 Figure 17: Noise Test Function......................................................................................... 27 ii
List of Tables
Table 1: Design Requirements ............................................................................................ 6 Table 2: Hardware Functional Requirements Level 0 ........................................................ 8 Table 3: Analog Input Signal Conditioning Functional Requirements .............................. 9 Table 4: Programmable Gain Amplifier Functional Requirements .................................. 10 Table 5: Peak Hold Functional Requirements .................................................................. 11 Table 6: Low Pass Filter Functional Requirements .......................................................... 12 Table 7: ADC Functional Requirements........................................................................... 14 Table 8: DSP Functional Requirements ............................................................................ 14 Table 9: DAC Functional Requirements........................................................................... 15 Table 10: Analog Output Signal Conditioning Functional Requirements ........................ 15 Table 11: Start Button Functional Requirements.............................................................. 15 Table 12: USB Interface Functional Requirements .......................................................... 15 Table 13: Serial Interface Functional Requirements ........................................................ 16 Table 14: Status LED Functional Requirements .............................................................. 16 Table 15: Parts List ........................................................................................................... 17 Table 16: Software Functional Requirements Level 0 ..................................................... 20 Table 17: Calibration Functional Requirements ............................................................... 22 Table 21: THD Test Functional Requirements ................................................................. 23 Table 18: Frequency Response Test Functional Requirements ........................................ 25 Table 20: Burn-in Functional Requirements..................................................................... 26 Table 19: Noise Test Functional Requirements ................................................................ 27 Table 22: Pass/Fail and Status Functional Requirements ................................................. 28 Table 23: Budget ............................................................................................................... 29 Table 24: Design Gantt Chart Part 1 ................................................................................. 30 Table 25: Design Gantt Chart Part 2 ................................................................................. 31 Table 26: Implementation Gantt Chart ............................................................................. 32 iii
Abstract
A test system will be created to automate the calibration and quality control testing
processes at FMR Audio. The system will operate a single RNC1773 or RNLA7239
audio compressor through the entire calibration, burn-in, and test process and will contain
all the instrumentation necessary to perform these functions. Multiple test stations will be
needed to keep up with the company’s production rate, so the test system must be
inexpensive and compact, while providing the accuracy necessary to assure quality
products are shipped.
1
Problem Statement
Need
FMR Audio is a small business that designs and manufactures professional audio
equipment. The company specializes in dynamic compression devices, including the
RNC1773 compressor and RNLA7239 leveling amplifier. Compression is an audio effect
that reduces the dynamic range of an audio signal. Compression is used during recording
to prevent clipping. During mixing, an individual track such as a snare drum may have
heavy compression applied to reduce the volume of each drum hit. The overall volume of
the track can then be increased to allow the reverberation of the drum and surrounding
room to be heard. Compression is also used in mastering, where rock and pop songs are
compressed heavily, then brought up to the maximum volume level of the media, in order
to produce the loudest average sound level possible.
FMR Audio typically produces 75 RNC1773 compressors or RNLA 7239 leveling
amplifiers each week. After each unit is assembled, it must be attached to an audio tester
so that a pair of potentiometers inside the unit can be set to an optimal level. This
calibration reduces the total harmonic distortion (THD) that the unit produces. If the
calibrated unit meets the THD specification, it is then tested for noise and frequency
response. Units that pass these tests are disconnected from the tester and hooked up in a
burn-in area. Burn-in lasts for at least a day followed by the units being connected to the
audio tester one last time to repeat the noise, frequency response, and THD tests. The
process of calibrating, testing, and burning in each unit requires a significant amount of
labor, which the company would like to reduce.
Objective
The goal is to design and build an automated system that tests, calibrates, and operates
audio equipment during an initial burn-in period at the end of the manufacturing process.
The audio equipment to be tested has been in production for a number of years, and
testing standards are already in place. To pass the testing phase, the total harmonic
distortion plus noise (THD+N) of the device must be less than 0.005% and noise must be
-95dBu or lower. The frequency response must be +/- 1dB from 10Hz to 120kHz, flat to
within 0.05dB from 10Hz to 20kHz, and flat to within 0.30dB from 20kHz to 120kHz.
These tests are currently conducted on each unit individually through the use of a
standalone audio analyzer. This is particularly labor intensive as each unit must be
connected and tests performed one by one. An automated test system must be capable of
performing the same tests that are currently performed manually. Additionally, a pair of
digital potentiometers inside the audio equipment is set manually to optimize the
harmonic distortion figure. The automated test system should automate this process as
well. Once tested, multiple units are connected in a manner similar to normal operation
and are allowed to run for a period of time to catch any early failures. The burn-in period
should be integrated into an automated test system so that units do not have to be moved
2
between stations. After the burn-in period is completed, the tests are repeated on each
unit individually to detect any units that may have failed during the burn-in period.
Automating this test, calibration, and burn-in process would save a significant amount of
labor which could be used to improve the business.
Background
Audio tests often require a significant amount of processing. In order to measure
harmonic distortion it is necessary to remove the fundamental frequency from the output.
While this can be accomplished to some degree with analog circuits, a digital signal
processor allows for a more accurate implementation. A digital signal processor is a
specialized microprocessor that is highly optimized to process digital representations of
analog signals in real time [1]. The use of a digital signal processor allows not only for
accurate measurement, but can also be a convenient source of test signals with which to
test the device.
Because the device to be tested has low noise and distortion figures, it is important that
the testing device have better performance in these regards. Noise in the system will
come from two main areas: component noise and received electromagnetic radiation. All
resistors in the signal path will generate thermal noise. Flicker noise will be created by a
wide variety of devices, particularly carbon resistors. The use of metal film resistors will
allow for the lowest flicker noise. Burst noise can be caused by metallic impurities in p-n
junctions, so it may be necessary to specify high quality transistors, diodes, and
integrated circuits in the design [2]. Electromagnetic noise will be caused by external
fields as well as between various circuits within the design. By thoughtfully designing
circuit board traces and ground planes, electromagnetic interference between circuits can
be reduced. This includes separating analog and digital portions of the design and
keeping the traces of differential pairs close to each other to reduce loop area. Noise from
external sources can be reduced by providing proper filtering to incoming power lines,
enclosing the board in a metallic enclosure, and using shielded cables for all connections
outside of the enclosure [3].
Once the testing capability is designed, it should be possible to automatically calibrate the
device under test in order to minimize the harmonic distortion. Automatic calibration to
reduce distortion is not a new idea. Lucent Technologies holds a patent for a system that
can automatically calibrate a high frequency amplifier to reduce inter-modulation
distortion [4]. The optimization of harmonic distortion could be achieved through an
iterative process of adjusting digital potentiometers and measuring the resulting harmonic
distortion. While it may be possible to develop more advanced algorithms to predict an
optimal setting, this may not be necessary. If the testing and calibration system can be
economically duplicated, it will be possible to perform calibration, burn-in, and testing of
a unit in a single bay, while providing enough bays to achieve a desired throughput. Since
3
the burn-in period is primarily achieved by operating the device for a given period of
time, any extra time spent in calibration could be counted as part of the burn-in process.
Marketing Requirements
• Calibration
o Program digital potentiometers in device under test
o Test to determine optimal setting
• Burn-in
o Power the device and provide audio signals
o Allow for economical scaling to compensate for long burn-in time
• Test
o Measure frequency response in a range of at least 10Hz-120kHz with a
resolution of 0.05dB or better
o Measure THD+N to 0.005% or lower
o Measure noise to less than -95dBu
• Scalable
o Economical enough to allow a large number of stations to be built
o Compact enough to allow a large number of stations in a limited space
• Reduce labor
Objective Tree
Test System
Test Product
Calibrate Product
Burn-in Product
Scalable
Measure THD
Interface to Existing
Product
Compact
Measure Noise
Calibrate for
Optimal THD
Economical
Measure
Frequency
Response
Figure 1: Objective Tree
4
Reduce Labor
Figure 1 shows the objectives of the test system to be designed. In order to test the
performance of the product, the test system must measure total harmonic distortion
(THD), noise, and frequency response. In order to calibrate the product, the test system
must interface to the product over an existing interface that is specified by FMR Audio.
The test system must be capable of determining the optimal digital trim pot settings to
allow the product to operate with the lowest possible THD. The test system must also
operate the device under test for an extended period of time and verify that it is still
operating within specifications at the end of that period. In order to reduce labor, it is
desirable to create a system that remains connected to the device under test for the entire
test, calibration, and burn-in period. Since this process takes multiple days, it is necessary
to design the test system in such a way that it can be reproduced in large enough quantity
to match the company’s production rate. Since FMR Audio typically produces 75
RNC1773 or RNLA7239 units each week and would like to provide 48 hours of burn-in,
they will require at least 25 test systems. The production cost of each test system should
be as low as possible to provide a short pay-off period. These units must also not occupy
a large amount of space in FMR Audio’s production facility.
5
Design Requirements Specification
Marketing
Requirements
1
2
Engineering Requirements
Justification
The combined total harmonic distortion of
the test signal generation and THD
measurement circuits should be less than
0.001%.
The noise floor of the test system in noise
measurement mode must be ≤−100dBu.
The test system must have less
distortion than the device to be
tested.
3
The frequency response of the test system
must be repeatable to within ±0.01dB.
1,3
The test system is capable of generating a
sinusoidal test signal with a frequency of
10Hz-120kHz.
The generated test signal has a THD of
less than 0.001% at 0dBu
1,3
4
The dimensions of the test system must be
less than 2”H x 8”W x 24”D.
4
The test system must generate
less noise than the device to be
tested.
The test system must be
capable of measuring the
frequency response of the
device.
This signal is required to test
frequency response.
The signal must have less
harmonic distortion than the
device under test in order to
accurately measure this figure.
At least 25 test units must fit
on a table or rack and occupy
as little space as possible.
It must be economical to build
at least 25 test units.
Reduce the labor required to
calibrate the device.
The test system must have a production
cost less than $400.
5,6
The test system must be capable of setting
the digital trim potentiometers on the
RNC1773 or RNLA7239 to a setting that
produces the lowest possible THD.
6
The test system must operate without any
Reduce the labor required to
operator intervention during the
test the device.
calibration, test, and burn-in cycle.
6,7
The test system must power the device
Burn-in is a proven method for
under test for the duration of the burn-in
catching early failures in a
period.
product.
Marketing Requirements
1. Measure THD+N to 0.005% or lower
2. Measure noise to less than -95dBu
3. Measure frequency response to the customer’s specification ±0.05dB flatness(10Hz20kHz) ±0.3dB flatness (20kHz-120kHz)
4. The test system must be scalable to meet the production rate of the customer.
5. Calibrate the device under test.
6. Reduce labor
7. Burn-in product
Table 1: Design Requirements
6
Accepted Technical Design
Hardware
The test system connects to an FMR Audio RNC1773 or RNLA7239 audio compressor
as shown in Figure 2. The test system provides test signals to the device under test in the
form of single frequency sine waves, swept sine waves, and silence. The test system
receives a response back from the device under test that includes the original test signal,
plus any noise, distortion, and non-linearity. The software shown in Figure 11 evaluates
the received audio signal to measures noise, harmonic distortion, and frequency response
magnitude. The software is also responsible for generating the sine wave that is sent to
the compressor. The digital trim potentiometers on the audio compressor are adjusted and
harmonic distortion tests are repeated until an optimal setting is found. The test system
operates the compressor for a burn-in period, and then repeats the tests to verify the
proper operation of the device under test. Test results are sent to a computer for storage
and the pass/fail status of the compressor is displayed to the operator.
Computer
USB
Power
Test System
Response to
Test Signal
Digital Bus
(trim pots)
Test Signal
Device Under Test
(Audio
Compressor)
Figure 2: Hardware Block Diagram Level 0
7
Module
Inputs
Outputs
Functionality
Designer
Test System
• Power
• Response to Test Signal
• Test Signal
• USB
• Device bus
Measure the audio performance of the FMR Audio
RNC1773 and RNLA7239. Calibrate device under
test for optimal performance. Operate device under
test for burn-in period and verify the unit is still
operational.
Mark Demko, Michael Kyagaba, Jonathan Adams
Table 2: Hardware Functional Requirements Level 0
The level 1 hardware block diagram is shown in Figure 3. The incoming analog signal
contains high frequency noise that is not of interest to our test system. This noise must be
filtered out by the analog input signal conditioning block (Table 3) to avoid aliasing in
the ADC (Table 7). Additional analog conditioning is possible to greatly reduce the
sample rate and sample size requirements for each test. The DSP (Table 8) processes the
incoming signal to measure the relevant parameters for the tests, generates the test signal
that will be fed to the product, receives user input to start the test cycle, and outputs trim
pot settings, test status, and a test report. The DAC (Table 9) converts the digital test
signal to an analog signal. The analog sine wave is not smooth when it exits the DAC, but
consists of small stair steps due to the discrete times and values represented in the digital
system. This signal must be smoothed by an output filter (Table 10).A serial interface
(Table 13) allows the system to send trim pot settings to the device being calibrated. A
USB interface (Table 12) allows the test system to report the test results to an attached
computer for logging. The start button (Table 11) allows the operator to start a test cycle
once the device has been connected. The status LED (Table 14) will light different colors
and blink to indicate pass, fail, and test progress.
8
Analog Input
Signal
Conditioning
Start Button
USB interface
Status LED
ADC
DSP
DAC
Analog
Output Signal
Conditioning
Serial
Interface
Figure 3: Hardware Block Diagram Level 1
Module
Inputs
Outputs
Functionality
Designer
Analog Input Signal Conditioning
Analog signal from device under test
Analog signal or value to ADC
Perform analog signal processing to overcome
limitations of the ADC.
Jonathan Adams
Table 3: Analog Input Signal Conditioning Functional Requirements
Peak Hold
Programmable
Gain Amplifier
~25kHz Low Pass
FIlter
Figure 4: Hardware Level 2: Input Analog Signal Processing
9
Module
Inputs
Outputs
Functionality
Designer
Programmable Gain Amplifier
Analog test signal
Scaled Analog test signal
Provide input gain selection. For noise measurements,
significant gain will be applied to bring the noise of the
device under test into a measure
Jonathan Adams
Table 4: Programmable Gain Amplifier Functional Requirements
Figure 4 is a hardware level 2 block diagram showing the analog input signal processing.
The analog input signal conditioning block consists of a programmable gain amplifier,
peak hold circuit, and low pass filter which prepare the incoming signal for analog to
digital conversion. The programmable gain amplifier (Table 4) allows the test system to
select a level of gain to be applied to the incoming signal. The programmable gain
amplifier consists of a TLC7528 multiplying digital to analog converter (MDAC) and an
OPA2227 operational amplifier as shown in Figure 5. During frequency response and
THD tests, the programmable gain amplifier will be set to provide the ADC with a signal
that is close to full scale without clipping.
Figure 5: Programmable Gain Amplifier
During the noise test, significantly more gain will be applied to bring the incoming noise
signal into up to a measurable level. Since this block must amplify a very small noise
signal, it is necessary to design it to produce very little noise. An important source of
noise is the current and voltage noise density of the operational amplifier which converts
the current output of the MDAC into a voltage. For ease of analysis, this noise is referred
to the input of the op-amp and is given by Equation 1 where n is the noise in dBu.
10
𝑛 = 20× log
𝑒! × 𝐵𝑊 + 𝑖! × 𝐵𝑊×𝑍!"#
0.775V
Equation 1: Noise Calculation
For the OPA2227 dual op-amp, the voltage noise density (en) is 3.5 nV/√Hz. Over a
20kHz bandwidth (BW), this produces 495nV of noise. The current noise density (in) of
the OPA2227 is 0.4 pA/√Hz. Over a 20kHz bandwidth, this produces 57pA of noise,
which will produce a 1.13 µV voltage drop across the 20kΩ output impedance (Zout) of
the MDAC. Adding the voltages from both sources of noise, there is 1.626µV of noise,
which corresponds to -113 dBu.
Module
Inputs
Outputs
Functionality
Designer
Peak Hold
Analog test signal
Peak value of test signal
Provide an analog voltage that relates to the peak value
of the input waveform.
Michael Kyagaba
Table 5: Peak Hold Functional Requirements
Figure 6: Peak Hold Circuit
One method of measuring the amplitude of a signal for the frequency response test is to
measure the peak value of the waveform. When attempting to measure the peak of a
waveform with a simple ADC, significant oversampling is required in order to ensure a
sample is taken sufficiently close to the peak. The test criteria state that the test system
must measure frequency response up to 120kHz, which would require a sample rate on
the order of 2.4MHz. An ADC and DSP which could support such a high sample rate
would greatly increase the cost of the test system.
The peak hold circuit (Table 5, Figure 6) takes in a sinusoidal test signal and outputs a
voltage that represents the peak value of the incoming signal. This allows the test system
to sample at a low rate, reducing the cost of the system. During the peak of the waveform,
D1 conducts and charges the capacitor. When the input decreases, D1 stops conducting
and the capacitor maintains the voltage. Due to the very high input impedance of the opamp and low leakage current of the diode, the capacitor discharges very slowly. Without
11
D2, the first op-amp would operate open loop over most of the input signal’s duty cycle.
This would cause the output to slew to the negative rail. At high frequencies, this
becomes a problem as the output is unable to slew to the input signal’s peak value fast
enough. The addition of D2 pulls down the inverting input of the first op-amp whenever
D1 is not conducting, which keeps the op-amp in a closed loop operation at all times.
This causes the output to track the non-inverting input at all times and allows the circuit
to provide a relatively flat frequency response across a wide range of frequencies as
shown in Figure 7.
0 10 100 1000 10000 100000 1000000 -­‐0.2 -­‐0.4 -­‐0.6 -­‐0.8 -­‐1 -­‐1.2 Figure 7: Peak Hold Circuit Frequency Response
Module
Inputs
Outputs
Functionality
Designer
Low Pass Filter
Analog test signal
Analog test signal
Filter out high frequencies to avoid aliasing.
Mark Demko
Table 6: Low Pass Filter Functional Requirements
Aliasing is a concern whenever an ADC is used. A low pass filter (Table 6) is necessary
to reduce frequencies above half the sample rate to an acceptable level. An ideal low pass
filter attenuates the signal by 20dB per order per decade above the corner frequency. For
a low pass filter of order n, corner frequency f0, and sampling frequency fs, the
attenuation, A, at the Nyquist frequency can be calculated as shown in Equation 2.
12
𝐴 = 𝑛×20× log!"
2×𝑓!
𝑓!
Equation 2: Nominal Attenuation of Low Pass Filter
Real filters are not ideal, but attenuate the signal to some degree below the corner
frequency. At the corner frequency, the signal is attenuated by 3dB. For this reason, it is
necessary for the corner frequency of the filter to be higher than the highest desired
frequency if a flat response is required. A 25kHz 4th order low pass filter feeding a
256kHz ADC will provide approximately 56dB of attenuation at the Nyquist frequency.
Figure 8: Low Pass Filter Circuit
Figure 8 shows the low pass filter selected for this design. The filter is a second order
multiple feedback topology designed for a corner frequency of 20 kHz. Substituting for
standard values of 5% resistors and 10% capacitors yields a corner frequency of 20.5
kHz. The results of the low pass filter are shown in Figure 9. Analysis of the worst case
resistor and capacitor values shows that this circuit will yield a corner frequency between
17.7 kHz and 23.9 kHz. With the same 256 kHz sample frequency as the previous
example, the worst case corner frequency of 23.9 kHz gives only 19dB of attenuation at
the Nyquist frequency. If the input signal had significant high frequency content, aliasing
would certainly be a problem. When measuring Harmonic distortion, the incoming signal
has very little content above 1 kHz. The signal consists of a 1 kHz test signal at 0dBu,
harmonics which add up to less than -43dBu, and broadband noise at -95dBu or less.
Because of the nature of this signal, a steep low pass filter is not necessary. During the
noise test, some aliasing will be present. However, the signal sampled during this test is
simply random noise and aliasing will have little effect on the results.
13
5 0 -­‐5 -­‐10 -­‐15 -­‐20 -­‐25 -­‐30 -­‐35 1000 10000 100000 Figure 9: Frequency Response of Low Pass Filter
Module
Inputs
Outputs
Functionality
Designer
ADC
Analog signal
Digital representation of analog signal
Convert the analog signals into digital values at a certain
sample rate. This is a single component.
Michael Kyagaba
Table 7: ADC Functional Requirements
Module
Inputs
Outputs
Functionality
Designer
DSP
Digital representation of analog signal
Start button
Sine wave values or parameters
Status light signals
Serial data to trim pots
USB data to computer
Calculate noise, harmonic distortion, and frequency
response from captured signals. Generate values of test
signals. Select appropriate analog signal processing for
a given task. Select trim pot values based on tests. Send
test results to an external system for logging. This is
likely a single DSP chip.
Michael Kyagaba
Table 8: DSP Functional Requirements
14
Module
Inputs
Outputs
Functionality
Designer
DAC
Digital values or parameters for sine wave
Analog sine wave or null
Output a sine wave at a constant or varying frequency as
instructed by the DSP for THD and frequency response
tests. No output for noise test. This is likely a single
component.
Mark Demko
Table 9: DAC Functional Requirements
Module
Inputs
Outputs
Functionality
Designer
Analog Output Signal Conditioning
Analog test signal
Analog test signal
Reconstruct the stepped output of the DAC into a
smooth sine wave. Apply necessary gain to the signal.
Mark Demko
Table 10: Analog Output Signal Conditioning Functional Requirements
The ADC (Table 7), DSP (Table 8), USB interface (Table 12), and serial interface (Table
13) are all contained within the dsPIC33EP256MU806 device selected for this project.
The PCM5100 DAC perform all the DAC functionality (Table 9). Additionally, the
PCM5100 is designed to be used with a simple first order RC low pass filter as the only
output signal processing (Table 10). In order to simplify programming, the status LED
(Table 14) is comprised of 8 individual red/green LEDs, one for each major step in the
test system’s operation. By turning on red and green simultaneously, an amber color can
be created to indicate that a step is running.
Module
Inputs
Outputs
Functionality
Designer
Start Button
Button Press
Digital signal
Single component. Allow the operator to start the test
cycle.
Michael Kyagaba
Table 11: Start Button Functional Requirements
Module
Inputs
Outputs
Functionality
Designer
USB Interface
USB data
USB port
Format data for transmission over a USB cable. Single
component or integrated into DSP.
Michael Kyagaba
Table 12: USB Interface Functional Requirements
15
Module
Inputs
Outputs
Functionality
Designer
Serial interface
Trim pot value
Trim pot value, formatted for serial transmission
Format trim pot value for serial transmission to device
under test. Single component or integrated into DSP.
Michael Kyagaba
Table 13: Serial Interface Functional Requirements
Module
Inputs
Outputs
Functionality
Designer
Status LED
2 digital signals
Red, green, yellow light
Light to indicate the status of a test station to the
operator. Green for pass, red for fail. Yellow for
running. Each test will have a separate LED so that
failures can easily be traced to a particular test.
Michael Kyagaba
Table 14: Status LED Functional Requirements
16
Parts (Table 15) were selected for a combination of cost, manufacturability, and reuse of
the customer’s existing inventory while still meeting the performance requirements of the
design project.
Qty.
1
1
1
3
1
3
2
8
4
2
2
6
2
2
1
16
2
4
15
2
2
1
1
3
2
1
1
4
4
1
1
6
1
1
1
1
1
Refdes
U1
U2
U3
U4, U5, U6
U6
U7-U9
D1, D2
D3-D10
R1, R3, R4, R6
R2, R5
R7, R8
R9, R11
R10, R12
R13, R14
R15
R16-R31
C1, C3
C2, C4, C5, C6
C7-C21
C22, C23
C24, C25
C26
C27
C28-C29
C30,C31
SV1
X1
SL1
K1
L1
Part Num.
dsPIC33EP256MU806
TLC7528CPW
OPA2228UA
TL072
PCM5100PWR
FT531JA
BAV23S
LTST-C155KGJRKT
RMCF0805JT330R
RCMF0805JT390R
RMCF0805JT20K0
RMCF0805JT100K
RMCF0805JT1K00
RC0805JR-07470RL
CR0805-JW-103ELF
RC0805FR-07162RL
C0805C473D5RACTU
C0805C103K5RACTU
CC0805KRX7R9BB104
CC0805ZRY5V7BB225
C0805C222K5RACTU
C2012Y5V1A106Z
EEE-1EA100NP
EMZA230ADA331MJA0G
ECH-U1C104GX5
98002-205HLF
USB2983-ND
NRJ6HF
NYS237
640457-6
1375820-6
1375819-1
SS-300ET
TQ2-5V
MCP1416T-E/OT
KSL0M212LFT
ELJ-FA2R7JF
Description
DSP
8-bit MDAC
Dual Op Amp
Dual Op Amp
384kHz DAC
3.3V regulator
Dual Diode
Red/Green LED
330R 5% 0805
390R 5% 0805
20k 5% 0805
100k 5% 0805
1k 5% 0805
470R 5% 0805
10k 5% 0805
162R 1% 0805
0.047uF 0805
0.01uF 0805
0.1uF 0805
2.2uF 0805
2.2nF 0805
10uF 0805 Ceramic
10uF Electrolytic
330uF Electrolytic
0.1uF Poly 1210
5 pin programming header
USB B jack
1/4" jack, stereo
1/4" adapter
6 pin power header
6 pin power connector
Crimp pin
Power Supply
Relay
MOSFET driver
Pushbutton
2.7uH Inductor
Table 15: Parts List
17
Figure 10: Master Schematics
18
19
Software
Test Report
Response to
Test Signal
Test System
Software
Synthesized
Test Signal
Trim Pot Setting
Figure 11: Software Block Diagram Level 0
Module
Inputs
Outputs
Functionality
Designer
Test System Software
• Response to Test Signal
• Synthesized Test Signal
• Test Report (USB)
• Trim Pot Setting
Generate test signals and measure returned audio signals.
Calculate noise, harmonic distortion, and amplitude frequency
response from measured data. Adjust digital trim pot setting
and repeat harmonic distortion measurement until lowest
harmonic distortion is achieved. Repeat tests at end of burn-in
period. Send results to computer system for logging. Report
the status to the operator during the test cycle.
Judicael Djoko, Jonathan Adams
Table 16: Software Functional Requirements Level 0
20
Start
Trim Pot Setting
Response
Calibration
Test Signal
Status LED
Response
Frequency
Response
Test Signal
Status LED
Mute Test Signal
Response
Noise
Status LED
Burn-In
Response
Frequency
Response
Status LED
Test Signal
Status LED
Mute Test Signal
Response
Noise
Status LED
Response
Total
Harmonic
Distortion
Test Signal
Status LED
Test Report
Pass/Fail, Status
Status LED
Figure 12: Software Block Diagram Level 1
21
Figure 12 shows the level 1 software of the test system and typical flow of the software.
At the start of a test cycle, the test system will calibrate the device under test (Table 17).
This block will iterate through settings of the digital trim pots to find the setting that
produces the lowest level of harmonic distortion. This setting will be saved to the device
under test and the harmonic distortion level achieved will be passed to the status block.
Module
Inputs
Outputs
Functionality
Designer
Calibration
Test signal
Test signal parameters
Digital trim pot setting
Best THD figure achieved
Iterate through digital trim pot settings. Call the THD
test function for each trim pot setting. Select the setting
with the lowest THD and program the device under test.
Report the THD level achieved at the optimal trim pot
setting.
Judicael Djoko
Table 17: Calibration Functional Requirements
Start
N=0
Set trimpot = N
N=N+1
THD
Calculation
Store THD value
N < Max
number of
iterations
Set trimpot with
lowest THD value
Report lowest THD
value
End
Figure 13: Calibration Function
The calibration function (Figure 13) iteratively sets each possible trim pot setting and
calls the THD test function (Figure 14). The THD test function generates a 1 kHz
22
sinusoidal signal. The device under test creates distortions which appear as harmonics at
multiples of the 1 kHz test signal. The THD test function calculates a discrete Fourier
transform on the sampled response signal for frequencies that are multiples of 1 kHz. The
function then adds up the power of each harmonic frequency and returns the total as a
percentage of fundamental frequency power. If THD is a concave up function of the trim
pot setting, it may be possible to optimize this function by taking course steps through the
trim pot settings, then testing fine steps through a more limited range of trim pot settings.
The trim pot setting which achieves the best THD level is then stored in the device under
test and the best THD result is returned.
Research and simulation of the discrete Fourier transform has shown that the frequency
bins will not exhibit ideal filter behavior if the sampled waveform does not contain an
integer number of the frequency in the bin. Instead, frequency bins measure frequencies
outside their range, albeit at reduced amplitude. Under normal conditions, this could
cause a large problem since the 1kHz fundamental in the THD test is many orders of
magnitude larger than the harmonics being measured. Simulations show that a 0.0006%
THD system could be measured as 14% THD in such a case. This can be avoided if the
signal generator and analog to digital converter are synchronized and the sample time is
carefully calculated. If done properly, the discrete Fourier transform is performed on an
integer number of cycles of the 1 kHz test signal and the frequency bins perform as ideal
filters [5].
Module
Inputs
Outputs
Functionality
Designer
Total Harmonic Distortion Test
Test signal
Test signal parameters
THD figure
Instruct the test signal generator to produce a 1kHz sine
wave. Process a Fourier transform on the returned
signal. Sum the power of the frequency bins that contain
harmonics of 1kHz. Report the summed power as a
percentage of the power of the fundamental frequency.
Judicael Djoko
Table 18: THD Test Functional Requirements
23
Start
Generate 1kHz sine wave
Sample returned signal
Discrete Fourier
transform
Calculate THD and
return value
End
Figure 14: THD Test Function
Each test requires the test system to generate a sinusoidal signal or silence and
simultaneously sample the response. Since this functionality is used often and requires
critical timing in order to output the proper frequency, it is worthwhile to have a function
that performs these tasks. Figure 15 shows the generate and sample function. It takes in
arguments of amplitude (A), frequency (f), number of samples (i), and input channel (c)
to sample. The samples are stored in a global value for use by the test.
Start
i=0
DAC = A*cos(i*f)
i = i+1
sample(i) =
ADC(c)
Wait for timer
i < number of
samples
End
Figure 15: Generate and Sample Function
24
If the calibration function returns an acceptable result, the software will continue to the
frequency response test (Table 19). This test will cause a series of sine waves at various
frequencies to be passed through the device under test. The test will receive the peak
voltage of each returned test signal and report the frequency response magnitude of the
device under test. Upon successful completion of the frequency response test, the noise
test (Table 21) will be performed. This test instructs the signal generator to output
silence. The signal from the device under test is greatly amplified and passed to the noise
test block as a series of digital samples. The noise test block calculates the signal power
and reports this figure to the status block.
Module
Inputs
Outputs
Functionality
Designer
Frequency Response Test
Peak voltage of test signal
Test signal parameters
Frequency response
Iterate through test frequencies from 10Hz to120kHz.
Take multiple samples of the peak voltage of the
returned test signal and average. Convert the peak
voltage to a signal power referenced in dBu. Report the
frequency response magnitude of the device under test.
Michael Kyagaba
Table 19: Frequency Response Test Functional Requirements
The frequency response function (Figure 16) iteratively generates sinusoidal test and
measures the returned power level based on the peak value from the peak-hold circuit.
The frequency response must be measured from 10 Hz to 120 kHz. The test frequencies
in this range are incremented exponentially and are stored in a lookup table.
25
Start
N=0
Generate sine wave at
lookup(N) Hz.
Sample peak value
N = N+1
Store signal power
Lookup(N) <
120kHz
Return results
End
Figure 16: Frequency Response Test Function
With all initial testing complete, the test system waits in the burn-in block (Table 20) for
a period of time. During this period, the device under test is allowed to operate in an
attempt to flush out any early failures.
Module
Inputs
Outputs
Functionality
Designer
Burn-in
None
None
Allow the device under test to operate for a period of
time.
Judicael Djoko
Table 20: Burn-in Functional Requirements
26
After the burn-in period, the test system repeats the frequency response and noise tests
and performs a THD test (Table 18) to verify the device under test is still functioning
within specifications. The THD test instructs the signal generator to output a 1kHz sine
wave. It then performs a Fourier transform on the returned signal. Frequency bins that
contain harmonics of the fundamental frequency are summed together. This summed
value represents the signal power of the harmonic distortion generated by the device
under test. This figure is returned as a percentage of the fundamental power.
Module
Inputs
Outputs
Functionality
Designer
Noise Test
Amplified Test signal
Test signal parameters
Noise figure
Instruct the test signal generator to output silence.
Sample the returned signal over a sample window.
Calculate the signal power in dBu. Report the signal
power.
Mark Demko
Table 21: Noise Test Functional Requirements
The noise test function (Figure 17) measures the noise generated by the device under test
with no input signal. Once a certain number of noise samples are stored in memory, the
function iterates through each sample point and adds the square of the sample value to an
accumulated value. After all samples are accumulated, the accumulated value is
converted to a noise figure in dB which the noise test function returns.
Start
N=0
Generate Silence.
Sample returned signal
N = N+1
Accumulate
square of sample
value
N < number of
samples
Return noise figure
End
Figure 17: Noise Test Function
27
The pass/fail and status block (Table 22) takes the results of the tests and formats the data
for transmission to the attached computer. Each step of the process also provides
feedback to the operator through status LEDs. Each block will report a status of running,
pass, or fail, which will light its respective status LED a particular color. This will allow
the operator to view the progress of the test cycle and quickly identify which test failed.
Once the test system has passed or failed the device under test, the status block will
generate a test report to send to an attached computer. This test report will be archived for
on the computer for statistical analysis and may be used to troubleshoot failures.
Module
Inputs
Outputs
Functionality
Designer
Pass/Fail and Status
THD test results
Frequency Response test results
Noise test results
Status LED
Test report
Compare returned test results to pre-determined test
criteria. Display the pass/fail status or test progress on
the status LED. Send a test report to an attached
computer at the end of the test cycle.
Jonathan Adams
Table 22: Pass/Fail and Status Functional Requirements
28
Budget
With all parts selected, the project is still well under budget.
Qty.
1
1
1
3
1
3
2
8
4
2
2
6
2
2
1
16
2
4
15
2
2
1
1
3
2
1
1
4
4
1
1
6
1
1
1
1
1
1
Part Num.
dsPIC33EP256MU806
TLC7528CPW
OPA2228UA
TL072
PCM5100PWR
FT531JA
BAV23S
LTST-C155KGJRKT
RMCF0805JT330R
RCMF0805JT390R
RMCF0805JT20K0
RMCF0805JT100K
RMCF0805JT1K00
RC0805JR-07470RL
CR0805-JW-103ELF
RC0805FR-07162RL
C0805C473D5RACTU
C0805C103K5RACTU
CC0805KRX7R9BB104
CC0805ZRY5V7BB225
C0805C222K5RACTU
C2012Y5V1A106Z
EEE-1EA100NP
EMZA230ADA331MJA0G
ECH-U1C104GX5
98002-205HLF
USB2983-ND
NRJ6HF
NYS237
640457-6
1375820-6
1375819-1
SS-300ET
TQ2-5V
MCP1416T-E/OT
KSL0M212LFT
ELJ-FA2R7JF
PCB
Description
DSP
8-bit MDAC
Dual Op Amp
Dual Op Amp
384kHz DAC
3.3V regulator
Dual Diode
Red/Green LED
330R 5% 0805
390R 5% 0805
20k 5% 0805
100k 5% 0805
1k 5% 0805
470R 5% 0805
10k 5% 0805
162R 1% 0805
0.047uF 0805
0.01uF 0805
0.1uF 0805
2.2uF 0805
2.2nF 0805
10uF 0805 Ceramic
10uF Electrolytic
330uF Electrolytic
0.1uF Poly 1210
5 pin programming header
USB B jack
1/4" jack, stereo
1/4" adapter
6 pin power header
6 pin power connector
Crimp pin
Power Supply
Relay
MOSFET driver
Pushbutton
2.7uH Inductor
Table 23: Budget
29
Unit
Cost
$9.19
4.70
5.85
0.12
2.73
0.40
0.23
0.42
0.03
0.03
0.03
0.03
0.03
0.00
0.01
0.00
0.10
0.01
0.01
0.12
0.15
0.15
0.13
0.32
1.09
0.27
0.54
0.59
1.69
0.42
0.33
0.10
39.99
3.45
0.77
0.54
0.09
33.00
Total
Total
Cost
$9.19
4.70
5.85
0.35
2.73
1.20
0.46
3.36
0.12
0.06
0.06
0.18
0.06
0.00
0.01
0.04
0.20
0.04
0.14
0.24
0.30
0.15
0.13
0.97
2.18
0.27
0.54
2.36
6.76
0.42
0.33
0.60
39.99
3.45
0.77
0.54
0.09
33.00
$121.85
Project Schedules
Table 24: Design Gantt Chart Part 1
30
ID
Task Name
Duration
Start
Finish
Predecessors
Resource Names
Oct 14, '12
W
59
Project Poster
11 days Mon 10/15/12
60
61
Final Design Report
30 days Mon 10/15/12 Wed 11/14/1217
Jonathan Adams
30 days Mon 10/15/12 Wed 11/14/12
30 days Mon 10/15/12 Wed 11/14/12
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
Abstract
Softw are Design
Development Environment Setup
ADC and DAC Functionality
Signal Generation and Sampling
THD Test Algorithm
Status, and Reporting
Pseudo Code
Burn-in
Pseudo Code
Hardw are Design
MDAC and Gain
Simulations
Schematics
Peak Hold
Simulations
Schematics
Anti-aliasing Filter
Simulations
Schematics
DSP (inc. USB, serial, ADC)
Simulations
Schematics
DAC
Simulations
Schematics
Output LPF
Simulations
Schematics
UI
Schematics
Parts Request Form
Budget (Estimated)
Implementation Gantt Chart
Conclusions and Recommendations
Final Presentation
11 days
7 days
7 days
5 days
14 days
14 days
14 days
14 days
30 days
22.63 days
7 days
7 days
30 days
7 days
30 days
22.63 days
7 days
7 days
22 days
7 days
7 days
22 days
7 days
7 days
22 days
7 days
7 days
7 days
7 days
30 days
30 days
30 days
30 days
15 days
Final Design Presentation Part 1 3:15PM ASEC0 120
days
Final Design Presentation Part 2 3:15PM ASEC0 120
days
Final Design Presentation Part 3 3:15PM ASEC0 120
days
Mon 10/15/12
Fri 10/26/12
Fri 11/2/12
Fri 11/9/12
Mon 10/15/12
Mon 10/15/12
Wed 10/31/12
Wed 10/31/12
Mon 10/15/12
Mon 10/15/12
Mon 10/15/12
Wed 10/31/12
Mon 10/15/12
Mon 10/15/12
Mon 10/15/12
Mon 10/15/12
Mon 10/15/12
Wed 10/31/12
Tue 10/23/12
Tue 10/23/12
Wed 11/7/12
Tue 10/23/12
Tue 10/23/12
Wed 11/7/12
Tue 10/23/12
Tue 10/23/12
Wed 11/7/12
Wed 11/7/12
Wed 11/7/12
Mon 10/15/12
Mon 10/15/12
Mon 10/15/12
Mon 10/15/12
Wed 10/31/12
Fri 11/16/12
Fri 11/30/12
Fri 12/7/12
Fri 10/26/1217
Fri 10/26/12
Judicael Briand Djoko
Fri 11/2/12 64 Judicael Briand Djoko
Fri 11/9/12 65 Judicael Briand Djoko
Wed 11/14/12 66
Mon 10/29/12
Mon 10/29/12
Wed 11/14/12
Wed 11/14/12
Wed 11/14/12
Wed 11/7/12
Mon 10/22/12
Wed 11/7/12
Wed 11/14/12
Mon 10/22/12
Wed 11/14/12
Wed 11/7/12
Mon 10/22/12
Wed 11/7/12
Wed 11/14/12
Tue 10/30/12
Wed 11/14/12
Wed 11/14/12
Tue 10/30/12
Wed 11/14/12
Wed 11/14/12
Tue 10/30/12
Wed 11/14/12
Wed 11/14/12
Wed 11/14/12
Wed 11/14/12
Wed 11/14/12
Wed 11/14/12
Wed 11/14/12
Thu 11/15/12
Jonathan Adams
Jonathan Ad
Judicael Bria
Jonathan Ad
Judicael Briand Djoko
Jonathan Adams
Jonathan Adams
Jonathan Ad
Michael Kyagaba
Michael Kyagaba
Michael Kyag
Michael Kyag
Mark Demko
Mark Demko
Mark Demko
Michael Kyagaba
Michael Kyagaba
Jonathan Adams
Jonathan Adams
Mark Demko
Mark Demko
Jonathan Adams
Jonathan Adams
Jonathan Ad
Jonathan Adams
Jonathan Ad
Jonathan Adams
Jonathan Ad
Jonathan Adams
Jonathan Ad
Jonathan Adams
Fri 11/16/12
Fri 11/30/12
Fri 12/7/12
Table 25: Design Gantt Chart Part 2
Table 24 and Table 25 show the schedule of the project’s design stage. All design tasks
have been completed at this point. Table 26 shows the schedule for the implementation
process. Because much of the design proceeded ahead of schedule, some of the
implementation steps have already been completed. The software development represents
a particularly rigorous section of the schedule, but it may be possible for the hardware
developers to assist in the process.
31
T
ID
Task Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Revise Gantt Chart
Implement Project Design
Hardware Implementation
Breadboard Components
Peak Hold Circuit
Anti-Aliasing Filter
DSP, DAC, and MDAC
Layout and Generate PCB(s)
Assemble Hardware
Test Hardware
Revise Hardware
MIDTERM: Demonstrate Hardware
SDC & FA Hardware Approval
Software Implementation
Develop Software
User Interface
Generate and Capture
Frequency Response Test
THD Test
Noise Test
Calibration
Reporting
Test Software
Revise Software
MIDTERM: Demonstrate Software
SDC & FA Software Approval
System Integration
Assemble Complete System
Test Complete System
Revise Complete System
Demonstration of Complete System
Duration
8 days
88 days
56 days
14 days
14 days
14 days
4 days
14 days
7 days
14 days
7 days
7 days
0 days
56 days
28 days
4 days
4 days
4 days
4 days
4 days
4 days
4 days
14 days
7 days
7 days
0 days
32 days
14 days
18 days
18 days
0 days
Mon 1/14/13
Mon 1/14/13
Mon 1/14/13
Mon 1/14/13
Mon 1/14/13
Mon 1/14/13
Mon 1/14/13
Mon 1/28/13
Mon 2/11/13
Mon 2/18/13
Mon 2/18/13
Mon 3/4/13
Mon 3/11/13
Mon 1/14/13
Mon 1/14/13
Mon 1/14/13
Fri 1/18/13
Tue 1/22/13
Sat 1/26/13
Wed 1/30/13
Sun 2/3/13
Thu 2/7/13
Mon 2/11/13
Mon 2/25/13
Mon 3/4/13
Mon 3/11/13
Mon 3/11/13
Mon 3/11/13
Mon 3/25/13
Mon 3/25/13
Fri 4/12/13
Tue 1/22/13
Fri 4/12/13
Mon 3/11/13
Mon 1/28/13
Mon 1/28/13
Mon 1/28/13
Fri 1/18/13
Mon 2/11/13
Mon 2/18/13
Mon 3/4/13
Mon 2/25/13
Mon 3/11/13
Mon 3/11/13
Mon 3/11/13
Mon 2/11/13
Fri 1/18/13
Tue 1/22/13
Sat 1/26/13
Wed 1/30/13
Sun 2/3/13
Thu 2/7/13
Mon 2/11/13
Mon 2/25/13
Mon 3/4/13
Mon 3/11/13
Mon 3/11/13
Fri 4/12/13
Mon 3/25/13
Fri 4/12/13
Fri 4/12/13
Fri 4/12/13
Develop Final Report
Write Final Report
Submit Final Report
93 days
93 days
0 days
Mon 1/14/13
Mon 1/14/13
Wed 4/17/13
W ed 4/17/13
Wed 4/17/13
Wed 4/17/13 34
15
0 days
6 days
0 days
0 days
0 days
Mon 1/14/13
Mon 3/25/13
Fri 4/12/13
Fri 4/26/13
Wed 4/24/13
Mon 1/14/13
Sun 3/31/13
Fri 4/12/13
Fri 4/26/13
Wed 4/24/13
12
15
15
Martin Luther King Day - University closed
Spring Recess
Project Demonstration and Presentation
Faraday Banquet
Senior Design Expo
Start
Finish
Table 26: Implementation Gantt Chart
32
Predecessors
Week Resource
October 2012
Names
1 Jonathan Adams
4
8
9
9
10,11
12
Michael Kyagaba
Mark Demko
Jonathan Adams
3 Jonathan Adams
5 Jonathan Adams
6 Mark Demko
Jonathan Adams
8 Jonathan Adams
9
Briand Djoko
7
17
17
17
19
21
15
23
24
25
25,13
28
28
30
Briand Djoko
Briand Djoko
Briand Djoko
Briand Djoko
Briand Djoko
Briand Djoko
5 Michael Kyagaba
7 Briand Djoko
8 Briand Djoko
9
10
13
15
18
21
Design Team Information
Jonathan Adams: Project Manager, EE, ESI
Mark Demko, Hardware Engineer, EE
Judicael Briand Djoko: Software Engineer, CpE, ESI
Michael Kyagaba: Archivist, EE
33
Conclusions and Recommendations
The Automated Calibration, Test, and Burn-in System has been significantly designed at
this point. Simulation, parts selection, and testing have proven that the design
requirements should be met. The next step is to implement a prototype of the design and
demonstrate the unit’s functionality. Since the hardware design is ahead of schedule,
remaining hardware design steps should be pulled forward in the schedule. This will
allow software development to migrate to the final hardware and system integration to
occur much sooner than anticipated. Additionally, hardware developers should assist in
the software development process as much as possible.
34
References
[1] Hoffmann, S., & Vella-Coleiro, G. P. (1999). Patent No. 6236286.
[2] Kester, W. (2003). Mixed Signal and DSP Design Techniques. Newnes.
[3 ]Laughton, M. A., & Warne, D. F. (2003). Electrical Engineer's Reference Book.
Elsevier.
[4] Leach Jr., W. M. (Oct 1994). Fundamentals of Low-Noise Analog Circuit Design.
Proceedings of the IEEE , 82, 1515-1538.
[5] Skolnick, D., & Levine, N. (1997). Why Use DSP: Digital Signal Processing 101 - An
Introductory Course in DSP System Design: Part 1. Analog Dialogue , 31.
35