‫ﻣﺪﺍﺭ ﻫﺎﻱ ﻣﻨﻄﻘﻲ ﭘﻴﺸﺮﻓﺘﻪ ‪40412‬‬
‫ﻧﻴﻤﺴﺎﻝ ﺍﻭﻝ ‪90-91‬‬
‫ﻣﺪﺭﺱ‪ :‬ﺩﻛﺘﺮ ﺍﺟﻼﻟﻲ‬
‫ﺩﺍﻧﺸﻜﺪﻩﻱ ﻣﻬﻨﺪﺳﻲ ﻛﺎﻣﭙﻴﻮﺗﺮ‬
‫ﺗﻤﺮﻳﻦ ﺳﺮﻱ ﺍﻭﻝ ‪:‬‬
‫ﻃﺮﺍﺣﻲ ﻧﻤﻮﺩﺍﺭ ﺍﻟﮕﻮﺭﻳﺘﻤﻲ ﻣﺎﺷﻴﻦ ﺣﺎﻟﺖ )‪ - (ASM‬ﺁﺷﻨﺎﻳﻲ ﺑﺎ ﺍﺑﺰﺍﺭ‬
‫‪ASM++ Compiler‬‬
‫ﺩﺭ ﺍﻳﻦ ﺗﻤﺮﻳﻦ ﺑﺎﻳﺪ ‪ ASM‬ﻣﺮﺑﻮﻁ ﺑﻪ ﺩﻭ ﻣﺪﺍﺭ ﻛﻪ ﺩﺭ ﺯﻳﺮ ﺗﻮﺿﻴﺢ ﺩﺍﺩﻩ ﺷﺪﻩ ﺍﻧﺪ‪ ،‬ﺭﺍ ﻃﺮﺍﺣﻲ ﻛﻨﻴﺪ‪ .‬ﺩﺭ ﻃﺮﺍﺣﻲ ﺍﻳﻦ ‪ ASM‬ﻫﺎ‬
‫ﺑﺎﻳﺪ ﻗﻮﺍﻋﺪ ﻃﺮﺍﺣﻲ ﮔﻔﺘﻪ ﺷﺪﻩ ﺭﺍ ﺩﺭ ﻧﻈﺮ ﺩﺍﺷﺘﻪ ﺑﺎﺷﻴﺪ‪.‬‬
‫ﻃﺮﺍﺣﻲ ﺷﻤﺎ ﺑﺎﻳﺪ ﺑﺮ ﭘﺎﻳﻪ ﺯﺑﺎﻥ ‪ ASM++‬ﺍﻧﺠﺎﻡ ﺷﻮﺩ‪ ،‬ﻭ ‪ASM‬ﺗﻮﻟﻴﺪ ﺷﺪﻩ ﺑﺎﻳﺪ ﺩﺭ ﻗﺎﻟﺐ ﻓﺎﻳﻞ ‪ .vdx‬ﺗﻮﺳﻂ ﻧﺮﻡ ﺍﻓﺰﺍﺭ‬
‫‪ Microsoft Visio‬ﻃﺮﺍﺣﻲ ﺷﻮﺩ‪ .‬ﺳﭙﺲ ﺧﺮﻭﺟﻲ ‪ a++‬ﻭ ‪ Verilog‬ﻛﻪ ﺗﻮﺳﻂ ‪ ASM++ Compiler‬ﺗﻮﻟﻴﺪ ﻣﻲ ﺷﻮﺩ ﺭﺍ‬
‫ﺑﻪ ﺍﻧﻀﻤﺎﻡ ‪ ASM‬ﻃﺮﺍﺣﻲ ﺷﺪﻩ‪ ،‬ﺗﺤﻮﻳﻞ ﺩﻫﻴﺪ‪.‬‬
‫ﺟﺰﺋﻴﺎﺕ ﻣﺮﺑﻮﻁ ﺑﻪ ﺍﺑﺰﺍﺭ ‪ ASM++ Compiler‬ﺩﺭ ﻛﻼﺱ ﺣﻞ ﺗﻤﺮﻳﻦ ﺍﺭﺍﺋﻪ ﺷﺪ ﻭ ﻣﻲ ﺗﻮﺍﻧﻴﺪ ﺍﺑﺰﺍﺭ ﻭ ﺭﺍﻫﻨﻤﺎﻱ ﻣﺮﺑﻮﻃﻪ ﺭﺍ‬
‫ﺩﺭ ﺳﺎﻳﺖ ﺩﺭﺱ ﺑﻴﺎﺑﻴﺪ‪ .‬ﻃﺮﺍﺣﻲ ﺷﻤﺎ ﺑﺎﻳﺪ ﺑﻪ ﻭﺳﻴﻠﻪ ﺍﺟﺰﺍ ﺳﺎﺯﻧﺪﻩ ‪ ASM++‬ﻛﻪ ﺩﺭ ﻗﺎﻟﺐ ‪ .vsx‬ﻣﻮﺟﻮﺩ ﺍﺳﺖ‪ ،‬ﺍﻧﺠﺎﻡ ﺷﻮﺩ‪ .‬ﻣﻲ‬
‫ﺗﻮﺍﻧﻴﺪ ﻃﺮﺡ ﻃﺮﺍﺣﻲ ﺷﺪﻩ ﺭﺍ ﺍﺯ ﻃﺮﻳﻖ ﺯﺑﺎﻥ ﻣﻴﺎﻧﻲ ‪ a++‬ﺑﺎﺯﺑﻴﻨﻲ ﻭ ﺭﻓﻊ ﻋﻴﺐ ﻧﻤﺎﻳﻴﺪ‪ .‬ﺩﺭ ﻧﻬﺎﻳﺖ ﻓﺎﻳﻞ ‪ Verilog‬ﺗﻮﻟﻴﺪ ﺷﺪﻩ‬
‫ﺗﻮﺳﻂ ‪ Compiler‬ﻣﺒﻨﺎﻱ ﺩﺭﺳﺘﻲ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﻣﺪﺍﺭ ﺷﻤﺎ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪.‬‬
‫‪ .1‬ﻃﺮﺍﺣﻲ ﻣﺪﺍﺭ ﺟﻤﻊ ﻛﻨﻨﺪﻩ‪/‬ﺗﻔﺮﻳﻖ ﻛﻨﻨﺪﻩ ﺍﻋﺪﺍﺩ ﺩﺭ ﻣﺒﻨﺎﻱ ﺩﻩ‬
‫‪‬ﺷﺮﺡ ﻣﺴﺎﻟﻪ‪:‬‬
‫ﺩﺭ ﺍﻳﻦ ﻣﺴﺎﻟﻪ ﺑﺎﻳﺪ ﻗﺴﻤﺖ ﺟﻤﻊ ﻛﻨﻨﺪﻩ ﻱ ﺍﻋﺪﺍﺩ ﺩﻩ ﺩﻫﻲ ﺭﺍ ﺑﻪ ﻭﺳﻴﻠﻪ ﻱ ﺟﻤﻊ ﻛﻨﻨﺪﻩ ﻱ ﺩﻭ ﺩﻭ ﻳﻲ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﻧﻤﺎﻳﻴﺪ‪.‬‬
‫ﺍﺟﺰﺍﻱ ﻃﺮﺡ ﺷﻤﺎ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﭘﻴﺸﻨﻬﺎﺩ ﻣﻲ ﺷﻮﺩ‪.‬‬
‫‪.1‬‬
‫‪.2‬‬
‫‪.3‬‬
‫‪.4‬‬
‫ﻣﺒﺪﻝ ﺍﻋﺪﺍﺩ ﺩﻩ ﺩﻫﻲ ) ‪ (BCD‬ﺑﻪ ﺩﻭﺩﻭﻱ ﺑﺎ ﺍﺭﺯﺵ ﮔﺬﺍﺭﻱ ‪8421‬‬
‫ﺟﻤﻊ ﻛﻨﻨﺪﻩ‪/‬ﺗﻔﺮﻳﻖ ﻛﻨﻨﺪﻩ ﺍﻋﺪﺍﺩ ﺩﻭﺩﻭﻳﻲ‬
‫ﻣﺒﺪﻝ ﺍﻋﺪﺍﺩ ﺩﻭﺩﻭﻳﻲ ﺑﻪ ﺍﻋﺪﺍﺩ ﺩﻩ ﺩﻫﻲ )‪ (BCD‬ﺑﺎ ﺍﺭﺯﺵ ﮔﺬﺍﺭﻱ ‪8421‬‬
‫ﻗﺴﻤﺖ ﻛﻨﺘﺮﻝ ﻛﻨﻨﺪﻩ ﻱ ﺍﺭﺗﺒﺎﻁ ﺑﻴﻦ ﺍﺟﺰﺍ‬
‫ﻣﻮﺍﺭﺩ ﺗﺤﻮﻳﻠﻲ‪:‬‬
‫‪ ASM ‬ﻣﺮﺑﻮﻃﻪ ﺑﻪ ﺍﻳﻦ ﻣﺪﺍﺭ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﺷﺪﻩ ﺩﺭ ﺯﺑﺎﻥ ‪ ASM++‬ﺩﺭ ﻗﺎﻟﺐ ﻫﺎﻱ ‪ .vdx‬ﻭ ‪. .pdf‬‬
‫‪‬‬
‫ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﺻﺤﻴﺢ ‪ ASM‬ﻣﺪﺍﺭ ﺩﺭ ﻗﺎﻟﺐ ﺯﺑﺎﻥ ‪. ASM++‬‬
‫‪‬‬
‫ﻓﺎﻳﻞ ﺗﻮﻟﻴﺪ ﺷﺪﻩ ﺍﺯ ‪.ASM‬‬
‫‪ ‬ﻓﺎﻳﻞ ﻣﻴﺎﻧﻲ ﺑﺎ ﭘﺴﻮﻧﺪ ‪. .a++‬‬
‫‪ ‬ﻓﺎﻳﻞ ‪ verilog‬ﺧﺮﻭﺟﻲ ﺗﻮﻟﻴﺪ ﺷﺪﻩ ﺑﺎ ﭘﺴﻮﻧﺪ ‪..v‬‬
‫‪ ‬ﻓﺎﻳﻞ ﺗﻮﻟﻴﺪ ﺷﺪﻩ ﺍﺯ ﻓﺎﻳﻞ ‪ a++‬ﻭ ﺑﺎ ﻭﺍﺳﻂ ﺫﻛﺮ ﺷﺪﻩ ﺩﺭ ﺍﺩﺍﻣﻪ‪.‬‬
‫ﻣﺪﺭﺱ‪ :‬ﺩﻛﺘﺮ ﺍﺟﻼﻟﻲ‬
‫ﻣﺪﺍﺭ ﻫﺎﻱ ﻣﻨﻄﻘﻲ ﭘﻴﺸﺮﻓﺘﻪ ‪40412‬‬
‫ﺩﺍﻧﺸﻜﺪﻩﻱ ﻣﻬﻨﺪﺳﻲ ﻛﺎﻣﭙﻴﻮﺗﺮ‬
‫ﻧﻴﻤﺴﺎﻝ ﺍﻭﻝ ‪90-91‬‬
‫ﻭﺍﺳﻂ ﻣﻮﺭﺩ ﻗﺒﻮﻝ‪:‬‬
‫‪module decimal_adder_ subtractor (Sum, Ready, A, B, Start, Add,‬‬
‫;)‪Clock‬‬
‫ﺩﺭ ﺍﻳﻦ ﻣﺪﺍﺭ ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ﺳﻴﮕﻨﺎﻝ ‪ Start‬ﻓﻌﺎﻝ ﺷﻮﺩ ﻋﻤﻠﻴﺎﺕ ﺟﻤﻊ ﺑﺎ ﺗﻔﺮﻳﻖ ﻣﺘﻨﺎﺳﺐ ﺑﺎ ‪ 0‬ﻳﺎ ‪ 1‬ﺑﻮﺩﻥ ‪ Add‬ﺑﺮ ﺭﻭﻱ ﺩﻭ‬
‫ﻭﺭﻭﺩﻱ ‪ A, B‬ﺍﻧﺠﺎﻡ ﻣﻲ ﺷﻮﺩ‪ .‬ﺑﺎ ﭘﺎﻳﺎﻥ ﻳﺎﻓﺘﻦ ﻋﻤﻠﻴﺎﺕ ﺧﺮﻭﺟﻲ ‪ Sum‬ﺁﻣﺎﺩﻩ ﺍﺳﺖ ﻭ ﺳﻴﮕﻨﺎﻝ ‪ Ready‬ﻓﻌﺎﻝ ﻣﻲ ﺷﻮﺩ‪.‬‬
‫‪.2.2‬ﻃﺮﺍﺣﻲ ﻳﻚ ﻣﺪﺍﺭ ﺗﻘﺴﻴﻢ ﻛﻨﻨﺪﻩ ﻣﺒﺘﻲ ﺑﺮ ﺍﻟﮕﻮﺭﻳﺘﻢ ‪shift and‬‬
‫‪subtract ‬‬
‫)‪(Unsigned Shift and Subtract Divider‬‬
‫ﺷﺮﺡ ﻣﺴﺎﻟﻪ‪:‬‬
‫ﺩﺭ ﺍﻳﻦ ﻣﺴﺎﻟﻪ ﺑﺎﻳﺪ ﻣﺪﺍﺭﻱ ﻃﺮﺍﺣﻲ ﻧﻤﺎﻳﻴﺪ‪ ،‬ﺗﺎ ﺣﺎﺻﻞ ﻋﻤﻠﻴﺎﺕ ﺗﻘﺴﻴﻢ ﻳﻚ ﻋﺪﺩ ‪ 16‬ﺑﻴﺘﻲ )ﻣﻘﺴﻮﻡ ﻳﺎ ‪ (Divider‬ﺭﺍ ﺑﺮ‬
‫ﻳﻚ ﻋﺪﺩ ‪ 16‬ﺑﻴﺘﻲ )ﻣﻘﺴﻮﻡ ﻋﻠﻴﻪ ﻳﺎ ‪ (Dividend‬ﺭﺍ ﺑﻪ ﺩﺳﺖ ﺁﻭﺭﺩ‪.‬‬
‫ﺍﻳﻦ ﻣﺪﺍﺭ ﺑﺎﻳﺪ ﻭﺭﻭﺩﻱ ﻫﺎﻱ ) ‪ clock, divider, dividend, ready (input numbers are ready‬ﺭﺍ ﮔﺮﻓﺘﻪ ﻭ‬
‫ﺧﺮﻭﺟﻲ ﻫﺎﻱ )ﺧﺎﺭﺝ ﻗﺴﻤﺖ ( ‪ quotient‬ﻭ )ﺑﺎﻗﻲ ﻣﺎﻧﺪﻩ (‪ reminder‬ﻭ )‪finish (output signals are ready‬‬
‫ﺭﺍ ﺗﻮﻟﻴﺪ ﻛﻨﺪ‪ .‬ﻫﻤﺎﻥ ﻃﻮﺭ ﻛﻪ ﻣﺸﺨﺺ ﺍﺳﺖ‪ ،‬ﻋﻤﻠﻴﺎﺕ ﺗﻘﺴﻴﻢ** ﺑﺎﻳﺪ ﺗﻮﺳﻂ ﺟﺰ ﻋﻤﻠﻴﺎﺕ ﻫﺎﻱ ﺗﻔﺮﻳﻖ )‪ (Subtract‬ﻭ‬
‫ﺷﻴﻔﺖ )‪ (Shift‬ﺍﻧﺠﺎﻡ ﮔﻴﺮﺩ‪.‬‬
‫ﻣﻮﺍﺭﺩ ﺗﺤﻮﻳﻠﻲ‪:‬‬
‫‪ ASM ‬ﻣﺮﺑﻮﻃﻪ ﺑﻪ ﺍﻳﻦ ﻣﺪﺍﺭ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﺷﺪﻩ ﺩﺭ ﺯﺑﺎﻥ ‪ ASM++‬ﺩﺭ ﻗﺎﻟﺐ ﻫﺎﻱ ‪ .vdx‬ﻭ ‪. .pdf‬‬
‫‪‬‬
‫ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﺻﺤﻴﺢ ‪ ASM‬ﻣﺪﺍﺭ ﺗﻘﺴﻴﻢ ﻛﻨﻨﺪﻩ ﺑﻪ ﺻﻮﺭﺕ ‪ shift and add‬ﺩﺭ ﺯﺑﺎﻥ ‪ ASM++‬ﺩﺭ ﻗﺎﻟﺐ‬
‫ﺻﺤﻴﺢ‪.‬‬
‫‪ ‬ﻓﺎﻳﻞ ﻣﻴﺎﻧﻲ ﺑﺎ ﭘﺴﻮﻧﺪ ‪. .a++‬‬
‫‪‬‬
‫ﻓﺎﻳﻞ ﺗﻮﻟﻴﺪ ﺷﺪﻩ ﺍﺯ ‪.ASM‬‬
‫‪ ‬ﻓﺎﻳﻞ ‪ verilog‬ﺧﺮﻭﺟﻲ ﺗﻮﻟﻴﺪ ﺷﺪﻩ ﺑﺎ ﭘﺴﻮﻧﺪ ‪..v‬‬
‫‪‬‬
‫ﻓﺎﻳﻞ ﺗﻮﻟﻴﺪ ﺷﺪﻩ ﺍﺯ ﻓﺎﻳﻞ ‪ a++‬ﻭ ﺑﺎ ﻭﺍﺳﻂ ﺫﻛﺮ ﺷﺪﻩ ﺩﺭ ﺍﺩﺍﻣﻪ‪.‬‬
‫‪‬ﻭﺍﺳﻂ ﻣﻮﺭﺩ ﻗﺒﻮﻝ ﺑﺮﺍﻱ ﻣﺪﺍﺭ ﻃﺮﺍﺣﻲ ﺷﺪﻩ‪:‬‬
‫‪module divide(finish,‬‬
‫;)‪ready,quotient,remainder,dividend,divider,clock‬‬
‫ﻣﺪﺍﺭ ﻫﺎﻱ ﻣﻨﻄﻘﻲ ﭘﻴﺸﺮﻓﺘﻪ ‪40412‬‬
‫ﻧﻴﻤﺴﺎﻝ ﺍﻭﻝ ‪90-91‬‬
‫ﻣﺪﺭﺱ‪ :‬ﺩﻛﺘﺮ ﺍﺟﻼﻟﻲ‬
‫ﺩﺍﻧﺸﻜﺪﻩﻱ ﻣﻬﻨﺪﺳﻲ ﻛﺎﻣﭙﻴﻮﺗﺮ‬
‫ﺑﺎ ﺗﻮﺟﻪ ﺑﺎ ﻣﺎژﻭﻝ ﺑﺎﻻ‪ ،‬ﺩﺭ ﻟﺒﻪ ﻱ ‪ clock‬ﺍﮔﺮ ﺑﺎ ﺳﻴﮕﻨﺎﻝ ‪ ready‬ﺭﻭﺑﺮﻭ ﺷﺪﻳﻢ‪ ،‬ﻭﺭﻭﺩﻱ ‪ divider‬ﺧﻮﺍﻧﺪﻩ ﺷﺪﻩ ﻭ‬
‫ﻋﻤﻠﻴﺎﺕ ﺗﻘﺴﻴﻢ ﺑﺮ ‪ dividend‬ﺁﻏﺎﺯ ﻣﻲ ﺷﻮﺩ‪ .‬ﭘﺲ ﺍﺯ ﺍﺗﻤﺎﻡ ﻓﺮﺁﻳﻨﺪ ﺗﻘﺴﻴﻢ ﺑﺎﻗﻲ ﻣﺎﻧﺪﻩ ﺗﻘﺴﻴﻢ ﺩﺭ ‪ remainder‬ﻭ ﺧﺎﺭﺝ‬
‫ﻗﺴﻤﺖ ﺑﻪ ﺩﺳﺖ ﺁﻣﺪﻩ ﺩﺭ ‪ quotient‬ﺧﻮﺍﻫﺪ ﺑﻮﺩ ﻭ ﺧﺮﻭﺟﻲ ‪ finish‬ﻓﻌﺎﻝ ﺧﻮﺍﻫﺪ ﺷﺪ‪.‬‬
‫**‬
‫ﺑﺮﺍﻱ ﺁﺷﻨﺎﻳﻲ ﺑﺎ ﺍﻟﮕﻮﺭﻳﺘﻢ ﻣﺮﺑﻮﻁ ﺑﻪ ﺍﻳﻦ ﻣﺪﺍﺭ ﺗﻘﺴﻴﻢ ﻛﻨﻨﺪﻩ ﻣﻲ ﺗﻮﺍﻧﻴﺪ ﺑﻪ ﻣﺮﺟﻊ ﺯﻳﺮ ﻳﺎ ﻣﺮﺍﺟﻊ ﺩﻳﮕﺮ ﺩﺭ ﺍﻳﻦ ﺭﺍﺑﻄﻪ ﻣﺮﺍﺟﻌﻪ ﻛﻨﻴﺪ ‪.‬‬
‫‪Computer Arithmetic: Algorithms and Hardware Design, Behrooz Parhami,‬‬
‫‪Chapter 13, Basic Division Schemes, 13.1, Shift/Subtract Division Algorithms‬‬
‫ﻧﻜﺎﺕ‪:‬‬
‫ﻟﻄﻔ ًﺎ ﺗﻮﺟﻪ ﺩﺍﺷﺘﻪ ﺑﺎﺷﻴﺪ ﻛﻪ‪:‬‬
‫‪ .1‬ﻣﻬﻠﺖ ﺗﺤﻮﻳﻞ ﺗﻤﺮﻳﻦ ﺩﻭ ﻫﻔﺘﻪ ﺍﺳﺖ‪ .‬ﺗﻤﺮﻳﻦ ﻫﺎﻱ ﺧﻮﺩ ﺭﺍ ﺑﺎﻳﺪ ﺑﻪ ﺁﺩﺭﺱ ‪ [email protected]‬ﺑﺎ ﻋﻨﻮﺍﻧﻲ‬
‫ﻣﺮﺗﺒﻂ ﺑﺎ ﺗﻤﺮﻳﻦ ﻛﻪ ﺩﺭ ﺑﺪﻧﻪ ﻱ ﺁﻥ ﻧﺎﻡ ﻭ ﺷﻤﺎﺭﻩ ﺩﺍﻧﺸﺠﻮﻳﻲ ﻭ ﺷﻤﺎﺭﻩ ﺗﻤﺮﻳﻦ ﻣﺮﻗﻮﻡ ﺑﺎﺷﺪ‪ ،‬ﺍﺭﺳﺎﻝ ﻛﻨﻴﺪ‪ .‬ﺗﺤﻮﻳﻞ ﺑﺎ ﺗﺎﺧﻴﺮ‬
‫ﺗﻤﺮﻳﻦ ﺑﺎ ﻛﺴﺮ ﻧﻤﺮﻩ ﻫﻤﺮﺍﻩ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪.‬‬
‫‪ .2‬ﺑﻪ ﻫﻴﭻ ﻋﻨﻮﺍﻥ ﺗﻤﺮﻳﻦ ﻳﺎ ﻗﺴﻤﺘﻲ ﺍﺯ ﺁﻥ ﺭﺍ ﺍﺯ ﺩﻳﮕﺮﺍﻥ ﻛﭙﻲ ﻧﻜﻨﻴﺪ ﻭ ﺑﻪ ﺩﻳﮕﺮﺍﻥ ﻛﭙﻲ ﻧﺪﻫﻴﺪ‪.‬‬
‫‪ .3‬ﺩﺭ ﺻﻮﺭﺕ ﻭﺟﻮﺩ ﺍﺷﻜﺎﻝ ﺩﺭ ﻣﻮﺭﺩ ﺗﻤﺮﻳﻦ ﺁﻥ ﺭﺍ ﺑﺎ ﺩﺳﺘﻴﺎﺭ ﺁﻣﻮﺯﺷﻲ ﺩﺭ ﻣﻴﺎﻥ ﺑﮕﺬﺍﺭﻳﺪ‪.‬‬
‫ﻣﻮﻓﻖ ﺑﺎﺷﻴﺪ!‬
‫ﺣﺴﻴﻦ ﺍﻳﺰﺩﻱ ﺭﺍﺩ‬