IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 8, AUGUST 2010
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Performance and Reliability Study of Single-Layer
and Dual-Layer Platinum Nanocrystal Flash Memory
Devices Under NAND Operation
Pawan K. Singh, Student Member, IEEE, Gaurav Bisht, Kshitij Auluck, M. Sivatheja, Ralf Hofmann,
Kaushal K. Singh, and Souvik Mahapatra, Senior Member, IEEE
Abstract—Memory window (MW) and the retention of singlelayer (SL) and dual-layer (DL) platinum (Pt) nanocrystal (NC)
devices are extensively studied before and after program/erase
(P/E) cycling. DL devices show better charge storage capability
and reliability over the SL devices. Up to 50% improvement in
the stored charge is estimated in the DL device over SL when
P/E is performed at equal field. Excellent high temperature and
postcycling retention capabilities of SL and DL devices are shown.
The impact of the interlayer film (ILF) thickness on the retention
of the DL structure is reported. While SL devices show poor P/E
cycling endurance, DL cycling is shown to meet the minimum
requirements of the multilevel cell (MLC) operation.
Index Terms—Cycling endurance, dual layer (DL), Flash
memory, metal nanocrystals (NC), reliability, retention, single
layer (SL).
I. I NTRODUCTION
F
LOATING-GATE (FG) [1] Flash is the dominant nonvolatile memory technology in the market. Increasing
demand in Flash memory has been met by the continual scaling
of the FG cell along with the adoption of the multilevel cell
(MLC) storage scheme [2], [3]. Scaling the FG cell size much
below than 30 nm is unlikely as several scaling challenges are
anticipated, solutions to which are still unknown [4]. The key
issues facing FG technology today are the following: 1) scaling
of the tunnel oxide (TO) and interpoly dielectric thickness;
2) scaling of the lateral dimensions which increases coupling
between the adjacent cells; and 3) the loss of control gate
(CG)–FG coupling due to the planar FG structure required at
sub-30-nm dimensions [5].
Localized charge storage structures like metal nanocrystal
(NC) [6]–[8] and silicon nitride (Si3 N4 )-based charge trap
flash (CTF) [9]–[14] devices are considered as the possible
alternatives to the FG flash. The term “localized” implies the
Manuscript received January 18, 2010; revised April 30, 2010; accepted
May 9, 2010. Date of publication June 21, 2010; date of current version
July 23, 2010. This work was supported in part by the Department of Information Technology, Government of India, through the Centre of Excellence in Nanoelectronics. The review of this paper was arranged by Editor
M. J. Kumar.
P. K. Singh, G. Bisht, K. Auluck, M. Sivatheja, and S. Mahapatra are
with the Center for Excellence in Nanoelectronics, Department of Electrical
Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India.
R. Hofmann and K. K. Singh are with the Applied Materials, Santa Clara,
CA 95054 USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2050961
charge storage in discrete storage nodes (Si3 N4 bulk traps in
CTF and Fermi level of metal in NC) which are electrically
isolated from each other. Ease of integration is the biggest
factor in favor of the CTF devices [13]. So far, reported CTF
devices have shown good memory window but poor retention
[9]–[11]. Large retention loss in CTF devices is related to the
shallow depth of Si3 N4 bulk traps, which is a fundamental issue
related to the nitride material composition and may be difficult
to control [9]–[11]. While process integration is a concern,
choice of tunable workfunction of the metal NC storage layer is
advantageous for achieving good retention, provided an optimal
NC area coverage is obtained [15] for good memory window.
Previous works on metal NC devices have focused mostly
on the single-layer (SL) structure, i.e., one layer of metal NC
embedded in the gate dielectric. High workfunction metals such
as the following: 1) platinum (Pt); 2) gold (Au); 3) nickel (Ni);
4) tungsten (W), etc., [6]–[8], [16]–[19] have been studied.
Less than 5 V of memory window was typically reported for
SL metal NC devices [7], [8], [17], [20]–[22]; though the use
of a metal NC has been shown to have improved both the
memory window and retention over semiconductor NC devices
[18], [19]. In author’s previous work on SL, Pt NC devices
[23], a large memory window (∼10 V), and excellent retention
were reported by optimizing the NC process flow to achieve
a large NC number density (> 3 × 1012 cm−2 , compared to
< 1 × 1012 cm−2 in most prior works) and area coverage
(∼30%). The average NC size was observed to be 3–4 nm,
which is smaller than ∼5 nm reported previously. Endurance
reliability of the SL devices was found to be of concern as maximum of 4 × 103 cycles could be achieved, which is insufficient
for most Flash memory applications [24]. Although the use of
DL NC structure has been reported in literature to improve the
memory window and retention over a SL NC structure [22],
[25], [26], extensive reliability assessment of the DL structure
is still lacking. Preliminary investigations have demonstrated
DL structure to have significantly better P/E cycling endurance
reliability compared to SL structure, with > 104 P/E cycle
endurance at 7-V memory window for the optimized device,
as shown in the author’s previous works [27]–[29].
In this paper, performance and reliability of the SL and
DL NC memory devices with Pt NCs as storage node and
optimized low-leakage Al2 O3 as control dielectric (CD) is reported. DL devices are compared with the SL devices fabricated
using identical process flow. The major contributions of this
0018-9383/$26.00 © 2010 IEEE
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work are as follows. First, the improvement in the memory
window and total stored charge by the use of DL structure
is reported; memory window is shown to improve by ∼90%,
corresponding to ∼50% improvement in stored charge for DL
compared to SL. Second, retention loss from both P- and
E-states for both SL and DL devices are discussed. Excellent
retention in the devices is noted due to a very small charge
room temperature loss and small temperature dependence from
both P- and E-states. For the first time, extensive study on
the impact of interlayer (nanocrystal) film (ILF) thickness on
the retention reliability of the DL devices is reported. While
trends in the retention loss are difficult to analyze, some dependence of the ILF thickness on retention loss is observed,
where the device with the least ILF thickness shows the largest
loss. Third, P/E cycling endurance reliability of SL and DL
devices is extensively studied and compared in this paper. DL
devices with a thick ILF are observed to have better endurance
reliability over devices with thin ILF. Improvement in the DL
endurance over SL devices is also noted and explained by the
two-region model [28], P/E cycling endurance of the SL devices
is unsatisfactory, while that for the DL devices, it is shown to be
satisfactory to meet the minimum MLC flash requirements [24].
Finally, a thorough investigation of the postcycling retention reliability data is presented to complete the understanding of P/E
stress-induced device degradation in NC devices. Compared
to authors’ previous work, this paper focuses on the impact
of ILF thickness on memory window and reliability; and the
postcycling reliability of DL devices in detail.
TABLE I
SL AND DL NC M EMORY P ROCESS F LOW
II. D EVICE FABRICATION
Device fabrication has been performed on p-type wafers with
doping of ∼1 × 1015 cm−3 . After suitable surface cleaning, a
4-nm TO (SiO2 ) was thermally grown using In-Situ-SteamGeneration (ISSG) process in an Applied Materials Centura
RTP tool. Subsequently, a thin film of Pt (0.5–1 nm) is deposited by sputtering from high-purity (> 99.999%) Pt metal
target, and subsequently annealed to form the metal NCs. For
the dual-layer NC formation, 4–6 nm Al2 O3 film is deposited
as the ILF followed by the deposition of another thin film of
Pt and anneal to form the second NC layer. Following the NC
formation step(s), a 12-nm Al2 O3 was deposited as the CD in
both SL and DL devices. Both ILF and CD Al2 O3 films are
deposited using pulsed dc reactive sputter deposition technique.
Postdeposition anneal (PDA) is performed at 1000 ◦ C after
Al2 O3 deposition to improve the film quality. 100-nm Pt metal
is deposited as the high-workfunction control gate (CG) using
a shadow mask to complete the device (capacitor) formation
process. Table I summarizes the process details for both SL and
DL device fabrication.
Fig. 1(a) and (b) show the schematic of SL and DL devices,
respectively. Fig. 1(c) and (d) show the cross section TEM
images confirming the formation of the desired SL and DL NC
structures. The images show the formation of the discrete NCs
and two separate NC layers for the DL devices. Plan-view TEM
images, similar to one shown in Fig. 1(e), are used to extract
the number density, area coverage, and size distribution of the
Fig. 1. Schematic of (a) SL and (b) DL metal NC devices. Random distribution of NC in the two layers is also shown. Cross section TEM of (c) SL and
(d) DL devices confirms the presence of the NCs in the gate stack and the
presence of physically separated NC layers in the DL device (e) plan-view TEM
of SL device showing excellent size and uniform distribution of NCs.
NCs. Area coverage and the number density were estimated to
be 26%–30% and 2.5 × 1012 − 3.4 × 1012 cm−2 , respectively.
The obtained area coverage is found to be very close to the
optimal area coverage required for good performance given by
numerical simulation [15]. Table II lists the stack details, as
well as the average NC size, area coverage, and the number
density for the splits used in this paper. The size distribution
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TABLE II
SL AND DL D EVICES S PLITS U SED IN T HIS W ORK
of the NC can be controlled to within 1 nm of the average size,
although statistics are not computed due to the lack of sufficient
TEM data. Extremely small NC sizes (< 2 nm diameter) are
not obtained,1 which prevents issues like quantum confinement.
More information on NC formation can be found here [30].
III. R ESULTS AND D ISCUSSION
A. Program/Erase (P/E) Transients and Memory Window
Capacitors with 100-μm diameter are used for the electrical
testing of all the devices. P/E transients are obtained using
flatband voltage (VFB ) from C–V measurements. Fig. 2(a)
shows the P/E transient for SL1 device where P/E VFB is
plotted against P/E pulse time. SL1 device can be programmed
to maximum 8-V VFB and erased to −2-V VFB . Overerased
ΔVFB is marked on the figure. The P-state VFB when the
devices are programmed from the overerased state, is identical
to when the device was programmed from the fresh device VFB
(∼2 V). Similar transients are observed for DL devices, which
also show large positive VFB shift during program and significant overerase. Fig. 2(b) compares the saturation memory
window of SL3 and DL9 devices at identical equivalent gate
voltage (EVG ). The TO field is identical in SL and DL devices
at identical EVG . P/E saturation is achieved at 10 ms for both
SL and DL devices. Since capacitor structures without S/D are
used in this work, the P/E speed is slow in these devices. But
for comparison, as an example, the programming time (TP ) for
6-V memory window for SL and DL devices, both programmed
at +20 V, are ∼100 μs and ∼20 ms, respectively. The P/E
speed, however, is not indicative of the practical P/E speed possible by the use of optimized transistor structure. The DL device
can be programmed to the maximum +11 V VFB and erased to
−4 V VFB . Maximum memory window obtained for SL and
DL devices are ∼10 V and ∼15 V, respectively. Note that the
obtained memory window for both SL and DL devices is significantly larger when compared to the reported CTF memory
window of 6–8 V [9], [11], [13]. Besides deeper potential well
for charge storage in metal NC devices, large memory window
is obtained as the high-k Al2 O3 CD film prevents leakage of
charge from the NC to CG during programming and reduces
electron back injection from the CG to NC during erase. High-k
Al2 O3 is used as the CD as its bandgap (8.8 eV) is very
similar to SiO2 bandgap (9.1 eV), thereby reducing the leakage
1 The current metal deposition process limits the control of NC size to above
2 nm. The average size of NC is always above 2 nm, which gives insignificant
number of NC with size < 2 nm.
Fig. 2. (a) P/E transient of SL1 device for three P- and E-voltages. Large
memory window and overerase are seen, and (b) comparison in memory
window of DL9 over SL3 when operated at identical equivalent VG shows
improvement in DL9 and (c) comparison in Memory window of SL device
with 17-nm CD over SL device with 12-nm CD.
current significantly to improve memory window. Other high-k
materials (HfO2 , ZrO2 , etc.) having much smaller bandgap
would likely result in higher gate leakage, with corresponding
reduction in the overall memory window.
In previous works [22], [25], [26], improvement in the memory window and total stored charge by the use of DL structure
has been reported, but has not been quantified. Any observed
improvement could be due to two reasons: 1) Increased CD
thickness for the first NC layer; and 2) Additional charge
storage in the second NC layer. Increase in the CD thickness
will increase the VFB due to the increased moment of the stored
charge. Fig. 2(c) compares the memory window improvement
between the standard SL device and SL devices with thicker
CD, to isolate the effect of the increased CD thickness. Note
the improvement in the memory window of an SL device with a
thicker CD over an SL device with a standard CD thickness. SL
device with CD thickness of 17 nm shows ∼38% improvement
in memory window over standard SL device (CD = 12 nm),
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Fig. 3. Comparison of the P/E VFB in DL devices at equal VG and equivalent
VG (EVG ). Difference in the P-VFB and E-VFB gives the memory window.
which is close to the expected 42%. The observed increase in
the memory window in Fig. 2(b) is ∼90%, which cannot be
explained by only an increase in the CD thickness. Additional
charge storage in the second NC layer is therefore essential
for the observed increase in memory window. DL charge is
estimated to be 1.5 times that of SL charge; the assumption in
the calculation is that no individual NC layer can store more
charge than the SL layer charge which is designated as 100%.
This assumption is valid as the programming is done at equal
TO field and hence should cause equal charge injection.
Fig. 3 shows the memory window of all DL devices both at
19-V and 21-V VG ; 19-V and 21-V EVG with respect to the
DL1 device. The TO field is identical for all devices at EVG .
The memory window at VG and EVG for DL1 are identical.
Dependence of the memory window on the ILF thickness
is observed, at identical VG , device DL3 with a thicker ILF
(6 nm) shows smaller memory window compared to device
DL2 and DL1 with thinner ILF (5 nm and 4 nm, respectively).
DL9 shows larger memory window due to its higher NC area
coverage. At EVG however, DL3 and DL2 shows nearly similar
memory window (DL3 > DL2) which is larger than DL1, while
the memory window of DL9 is still the largest. Reduction in
layer–layer coupling with an increasing ILF thickness may be
responsible for the increased memory window in thicker ILF
devices at equal EVG .
To further support the top-layer charging, 2-D simulations
are performed on a DL device structure. Using a 2-D structure
of NCs between a grounded conductor (substrate) and another
conductor at a bias (gate), potential on each NC is computed
using the capacitance extraction method [15]. The region is
then divided into very fine square grid of spacing of 0.1 nm.
Potential at each point on the grid in the region between CG
and the substrate is computed by solving Laplace Equation
using the finite difference method. The solution is iteratively
updated on each grid point until its saturation. Electric field is
obtained from the derivative of the potential. Fig. 4(a) shows
the simulated 2-D electric field in a DL structure with a 6-nm
ILF separating the NC layers at a program VG of 25 V. Electric
field lines, shown in Fig. 4(b), are then computed from the
2-D electric field data for the same device structure. From
the electric field data, we can see that during the program,
in addition to the large TO field below the bottom NC, large
electric field exists (∼15 MV/cm) between the NC layers (above
bottom layer NC and below top layer NC). Electrons from the
Fig. 4. 2-D simulations of the DL device structure showing (a) the electric
field and (b) electric field lines during program operation. Large electric field
exists between the two layers of NCs, making the charging of second layer
possible.
bottom layer NC can be emitted at such high fields, and travel
along the field lines [shown in Fig. 4(b)] to reach the top-layer
NC. It is also possible to charge the top layer directly from the
substrate depending upon the position of the top-layer NC. In
either case, charge storage in the top NC layer is plausible, as
also suggested by experiments.
B. Precycling Retention
Precycling retention measurements are performed on SL and
DL devices with 0 V applied at gate and substrate terminals.
Fig. 5(a) shows the retention loss transients from P- and
E-states2 at 25 ◦ C, 80 ◦ C, and 150 ◦ C for SL1 and DL9 devices.
E-state retention is measured from 0 V starting from VFB for
both devices, while the P-state retention is measured from 6 V
for SL1 and ∼8.5 V for DL9 device. Smaller charge loss
and weaker temperature dependence is seen from the E-state
retention loss for both devices (note that the natural VFB of
these devices are ∼2 V, so the internal field is not negligible
at VFB = 0 V). Room temperature (RT) retention loss from
P- and E-states at the end of 104 s for the SL device are −0.2 V
and 0.06 V, while for DL device, the loss from P- and E-states
are −0.12 V and 0.06 V, respectively. At 150 ◦ C, the charge loss
2 Charge gain in the E-state is also defined as a retention loss as it reduces the
overall memory window.
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Fig. 5. (a) High-temperature retention loss transients for one DL and one SL
devices at 25 ◦ C, 80 ◦ C, and 150 ◦ C and (b) bar graph showing the retention
loss from P- and E-states for all DL devices measured at 25 ◦ C, 80 ◦ C, and
150 ◦ C.
from the P-state is −0.25 V and −0.6 V, respectively, for SL
and DL devices. Charge loss is found to be smaller in the case
of low starting VFB for both SL and DL devices. Note that while
the TO thickness is similar for both devices, the CD thickness
for the first NC layer of the DL device is higher and that of the
second NC layer is identical when compared to the SL device.
Any higher CD advantage however gets compensated by higher
starting P-state VFB for the retention for the DL compared to the
SL device. Further studies are needed to understand the relative
charge loss during the retention from first and second NC layers
for the DL device. Retention loss measurements for other SL
and DL devices also show similar characteristics with relatively
smaller loss from the E-sate compared to the P-state. Fig. 5(b)
shows the measured retention loss of all the DL devices at
25 ◦ C, 80 ◦ C, and 150 ◦ C obtained after 104 s bake at respective
temperatures. DL1 shows the largest retention loss while DL9
shows the lowest retention loss at all temperatures. Retention
loss in DL2 is smaller than DL1, but it is important to realize
that the retention loss of the DL9 device is significantly better
than that reported for CTF devices having similar TO and CD
thicknesses, more so at higher temperatures [9]–[11]. This can
be ascribed to deeper potential well for charge storage in metal
NC devices.
C. P/E Cycle Endurance
Fig. 6(a) and (b) show the typical endurance characteristics
of the SL and DL devices, respectively. The magnitude and
time of the P/E pulse are kept identical during cycling. SL
Fig. 6. P/E cycling endurance for (a) SL devices with different P/E conditions
and (b) DL devices with 6-V memory window. Except DL1, all other devices
achieve 104 cycles without breakdown. DL1 breakdown occurs after 5 × 103
cycles.
devices (SL1 and SL3) show poor cycling endurance of no
more than 4 × 103 cycles for any starting memory window of
as marked by arrows in Fig. 6(a). The memory window is varied
by changing P/E conditions to alter the device stress conditions
and study its impact. The devices are observed to cycle with a
constant memory window until breakdown. After breakdown,
no programming can be performed on the devices. DL devices
show better endurance characteristics than SL devices. Fig. 6(b)
shows the P/E cycling endurance transients for all DL devices
cycled with 6-V memory window. Except DL1, all other DL
devices show 104 cycle endurance without breakdown which is
the minimum requirement for current NAND memory devices
[24]. DL1 is able to achieve only 5 × 103 cycles before breakdown is observed. The breakdown in DL devices is observed
after long cycling as shown in the inset in Fig. 7(b), illustrating
breakdown in DL9 after 75 000 cycles with 6-V starting memory window. Since the measurement time required for such long
measurements is extremely large, endurance measurements are
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Fig. 8. Pre-and postcycling high-temperature retention loss in DL9 at room
temperature and 150 ◦ C from the P-state. Difference of ∼100 mV is noted in
the retention loss measured at 150 ◦ C between pre- and postcycling retention
suggesting robust performance of the DL devices.
Fig. 7. (a) Comparison of pre- and postcycling retention transients for one SL
and one DL device showing loss at room temperature (b) Bar graph showing
the loss from both P- and E-states for all DL devices at room temperature.
stopped after 104 cycles or breakdown, whichever is earlier.
Fig. 6(c) shows the number of cycles possible with DL devices
with different memory windows in both linear and log scales.
Increasing the memory window from 6 V to 9 V reduces the
number of P/E cycles achieved, due to the defect generation
in the gate stack with increased P/E stress at larger memory
window.
Similar to the SL devices, the DL devices also do not show
any window closure with cycling. However, both P- and E-VFB
levels are observed to shift toward more negative VFB , suggesting the permanent positive charge trapping in the gate stack
for both SL and DL devices. Hole injection and subsequent
trapping in the gate stack during erase operation is suggested
as the primary reason for the negative shift in VFB and the
eventual breakdown in the NC gate stacks [28]. Larger area
coverage in DL compared to SL limits the hole injection during
erase, thus improving the endurance reliability [28]. Further
discussion on DL P/E cycling endurance is reported elsewhere
[29] for the brevity of this paper, while reporting key results for
completeness.
D. Postcycling Retention
Postcycling retention is one of the most important requirements for a flash device. P/E stress during cycling generates
traps in the TO and CD, causing an increase in the retention loss. Fig. 7(a) shows the room temperature retention loss
transients for DL9 (left-Y axis) and SL1 (right-Y axis) devices. The DL device was stressed for 104 P/E cycles with
6-V memory window and SL device for 103 cycles at 4-V
memory window. No change in the retention loss is observed
in the postcycling case w.r.t the precycling case from both
P- and E-levels. Fig. 7(b) shows the comparison of the preand postcycling retention loss for all DL devices after 104 s
at room temperature. The devices are cycled for 104 cycles at
6-V memory window (5 × 103 cycles for DL1). Retention loss
is shown from both the P- and E-states. Once again, there is
a small change in the retention loss in the postcycling case
compared to the precycling case, for both P- and E-levels.
Fig. 8 shows the pre- and postcycling retention loss transients at 25 ◦ C and 150 ◦ C in DL9. The device is cycled for
104 cycles at 6-V memory window for the postcycling measurement. Data is shown from the P-state as it is generally larger
than the E-state loss. Difference of ∼100 mV is noted between
the pre- and postcycling retention loss at 150 ◦ C, while the
difference at 25 ◦ C is only 50 mV. Fig. 9(a) shows the schematic
illustrating the direction of charge loss with the applied gate
voltage. Application of positive VG causes electrons to move
toward CG, increasing leakage through the CD, while negative
VG causes increased electron loss through the TO. Fig. 9(b)
shows the measurement results on DL3, where the retention
loss from both P- and E-states is plotted against the applied
VG (during retention). Fig. 9(b) (left-Y axis) shows that the
E-state retention loss (actually electron gain by NC causing
VFB increase) is found to be significantly more on application
of negative VG , while the application of the positive VG shows
a negligible effect. This suggests charge leakage from the CG
to NC via the CD, while a very minimal leakage from NC to
substrate via the TO. Fig. 9(b) (right-Y axis) shows the retention
loss from the P-state, which gradually increases with increasing
positive VG . Upon increasing negative VG , negligible change is
observed till about −6 V, after which, a sudden, large increase is
observed. This sudden increase in charge large loss can possibly
be caused by soft erase arising because of the large TO field on
application of negative VG on a programmed cell. If this effect
is isolated, the remaining bias dependence of P-state retention
loss again points out to dominant charge loss from NC to CG
via the CD. Improvement in the quality of CD is therefore
expected to further reduce the retention loss from both P- and
E-states. Gate bias measurements also suggest good quality
TO with low leakage at small electric field. The postcycling
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successfully explain the improved P/E cycling endurance for
devices having higher NC area coverage, and also the improvement observed for DL devices. Absence of the generated traps
above and below the NC prevents extra charge loss due to SILC,
and hence, postcycling retention loss remains identical to that
observed before cycling.
IV. C ONCLUSION
In this paper, SL and DL Pt NC devices are reported for
NAND Flash memory application with an optimal area coverage
Fig. 9. (a) Schematic of direction of charge loss with respect to the applied
gate voltage (b) Pre- and postcycling gate bias accelerated retention for DL3
from P- (Right-Y) and E- (left-Y) states. Measurements are performed by
applying nonzero VG during retention for 103 seconds.
retention loss changes only slightly even at large applied gate
bias, suggesting a robust performance of the NC gate device.
High-temperature retention measurements and gate bias accelerated measurements suggest retention loss through CD to
be the dominant cause of charge loss in the NC devices. In the
E-state, electrons are injected from the CG into the NC through
the CD, causing the observed increase in VFB . From the P-state,
electrons are emitted from the NC in the CD, which then move
toward the CG and causes VFB reduction. As E-state retention
loss involves tunneling of electrons into the NC, it may get
affected due to Coulomb blockade and hence, E-state retention
loss is usually lower than that from the P-state. It is well
known that in Al2 O3 films, trap-assisted Poole–Frenkel (PF)
conduction [31] is the dominant charge transport mechanism.
Conduction occurs by the electron movement from one trap to
another by detrapping, followed by trapping at another location.
Electrons emitted from the CG/NC are transported in the CD
through the traps present in the Al2 O3 CD. PF conduction is
dependent on both the temperature and electric field, and as
observed, retention loss increases at higher temperature and
on application of higher gate bias during retention. Therefore,
reduction in trap density or increase in trap depth is expected to
improve retention reliability.
The results are in agreement with the authors’ previous work
[28], where it was shown that in NC devices, P/E transients,
memory window, and retention loss are not significantly dependent on defect generation in the gate stack due to P/E
cycling-induced stress. A plausible explanation has been given
by invoking a two-region model, where P/E cycling induced
defect generation takes place in the gate stack between the NCs
and not in the line of NCs, see [28] for details. This model can
of ∼30% and a good number density of ∼3 × 1012 cm−2 .
DL devices show significant improvement over SL device in
the following: 1) memory window; 2) total charge stored; and
3) endurance reliability, without compromising on the retention
reliability. Impact of ILF thickness on the reliability of DL
devices is reported for the first time. Devices with thicker ILFs
are shown to have better retention reliability and charge storage,
but require larger voltage for P/E, and ILF thickness is therefore
a crucial design parameter. PF conduction via CD was shown to
be responsible for majority of charge leakage during retention,
for both SL and DL devices. Improvement in the CD film
quality is expected to improve the retention reliability, even
the thin ILF devices. Defects generated during P/E cycling are
shown to have insignificant impact on the memory window
and retention characteristics. No adverse effects related to
integration of metal NC in the gate stack is noted, and metal
NC devices show no fundamental reliability showstopper. It is
therefore concluded that the DL metal NC devices fabricated
in a CMOS compatible process flow show an early promise for
the MLC operation and are suitable for FG replacement at sub30-nm technology node.
ACKNOWLEDGMENT
P. Singh acknowledges the help from K. Srivastava in performing high-temperature retention measurements.
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May 2004.
Pawan K. Singh (S’07) received the B.Tech. and
M.Tech. combined degrees from the Department of
Electrical Engineering, Indian Institute of Technology (IIT) Bombay, Mumbai, India, in 2006, where
he is working toward Ph.D. degree in the Electrical
Engineering Department, IIT Bombay since 2006.
Since 2006, he is an AMAT fellow for Ph.D. in IIT
Bombay. From June 2007 to July 2008, he has been
a graduate intern at Applied Materials, Santa Clara,
CA. His research interests include technology development, physics, and reliability characterization
of nonvolatile memories. He is currently working on metal nanocrystal-based
nonvolatile memories for NAND application.
Gaurav Bisht received the M.Sc. degree in physics from Indian Institute
of Technology (IIT) Roorkee, Roorkee, India, 2007. He is working toward
the M.Tech. degree in microelectronics from the Department of Electrical
Engineering, IIT Bombay, Mumbai, India, since 2007.
His research interests are in the areas of nonvolatile memories, device
reliability, and characterization.
Kshitij Auluck is currently working toward the B.Tech. and M.Tech. degrees
(dual-degree) in microelectronics from the Department of Electrical Engineering, Indian Institute of Technology (IIT) Bombay, Mumbai, India, and will
graduate in 2010.
From May 2008 to July 2008, he was a student intern at Corporate Technology Group, Intel Corporation, Bangalore, India. His research interests are
physics, fabrication, and modeling and simulation of novel semiconductor
devices for logic and memory.
M. Sivatheja is working toward the B.Tech. and M. Tech. combined degrees
from the Department of Electrical Engineering, Indian Institute of Technology
(IIT) Bombay, Mumbai, India, since 2004.
His research interests include semiconductor device modeling and simulation. He is currently working on metal nanocrystal-based nonvolatile memories.
SINGH et al.: PERFORMANCE AND RELIABILITY STUDY OF FLASH MEMORY DEVICES UNDER NAND
Ralf Hofmann received the Diplom-Ingenieur (M.S.E.E.) degree in electrical
engineering from Chemnitz University of Technology, Chemnitz, Germany.
He is a member of Technical Staff in the Advanced Technology Group
under the Office of the CTO at Applied Materials. His work involves the
evaluation and development of new processing techniques and equipment for
new and emerging applications in the IC space as well as the energy sector. In
1994, he joined Applied Materials in the PVD Technology group, working on
various aspects of metal deposition and process integration. In 2001, he joined
ZMD America, Incorporated, a mixed-signal ASIC design company, where he
worked on two successfully productized IC designs. He worked from 2002 to
2003, as an Independent Consultant for a telecommunications startup company
as well as a small company in the transportation sector before rejoining Applied
Materials in 2004.
Kaushal K. Singh is a Senior Member of technical staff at Applied Materials,
Santa Clara, CA.
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Souvik Mahapatra (M’02–SM’07) received the
Ph.D. degree in electrical engineering from the
Indian Institute of Technology (IIT) Bombay,
Mumbai, India, in 1999.
During 2000 to 2001, he was at Bell Laboratories,
Murray Hill, NJ. Since 2002, he is with the Department of Electrical Engineering, IIT Bombay, and
presently holds the position of Professor. He has published more than 85 papers in peer reviewed journals
and conferences, delivered invited talks at leading
international conferences in the U.S., Europe, and
Asia-pacific including at the IEEE IEDM, delivered reliability tutorials at the
IEEE IRPS, and acted as a Reviewer of several international journals and
conferences. His research interests are in the area of characterization, modeling
and simulation of CMOS and Flash memory devices, and device reliability. He
also holds an honorary graduate faculty position at Purdue University, West
Lafayette, IN
Dr. Mahapatra is a Distinguished Lecturer of IEEE EDS.