IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 9, SEPTEMBER 2009
2065
Performance and Reliability of Au and Pt
Single-Layer Metal Nanocrystal Flash Memory
Under NAND (FN/FN) Operation
Pawan K. Singh, Student Member, IEEE, Ralf Hofmann, Kaushal K. Singh,
Nety Krishna, and Souvik Mahapatra, Senior Member, IEEE
Abstract—In this paper, we report on the fabrication and reliability characterization of gold (Au) and platinum (Pt) single-layer
nanocrystal (NC)-based Flash memory devices for NAND application. The devices are fabricated using a CMOS-compatible process
flow with high-quality (low leakage and large breakdown) Al2 O3
as the control dielectric. The impact of processing conditions on
the NC size, area coverage, and number density is also investigated. Large memory window (∼7.5 V for Au and ∼10 V for Pt)
and good retention are observed for both Au and Pt NC devices.
Excellent postcycling retention is also noted for Pt NC devices.
Endurance characteristics are found to be of concern as maximum
of only 1 × 103 and 4 × 103 cycles can be obtained for Au and Pt
devices, respectively. Anneal-temperature-dependent gate leakage
is observed in Au devices and is investigated using analytical methods. Diffusion of Au atoms from the NC into the gate dielectrics is
seen which correlates to the electrical measurements. Postcycling
retention and program/erase of Pt NC devices are shown to be
good.
Index Terms—Cycling endurance, Flash memory, memory window, metal nanocrystals (NCs), reliability failure, retention, transmission electron microscopy (TEM)/electron diffraction (EDX).
I. INTRODUCTION
C
ONVENTIONAL floating-gate (FG) flash [1] has been
the dominant nonvolatile memory (NVM) technology for
many years. The difficulty in scaling the tunnel oxide (TO)
thickness due to stress-induced leakage-current-related charge
loss, reduction in gate coupling, and increase in cell-to-cell
interference have made scaling of FG flash difficult at sub3× node [2]. Nanocrystal (NC) flash [3]–[12] and charge trap
flash (CTF) [13], [14] are considered as possible alternatives.
CTF devices reported so far show good memory window but
poor retention [13], [14], while the NC devices show poor
memory window [4], [6], [11], [12]. Poor retention of CTF
is linked to shallow trap depth of the nitride storage layer,
which is an inherent material property and is difficult to control
[14]. Choice of tunable workfunction (WF) of the metal-NC
storage layer is advantageous for achieving good retention.
Previously reported small memory window of the NC devices
Manuscript received April 9, 2009; revised June 9, 2009. Current version
published August 21, 2009. The review of this paper was arranged by Editor
G.-T. Jeong.
P. K. Singh and S. Mahapatra are with the Indian Institute of
Technology Bombay, Mumbai 400076, India (e-mail: [email protected];
[email protected]).
R. Hofmann, K. K. Singh, and N. Krishna are with Applied Materials, Santa
Clara, CA 95054 USA.
Digital Object Identifier 10.1109/TED.2009.2026324
can be attributed to nonoptimal NC number density (ND), size
distribution, small area coverage (AC), and low NC WF or high
control dielectric (CD) leakage.
A significant amount of work on NC-based Flash memory
structures has focused on semiconductor NCs like Si [3] and
Ge [4]. Issues with semiconductor-based NCs are small WF,
quantum-confinement (QC)-related WF lowering, and poor
control of NC size that result in poor overall performance of
such devices. QC arises due to the small size of the NC, causing
splitting of conduction and valence bands in a semiconductor
(Fermi level in metals) [15]. This band splitting lowers the
effective WF of the NC material. The problem of QC is reduced
if the density of states is high around the Fermi level. The use
of metal as an NC material offers a significant advantage over
the semiconductor as some metals have large WF, very little to
no QC (due to large density of states), and accurate control of
NC size. Large WF improves the retention of the device without
compromising on program/erase (P/E) speeds. The metals that
have been studied until now include Pt, Au, Ni, W, Co, and Pd
[5]–[12], [16], [17].
This paper reports on the fabrication of single-layer (SL) NC
devices with large WF metals with optimal AC, size distribution, and ND of NC along with an optimized high-k Al2 O3
CD. The metals investigated for NC include Au and Pt due
to excellent physical and chemical properties. Both Au and Pt
have large WF of more than 5.0 eV and low chemical reactivity.
Impact of NC size and density on the memory window is
investigated. The memory window of the NC device in this
paper has been improved by simultaneous use of the following:
1) large WF metal NC; 2) optimization of NC formation process
to obtain high ND; 3) optimal AC; 4) small and uniform NC
size; and 5) low-leakage high-k Al2 O3 as the CD. Performances
of the Au and Pt NC devices fabricated under identical conditions are compared. SL Pt NC devices are found to have
better memory window and retention than SL Au NC devices.
We also report on the P/E cycling endurance reliability and
postcycling retention and P/E characteristics of SL Au and
Pt devices in detail. The reasons for the better performance
of Pt devices are investigated and reported by electrical and
analytical measurements.
II. FABRICATION
Fabrication of the devices is performed on p-type wafers
with a doping level of ∼ 1 × 1015 cm−3 . After surface clean in
0018-9383/$26.00 © 2009 IEEE
2066
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 9, SEPTEMBER 2009
Fig. 1. (a) Schematic of NC device showing the position of NCs in the stack.
(b) Process flow of Pt and Au NC devices.
100 : 1 HF, 40-Å ISSG TO is grown with H2 and O2 gas flow
using RTP. High purity metal (Au and Pt) targets (> 5 N or
99.999%) are used to deposit thin films of 5 and 10 Å on the
TO by sputtering. These films are then annealed by RTP to yield
the respective metal NC. Au and Pt NC anneal temperatures are
in the range of 500 ◦ C–900 ◦ C. As will be discussed later, the
thickness of initial metal deposition determines the final NC
size and density distribution. A 120-Å optimized low-leakage
Al2 O3 film is then deposited by reactive sputtering as the CD.
Control gate (CG) is formed by depositing a 1000-Å Pt metal on
top of the CD using a shadow mask to form 100-μm-diameter
capacitors for electrical characterization. Pt CG is chosen as it
behaves as a large WF metal gate. Fig. 1 shows the schematic
and process flow of the fabricated NC devices.
Table I lists the devices used in this paper. Process condition
for each device is also mentioned in the table. In addition to
the devices mentioned in Table I, other Au NC devices are
also fabricated with 5-Å initial film thickness (Au-S3, Au-S4).
These devices are not used for electrical characterization due to
high gate leakage, the reason for which is provided later.
III. RESULTS AND DISCUSSION
Both physical and electrical characteristics of the NC devices
have been studied and are reported in this section. First, NC
formation and optimization by film deposition and annealtemperature control are investigated, and the resulting NC size
distribution, AC, and ND are extracted. The electrical performance and reliability of the Au and Pt NC devices are studied
in the later part of this paper.
A. Physical Characterization
Fig. 2 shows the cross-sectional and plane-view transmission
electron-microscopy (TEM) images for Au and Pt NC devices.
The formation of isolated (in horizontal and vertical directions)
NCs in the gate stack can be clearly seen. The NCs are found to
be located directly above the TO and are completely surrounded
from the top and sides by the CD. No voids are seen in the
gate stack after the deposition of CD. Plane-view TEM images
are used to obtain the ND, AC, and size distribution of the
NCs using an image processing algorithm [18]. These statistics
are listed in Table I along with the device splits used in the
work for both Au and Pt NC devices. Pt NC devices show
significantly better size distribution, ND, and AC compared to
Au NCs. Fig. 3 shows the effect of initial metal thickness and
anneal temperature on the NC size shown by plane-view TEM
images for Au NC. Moving down indicates the effect of the
increase in initial metal thickness, while moving right shows
the effect of anneal temperature at equal initial metal thickness.
More information on NC formation can be found in [18] and
[19] for Pt and Au NCs, respectively. By optimizing the anneal
temperature and initial metal thickness, the size distribution and
AC can be controlled.
It has been found that for unannealed Au NC devices, maximum NC ND is observed for samples with 5-Å Au deposition
but with small AC of ∼20%. Samples with 10-Å gold deposition show an AC of ∼25% but with smaller ND and wider size
distribution of NCs. NC anneal is found to decrease the ND of
the Au NCs. In the case of Pt NC, the AC is 26% and 30% for
5- and 10-Å Pt thicknesses, respectively. The largest observed
ND for Au is 2.5 × 1012 cm−2 , while it is 3.4 × 1012 cm−2
for Pt. The ND decreases and AC increases as the initial metal
thickness increases from 5 to 10 Å for both Au and Pt NCs. The
increase in NC anneal temperature causes the increase in size of
the NC while reducing the ND. The AC and ND of Pt NC are
found to be very close to the optimal suggested by numerical
simulations [20].
Pt NCs show a smaller average size compared to the Au
NCs, while the size distribution of the Pt NC is also superior.
Fig. 4(a) shows the size distribution of Au and Pt samples listed
in Table I. In the figure, the ND of NC is plotted for all the NC
sizes observed in the TEM to determine the size distribution.
For Au NC, the size distribution of unannealed samples is
found to be between 3 and 5 nm, which is very desirable. Upon
annealing, the distribution is found to tighten further, although
the entire distribution shifts toward larger sizes. Small NCs
are found to fuse together to form larger NCs, thus shifting
the whole distribution toward larger sizes. This shift is due
to melting and subsequent movement of extremely small Au
NCs during anneal. Although Au NC anneal temperature is
significantly lower than the bulk melting point of Au, due to
their small size, the melting point of the NCs is much lower than
that of the bulk material [21], [22]. Due to the size-dependent
melting temperature, it is possible to melt the smallest Au NCs
during NC anneal step, causing them to coalesce together.
Size distribution of the Pt NCs is clearly seen to be much
better compared to that of Au NCs. For Pt-S1 (5-Å) deposition,
the size distribution is between 2 and 4 nm with an average of
∼3 nm, while the distribution for Pt-S3 (10-Å) deposition is
between 3 and 5 nm with an average size of ∼4 nm. Fig. 4(b)
shows the effect of initial Pt metal thickness on the NC size.
The average NC size increases from 3 to 6 nm when the
initial film thickness is increased from 5 to 15 Å, keeping
identical anneal condition. Small average size, along with tight
NC size distribution, is essential for NC device scaling. Good
size distribution, along with large ND and AC, is important to
achieve uniformity in the gate stack of scaled NC devices.
B. Electrical Characterization
P/E transient, gate leakage, retention, and cycling
endurance have been performed on capacitors with diameter
(Φ) = 100 μm. QSCV measurements were performed using
SINGH et al.: PERFORMANCE AND RELIABILITY OF Au AND Pt SL METAL NC FLASH MEMORY
2067
TABLE I
NC DEVICE SPLITS AND THE CORRESPONDING EXTRACTED SIZE DISTRIBUTION, AC, AND ND
Fig. 2. Cross-sectional and plane-view TEM images of (a) Au and (b) Pt NC
devices showing formation of isolated NC in the gate dielectric. NC size and
density distributions are obtained from plane-view TEM images.
Fig. 4. (a) NC size distribution of Pt and Au NC devices. Au devices
have anneal and initial metal deposition thickness variation. (b) Initial metal
thickness dependence on NC size distribution for Pt NC at identical NC anneal
temperature.
Fig. 3. Thickness and temperature dependence of NC size for Au NCs. NC
size is impacted significantly more by the initial metal deposition thickness
compared to anneal temperature.
an Agilent 4156C semiconductor parameter analyzer to obtain
flatband voltage (VFB ) values for these devices. Constant
capacitance method is used for the extraction of VFB shift.
Separation between the P- and E-state VFB ’s obtained from the
P and E transients, respectively, at saturation is defined as the
memory window of the devices. EOT of the capacitors used is
∼ 93 Å. Devices Au-S3, Au-S4, Au-S5, and Au-S12 showed
very high gate leakage (will be discussed later), making CV
measurements difficult. No further electrical measurements
could therefore be performed on these wafers.
1) P/E Transients: Fig. 5(a) shows the P/E transient for the
Pt-S1 device at VG of ±18 to ±20 V. In the figure, the VFB of
the device is plotted against the P/E time. A fresh device shows
high VFB of nearly 1.2 V. The device can be programmed by
application of positive VG to large positive VFB (P-state) and
can then be erased from high VFB P-state to low VFB E-state on
application of negative VG . Increasing the programming gate
voltage (VGP ) from +18 to +20 V increases the saturation
P-state VFB from 6.8 to 8.2 V. Similarly, an increase (negative)
in the erase gate voltage (VGE ) from −18 to −20 V increases
(negative) E-state VFB from −0.2 to −1.4 V. P- and E-states
do not show saturation with increasing VG . At a particular VG ,
P/E saturation is observed to set in at nearly 10 ms. The devices
also show overerase, which is the erase below the fresh device
2068
Fig. 5. (a) P/E transient for Pt-S1 devices at different gate voltage showing
overerase. (b) P/E memory window at different gate voltage for Au-S2 and
Au-S11 and Pt-S1 devices. Faster P/E and larger window are observed for
Au-S11 compared to Au-S2. In addition, Pt NC devices show larger memory
window than Au NC devices.
VFB as shown in Fig. 5(a). From the erase level, the device can
be programmed again to the same saturation level as the fresh
device. The results in Fig. 5(a) show the general P/E transient
behavior of all SL (Au and Pt) NC devices.
2) Memory Window: Fig. 5(b) shows the memory window
of Au and Pt devices programmed at equal VG . All devices have
been erased at identical VG = −21 V for 10 ms. Device Au-S11
(unannealed) shows larger memory window than Au-S2 (unannealed). The difference in memory window of Au-S11 and
Au-S2 is larger at lower VG and reduces at higher VG . The
memory windows of Au-S11 and Au-S2 at +16 and +20 V
are (4.7 and 3.75 V) and (7.05 and 6.5 V), respectively. The
extracted analytical data (in Table I) indicate larger AC and
ND in Au-S11 than in Au-S2. This difference in AC and ND is
suspected to be the cause of larger memory window in Au-S11
compared to Au-S2.
Devices Pt-S1 (5 Å) and Pt-S3 (10 Å) with ACs of 26%
and 30% and NDs of 3.4 × 1012 and 2.5 × 1012 cm−2 show
significantly larger memory windows compared to both Au
NC devices because of both the increased AC and higher ND.
A small dependence of NC size/AC on the memory window
is also observed. Device Pt-S3 with an average NC size/AC
of 3.6 nm/30% shows a slightly larger memory window than
Pt-S1 with an average NC size of 2.8 nm/26%. Almost identical
separation of ∼0.2 V in VFB is noted at all gate voltages. Larger
memory window in Pt-S3 suggests a stronger dependence of
memory window on AC and NC size compared to ND. Small
difference in memory window between Pt-S1 and Pt-S3 sug-
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 9, SEPTEMBER 2009
Fig. 6. (a) Precycling room-temperature retention for Au-S2 and Au-S11 and
Pt-S1 devices. Au-S11 device shows marginally better retention than Au-S2.
(b) High-temperature retention data of Pt-S1 device show no change in retention
characteristics even at 150-◦ C retention.
gests that QC is not significant at the NC dimension achieved
in this paper, as change in WF of the NC due to QC would have
affected the memory window [15].
Large memory window is obtained for the device due to
significant overerase that is observed in these devices as shown
in the P/E transients in Fig. 5(a). Memory window of nearly
10 V can be achieved for the Pt NC devices. Such a high
memory window is possible due to the use of optimized lowleakage Al2 O3 CD which blocks the leakage of electrons
injected into the NC during program, resulting in saturation
at higher positive VFB . During erase, electron injection from
the CG is suppressed, resulting in the observed overerase. An
unoptimized film would result in higher leakage through the
CD during both program and erase, causing saturation at lower
VFB and hence reducing the memory window. This results
in the smaller P/E speed and memory window observed in
the transients. Slight overerase is observed in both Au-S2 and
Au-S11, indicating minimal injection of electrons from the top
electrode during erase due to the use of optimized low-leakage
Al2 O3 as CD.
Even though, when compared with Pt, the memory window
for Au NC devices is small, it is possible to achieve an appreciable memory window of ∼7 V in these devices. Saturation
in the memory window is observed at higher biases. Pt devices
do not show saturation in memory window, and the memory
window continuously increases until 22-V operation, giving
∼10-V memory window. On application of VG larger than
±22 V, device breakdown is observed.
3) Retention: Retention experiments were performed on
both Au and Pt devices to investigate the reliability. Fig. 6(a)
SINGH et al.: PERFORMANCE AND RELIABILITY OF Au AND Pt SL METAL NC FLASH MEMORY
shows the results of room-temperature retention measurements
performed with 0 V applied at all terminals during the measurement. Change in VFB is plotted against the retention time.
During the measurement, retention stress is stopped and VFB is
measured at predetermined time intervals. Precycling retention
loss of these devices after 104 s was found to be close to 0.35
and 0.4 V for Au-S11 and Au-S2, respectively. Retention loss
is found to be larger for Au-S2 sample than that for Au-S11.
The retention loss of both Au samples is found to be larger than
that of the Pt sample which showed a loss of only about 0.2 V
after 104 s. One of the possible reasons for better retention of Pt
devices is the larger WF of Pt (5.3 eV) which results in a deeper
quantum well compared to Au (5.0 eV). The retention loss of
the Au NC devices is thus deemed to be poor and inadequate
for Flash memory requirement.
High-temperature retention studies were performed on Pt-S1
device to check for the long-term charge stability. Fig. 6(b)
shows the retention loss from both the P- and E-state VFB ’s at
25-◦ C, 80-◦ C, and 150-◦ C temperatures. For this measurement,
chuck temperature is raised to the specified value, and the
retention measurement is performed with 0 V at all terminals.
No significant effect of temperature was observed on the E-state
retention. The charge gain from E-state remains constant with
changing retention temperature. The P-state retention, although
does show some dependence, is very small and can be neglected. The charge loss increases from −0.2 V at 25 ◦ C
to −0.25 V at 150 ◦ C. The observed good high-temperature
retention indicates CD (Al2 O3 ) with low trap density and/or
deep traps which do not participate in electrical conduction
at low retention fields. The assumption here is that retention
loss is expected to be primarily through the CD as it is prone
to defects generated during the sputter deposition. Details of
retention studies will be published elsewhere.
4) Endurance: Fig. 7(a) shows the cycling endurance results for Au NC devices Au-S2 and Au-S11, where the P/E
VFB ’s are plotted against the P/E cycle number. It is observed
that for a memory window of ∼4 V, the devices could only
be cycled for nearly 1 × 103 cycles before breakdown. Breakdown is defined as the sudden loss of programmability of
these devices. Approximately 0.5-V memory window closure
is observed for both Au-S2 and Au-S11 devices with P- and
E-states moving toward each other. P-state VFB continuously
falls, while the E-state VFB rises with cycling. This indicates
degradation and electron trapping in the gate dielectric during
cycling.
In spite of the better retention of the Pt devices, they still
show poor endurance characteristics. Fig. 7(b) shows the results
of cycling endurance measurements for Pt NC devices Pt-S1
and Pt-S3. Pt devices could not be cycled for more than 4 × 103
cycles before breakdown. As in the case of Au NC, breakdown
causes a sudden loss of programmability of the devices. Even
though this is an improvement over Au NC, it is still not
sufficient to meet the required specification of 104 cycles [23].
Both P- and E-state VFB ’s are observed to move toward lower
VFB with increasing cycles while still retaining the original
memory window. In contrast, Au NC device cycling endurance
shows a window closure of ∼0.5 V before breakdown. The
E-state VFB of Pt devices shifts by nearly −0.2 V before
2069
Fig. 7. (a) Cycling endurance characteristics for Au-S2 and Au-S11 devices.
A window closure of ∼0.4 and 0.35 V is observed for Au-S2 and Au-S11,
respectively. (b) Endurance characteristics of Pt-S1 and Pt-S3 devices with
varying memory window. No memory window closure is observed in Pt NC
devices, but both P- and E-states are found to move to more negative VFB with
cycling.
breakdown, indicating permanent positive charge trapping in
the gate dielectric. The permanent positive charge trapping in
the gate stack of Pt NC devices is possibly due to the hole
injection from the substrate during erase [24].
In one of our recent work [24], it has been shown that the
degradation in the Pt NC gate stack is caused primarily by hole
injection during erase and the negative shift of P/E levels is due
to the permanent hole trapping in the CD. A sudden loss of
programmability is due to formation of leakage path between
the channel and CG, which prevents further P/E operation on
the NC. It is also shown that dual-layer (DL) Pt NC devices are
able to meet the 104 cycling endurance requirement for MLC
flash, the discussion of which is beyond the scope of this paper.
For consideration of space, the results are not reproduced here.
5) Postcycling Characteristics: Even though the devices
could not be cycled for full 104 cycles, postcycling retention of
Pt devices after 1 × 103 cycles does not show any significant
change from precycling characteristics. Fig. 8(a) shows the
comparison of pre- and postcycling retention measurements of
Pt-S1 device after 103 cycles. Fig. 8(b) shows the P/E transient
comparison of Pt NC device, before and after 103 cycles. No
degradation in the P/E transients and the memory window is
observed after cycling. Au NC devices show increased retention
loss and closure of memory window after cycling. In Flash
memory devices, degradation of the gate dielectric occurs due
to P/E cycling and causes an increase in the retention loss [23].
The increase of the charge loss depends upon the generation
2070
Fig. 8. (a) Pre- and postcycling comparison for Pt NC SL devices after 103
cycles shows no degradation in the retention characteristics. (b) P/E transient
comparison before and after 103 P/E cycles.
of traps in the gate dielectric due to tunnelling of carriers
during P/E operation. Similarly, an increase in bulk traps in
the gate dielectric will result in degradation of P/E transients.
Only marginal change in the retention loss and memory window
and P/E transients between pre- and postcycling characteristics
suggests low defect generation and robust performance of the
Pt NC devices before breakdown.
C. Physical Failure Mechanism
QSCV measurements could not be performed on any of the
10-Å Au NC devices (Au-S3, Au-S4, Au-S5, and Au-S12). The
cause of this is found to be the high gate leakage observed
from these devices. Fig. 9(a) shows the gate current versus
gate voltage for 5-Å (Au-S11) and 10-Å (Au-S12) devices. It is
observed that the gate leakage of Au-S12 is orders of magnitude
higher than that of Au-S11 and that the breakdown voltage is
significantly lower. This high gate leakage is responsible for the
inability to perform QSCV measurements. Hence, no further
electrical measurements have been performed on the 10-Å
samples in this paper. Gate leakage of the NC devices is also observed to be dependent on the NC anneal temperature. Fig. 9(b)
shows the IG versus VG plot of 5-Å Au devices (Au-S2,
Au-S3, Au-S4, and Au-S11) which received NC anneal at
different temperature but identical duration. Gate leakage is
found to increase with increasing NC anneal temperature in
the following order: Tanneal (Au-S4) > Tanneal (Au-S3) >
Tanneal (Au-S2) > Tanneal (Au-S11, unannealed). Breakdown
voltage follows the reverse trend. Larger gate leakage of the
Au-S2 devices compared to the Au-S11 can also contribute
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 9, SEPTEMBER 2009
Fig. 9. (a) Gate leakage comparison between Au-S11 and Au-S12. Very large
leakage is observed for Au-S12. (b) Gate leakage comparison in Au NC devices
with increasing anneal temperature. Au-S3 and Au-S4 have higher NC anneal
temperature than Au-S2 and Au-S11 (unannealed). They show larger leakage
and lower breakdown voltage compared to Au-S2 and Au-S11.
toward the lower observed memory window for Au-S2. Gateleakage and breakdown-voltage dependence on initial metal
thickness and NC anneal temperature suggests a temperaturedependent mechanism.
Fig. 10 shows the cross-sectional TEM along with electron
diffraction (EDX) for Au NC samples performed at position 4.
EDX shows the presence of trace amounts of Au and Cu atoms
in the dielectric close to NC, whereas the signal is undetectable
at a sufficient distance from the NC (site 1). Au and Cu signals
from EDX are below the detection limit in the unannealed Au
sample. EDX taken at the center of NC (position 3) is also
shown for comparison. Lower melting point of Au NC [21],
[22] compared to bulk Au metal causes diffusion of metal
atoms into the gate dielectric during NC anneal. Post (Al2 O3 )
deposition anneal is also suspected to cause the diffusion of
the metal atoms in the film, but the effect is significantly
smaller. The EDX of Au NC samples is consistent with the
observed electrical behavior. EDX is not performed for the Pt
NC samples as their gate leakage is found to be independent of
NC anneal conditions.
Diffusion of Au and Cu into the gate stack during NC anneal
increases the gate leakage. Higher gate current leakage from
the NC/CG during P/E operation is also possible for the smaller
memory window of Au NC devices compared to Pt devices.
An increase in gate leakage is also a possibility, along with
smaller WF of Au, for the observed poor retention of the
Au NC devices compared to Pt NC devices. The memory
SINGH et al.: PERFORMANCE AND RELIABILITY OF Au AND Pt SL METAL NC FLASH MEMORY
2071
AC and ND compared to previous works. This, along with the
use of optimized low-leakage Al2 O3 , allows us to achieve large
memory window of ∼7 V in Au and ∼10 V in Pt NC devices.
Pt devices show a larger memory window and better retention
characteristics than Au NC devices. Although the endurance
characteristics improve in Pt SL devices over Au NC, only
4 × 103 P/E cycles could be achieved for Pt devices, which
is still lower than the required specification of 104 cycles. Pt
device postcycling (after 103 cycles) retention, P/E speed, and
memory window did not show any degradation from the precycling characteristics. Good retention is observed for Pt devices,
while slightly larger loss is observed in Au devices. Au (and
Cu impurity in the target) metal atoms were found to diffuse
into the TO and CD, causing reliability issues like lowering of
breakdown voltage, poor retention, and cycling endurance in
the Au NC memory devices. It is therefore concluded that the
Au metal NC may be unsuitable for NC flash application. Pt
NC devices are a viable option for MLC operation at below
3× node, provided that cycling endurance can be improved
further to meet the required specification necessary for NAND
application. The use of other structures like DL metal NC
must be investigated in detail as they have been shown to have
better cycling endurance than SL, which may be sufficient to
meet the MLC cycling endurance requirement. Although the asdeposited Al2 O3 film is found to be of sufficiently good quality,
defect generation leading to device breakdown is observed in all
SL devices with P/E cycling. Therefore, further improvement in
the quality of high-k CD and optimization of P/E conditions to
minimize defect generation and improve cycling endurance are
also essential. In conclusion, Pt NC devices show promise with
large memory window and good retention. Further investigation
is required to prove their reliability.
R EFERENCES
Fig. 10. (a) Cross-sectional TEM with EDX locations. (b) EDX pattern of AuS2 (annealed) at position 4. (c) Au-S11 (unannealed) at position 4. (d) EDX at
center of NC (position 3) for comparison. EDX of Au-S2 shows the presence
of trace amounts of Au and Cu in the TO.
window closure and positive movement of E-state VFB in the
Au cycling endurance can be explained by permanent trapping
in the traps generated by metal diffusion in the gate dielectric.
Pt devices do not show metal diffusion and hence have better
performance and reliability compared to Au devices. No degradation in the postcycling retention and P/E characteristics is
observed in Pt devices before breakdown.
IV. CONCLUSION
Au and Pt metal-based NC memory devices have been investigated in this paper as a potential replacement for FG flash
below 3× node. Both Pt and Au NC devices show excellent
[1] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories.
Boston, MA: Kluwer, 1999.
[2] International Technology Roadmap for Semiconductors, ITRS, 2007.
[Online]. Available: http://www.itrs.net
[3] G. Chindalore, J. Yater, H. Gasquet, M. Suhail, S.-T. Kang, C. M. Hong,
N. Ellis, G. Rinkenberger, J. Shen, M. Herrick, W. Malloch, R. Syzdek,
K. Baker, and K.-M. Chang, “Embedded split-gate flash memory with
silicon nanocrystals for 90 nm and beyond,” in VLSI Symp. Tech. Dig.,
2008, pp. 136–137.
[4] J. H. Chen, Y. Q. Wang, W. J. Yoo, Y.-C. Yeo, G. Samudra, D. S. Chan,
A. Y. Du, and D.-L. Kwong, “Nonvolatile flash memory device using Ge
nanocrystals embedded in HfAlO High-k tunneling and control oxides:
Device fabrication and electrical performance,” IEEE Trans. Electron
Devices, vol. 51, no. 11, pp. 1840–1848, Nov. 2004.
[5] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal
memories—Part I: Device design and fabrication,” IEEE Trans. Electron
Devices, vol. 49, no. 9, pp. 1606–1613, Sep. 2002.
[6] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—Part II: Electrical characteristics,” IEEE Trans. Electron
Devices, vol. 49, no. 9, pp. 1614–1622, Sep. 2002.
[7] C. Lee, J. Meteer, V. Narayanan, and E. C. Kan, “Self-assembly of metal
nanocrystals on ultrathin oxide for nonvolatile memory applications,”
J. Electron. Mater., vol. 34, no. 1, pp. 1–11, Jan. 2005.
[8] T.-H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, “Design
optimization of metal nanocrystal memory—Part I: Nanocrystal array
engineering,” IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3095–
3102, Dec. 2006.
[9] T.-H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, “Design
optimization of metal nanocrystal memory—Part II: Gate-stack engineering,” IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3103–3108,
Dec. 2006.
2072
[10] M. She and T.-J. King, “Impact of crystal size and tunnel dielectric on
semiconductor nanocrystal memory performance,” IEEE Trans. Electron
Devices, vol. 50, no. 9, pp. 1934–1940, Sep. 2003.
[11] J. J. Lee and D. L. Kwong, “Metal nanocrystal memory with high-k tunneling barrier for improved data retention,” IEEE Trans. Electron Devices,
vol. 52, no. 4, pp. 507–511, Apr. 2005.
[12] S. K. Samanta, P. K. Singh, W. J. Yoo, G. Samudra, Y.-C. Yeo,
L. K. Bera, and N. Balasubramanian, “Enhancement of memory window
in short channel nonvolatile memory devices using double layer tungsten
nanocrystals,” in IEDM Tech. Dig., 2005, pp. 170–173.
[13] C. Sandhya, U. Ganguly, K. K. Singh, P. K. Singh, C. Olsen, S. M. Seutter,
R. Hung, G. Conti, K. Ahmed, N. Krishna, J. Vasi, and S. Mahapatra,
“Nitride engineering and the effect of interfaces on charge trap flash
performance and reliability,” in Proc. IEEE Int. Rel. Phys. Symp., 2008,
pp. 406–411.
[14] C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date,
R. Hung, J. Vasi, and S. Mahapatra, “Effect of SiN on performance and
reliability of charge trap flash (CTF) under Fowler–Nordheim tunneling
program/erase operation,” IEEE Electron Device Lett., vol. 30, no. 2,
pp. 171–173, Feb. 2009.
[15] W. Guan, S. Long, M. Liu, Q. Liu, Y. Hu, Z. Li, and R. Jia, “Modeling of
retention characteristics for metal and semiconductor nanocrystal memories,” Solid State Electron., vol. 51, no. 5, pp. 806–811, May 2007.
[16] T. Shan, C. Mao, Y. Liu, D. Q. Kelly, and S. K. Banerjee, “Proteinmediated nanocrystal assembly for flash memory fabrication,” IEEE
Trans. Electron Devices, vol. 54, no. 3, pp. 433–438, Mar. 2007.
[17] K. S. Seol, S. J. Choi, J.-Y. Choi, E.-J. Jang, B.-K. Kim, S.-J. Park,
D.-G. Cha, I.-Y. Song, J.-B. Park, Y. Park, and S.-H. Choi, “Pdnanocrystal-based nonvolatile memory structures with asymmetric
SiO2 /HfO2 tunnel barrier,” Appl. Phys. Lett., vol. 89, no. 8, pp. 083 1091–083 109-3, Aug. 2006.
[18] R. Hofmann and N. Krishna, “Self-assembled metallic nanocrystal structures for advanced nonvolatile memory applications,” Microelectron.
Eng., vol. 85, no. 10, pp. 1975–1978, Oct. 2008.
[19] P. K. Singh, K. K. Singh, R. Hofmann, K. Armstrong, N. Krishna, and
S. Mahapatra, “Au nanocrystal flash memory reliability and failure analysis,” in Proc. 15th Int. Symp. Phys. Failure Anal. Integr. Circuits, 2008,
p. 214.
[20] A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi, and
S. Mahapatra, “Development of a 3D simulator for metal nanocrystal
(NC) flash memories under NAND operation,” in IEDM Tech. Dig., 2007,
pp. 947–950.
[21] P. Buffat and J.-P. Borel, “Size effect on the melting temperature of
gold particles,” Phys. Rev. A, Gen. Phys., vol. 13, no. 6, pp. 2287–2298,
Jun. 1976.
[22] Q. Jiang, S. Zhang, and M. Zhao, “Size-dependent melting point of noble
metals,” Mater. Chem. Phys., vol. 82, no. 1, pp. 225–227, 2003.
[23] N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares,
F. Trivedi, E. Goodness, and L. R. Nevill, “Bit error rate in NAND flash
memories,” in Proc. IEEE IRPS, 2008, pp. 9–19.
[24] P. K. Singh, G. Bisht, M. Sivatheja, C. Sandhya, R. Hofmann, K. Singh,
G. Mukhopadhyay, N. Krishna, and S. Mahapatra, “Reliability of single
and dual layer Pt nanocrystal devices for NAND flash applications: A
2-region model for endurance defect generation,” in Proc. IEEE IRPS,
2009, pp. 301–306.
Pawan K. Singh (S’07) received the B.Tech. and
M.Tech. combined degrees from the Department of
Electrical Engineering, Indian Institute of Technology (IIT) Bombay, Mumbai, India, in 2006, where
he has been working toward the Ph.D. degree in
electrical engineering.
From June 2007 to July 2008, he was a Graduate Intern with Applied Materials, Santa Clara,
CA. His research interests include technology development, physics, and reliability characterization
of nonvolatile memories. He is currently working on
metal-nanocrystal-based nonvolatile memories for NAND application.
Mr. Singh has received AMAT fellowship for Ph.D. in IIT Bombay
since 2006.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 9, SEPTEMBER 2009
Ralf Hofmann received the Diplom-Ingenieur degree in electrical engineering
(MSEE) from Chemnitz University of Technology, Chemnitz, Germany.
He joined Applied Materials, Santa Clara, CA, in 1994, in the PVD Technology group, working on various aspects of metal deposition and process
integration. In 2001, he joined ZMD America, Inc., a mixed-signal ASIC design
company, where he worked on two successfully produced IC designs. From
2002 to 2003, he was an Independent Consultant with a telecommunications
start-up company as well as a small company in the transportation sector before
rejoining Applied Materials in 2004. He is currently a Member of Technical
Staff in the Advanced Technology Group under the Office of the CTO at
Applied Materials. His work involves the evaluation and development of new
processing techniques and equipment for new and emerging applications in the
IC space as well as the energy sector.
Kaushal K. Singh is a Senior Member of Technical Staff at Applied Materials,
Santa Clara, CA.
Nety Krishna received the M.Sc. degree in physics from the Indian Institute
of Technology (IIT), Kanpur, India, in 1984, and the M.S. and Ph.D. degrees
in particle physics from Rice University, Houston, TX, in 1988 and 1989,
respectively.
Since 1995, he has been with Applied Materials, Santa Clara, CA, working
on advanced process solutions for transistor and interconnect areas.
Souvik Mahapatra (M’02–SM’07) received the
Ph.D. degree in electrical engineering from the Indian Institute of Technology (IIT) Bombay, Mumbai,
India, in 1999.
From 2000 to 2001, he was with Bell Laboratories,
Murray Hill, NJ. Since 2002, he has been with the
Department of Electrical Engineering, IIT Bombay,
where he is currently a Professor. He has published
more than 85 papers in peer-reviewed journals and
conferences; delivered invited talks at leading international conferences in the U.S., Europe, and Asia
pacific, including at the IEEE IEDM; delivered reliability tutorials at the IEEE
IRPS; and acted as a Reviewer of several international journals and conferences.
He also holds an honorary graduate faculty position with Purdue University,
West Lafayette, IN. He is a Distinguished Lecturer of IEEE EDS. His research
interests are in the area of characterization, modeling, and simulation of CMOS
and Flash memory devices, and device reliability.