‫ﺯﺑﺎﻥ ﻫﺎﻱ ﺗﻮﺻﻴﻒ ﺳﺨﺖ ﺍﻓﺰﺍﺭ‬
‫ﭘﺎﻳﻴﺰ ‪90‬‬
‫ﭘﺮﻭژﻩ ‪SYSTEMC‬‬
‫ﺳﻮﺍﻝ ‪1‬‬
‫ﺩﺭ ﺍﻳﻦ ﺳﻮﺍﻝ ﺑﺎﻳﺪ ﺳﺎﺧﺘﺎﺭ ﻳﻚ ﺗﻘﺴﻴﻢ ﻛﻨﻨﺪﻩ ﺭﺍ ﺩﺭ ﺳﻄﺢ ﺳﺎﺧﺘﺎﺭﻱ ﺑﻪ ﺯﺑﺎﻥ ‪ SystemC‬ﻃﺮﺍﺣﻲ ﻛﻨﻴﺪ‪.‬‬
‫‪ .1‬ﺍﺑﺘﺪﺍ ﺩﻭ ﻣﺎژﻭﻝ ‪ FA‬ﻭ ‪ XOR‬ﺭﺍ ﻃﺮﺍﺣﻲ ﻧﻤﻮﺩﻩ ﻭ ﺍﺯ ﺁﻧﻬﺎ ﺩﺭ ﻃﺮﺍﺣﻲ ﻣﺎژﻭﻝ ‪ CAS‬ﻣﻄﺎﺑﻖ ﺷﻜﻞ ﺯﻳﺮ ﺍﺳﺘﻔﺎﺩﻩ‬
‫ﻛﻨﻴﺪ‪ 25) .‬ﺍﻣﺘﻴﺎﺯ(‬
‫‪ .2‬ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻣﺎژﻭﻝ ﺑﺎﻻ ‪ ،‬ﺑﺎﻳﺪ ﺗﻘﺴﻴﻢ ﻛﻨﻨﺪﻩ ﻣﻮﺍﺯﻱ ‪ 8‬ﺑﻴﺘﻲ ﻛﻪ ﺩﺭ ﺯﻳﺮ ﺁﻭﺭﺩﻩ ﺷﺪﻩ ﺍﺳﺖ ﺭﺍ ﻃﺮﺍﺣﻲ ﻛﻨﻴﺪ ‪ .‬ﺑﺎ‬
‫ﺗﻮﺟﻪ ﺑﻪ ﺍﻳﻨﻜﻪ ﻣﻘﺴﻮﻡ ) ‪ (dividend‬ﺩﺭ ﺍﻟﮕﻮﺭﻳﺘﻢ ﺗﻘﺴﻴﻢ ﻣﻮﺍﺯﻱ ﺩﺭ ﺍﺑﺘﺪﺍ ﻳﻚ ﺑﻴﺖ ﺷﻴﻔﺖ ﺩﺍﺩﻩ ﻣﻲ ﺷﻮﺩ ﺳﺎﺧﺘﺎﺭ‬
‫ﺗﻘﺴﻴﻢ ﻛﻨﻨﺪﻩ ﺷﻜﻞ ﺯﻳﺮ ﻣﻘﺴﻮﻡ )‪ (dividend‬ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﻋﺪﺩ ‪ 7‬ﺑﻴﺘﻲ ﺩﺭﻳﺎﻓﺖ ﻛﺮﺩﻩ ﻭ ﭘﺲ ﺍﺯ ﺗﻘﺴﻴﻢ ﺁﻥ‬
‫ﺑﺮ ﻣﻘﺴﻮﻡ ﻋﻠﻴﻪ )‪ 4 (divisor‬ﺑﻴﺘﻲ‪ ،‬ﺑﺎﻗﻲ ﻣﺎﻧﺪﻩ )‪ (remainder‬ﻭ ﺧﺎﺭﺝ ﻗﺴﻤﺖ ) ‪ 4 (quotient‬ﺑﻴﺘﻲ ﻣﺘﻨﺎﺳﺐ‬
‫ﺭﺍ ﺗﻮﻟﻴﺪ ﻣﻲ ﻛﻨﺪ‪ 60) .‬ﺍﻣﺘﻴﺎﺯ(‬
‫ﺑﺮﻧﺎﻣﻪ ﺗﺴﺘﻲ ﺑﻨﻮﻳﺴﻴﺪ ﻛﻪ ﭼﻨﺪﻳﻦ ﻋﺪﺩ ﺭﺍ ﺍﺯ ﻭﺭﻭﺩﻱ ﻣﺪﺍﺭﻱ ﻛﻪ ﻃﺮﺍﺣﻲ ﻛﺮﺩﻩ ﺍﻳﺪ‪ ،‬ﺭﺍ ﮔﺮﻓﺘﻪ ﻭ ﺑﻪ ﻛﻤﻚ ﺁﻧﻬﺎ‬
‫ﺻﺤﺖ ﻋﻤﻠﻜﺮﺩ ﻣﺪﺍﺭ ﻃﺮﺍﺣﻲ ﺷﺪﻩ ﺭﺍ ﺑﺮﺭﺳﻲ ﻛﻨﻴﺪ‪.‬‬
‫ﺯﺑﺎﻥ ﻫﺎﻱ ﺗﻮﺻﻴﻒ ﺳﺨﺖ ﺍﻓﺰﺍﺭ‬
‫ﭘﺎﻳﻴﺰ ‪90‬‬
‫ﺳﻮﺍﻝ ‪2‬‬
‫ﺩﺭ ﺍﻳﻦ ﺗﻤﺮﻳﻦ ﺑﺎﻳﺪ ﻭﺍﺣﺪ ‪ ALU74181‬ﺭﺍ ﺳﻄﺢ ﺩﻟﺨﻮﺍﻩ )ﺭﻓﺘﺎﺭﻱ ﻳﺎ ﺳﺎﺧﺘﺎﺭﻱ( ﺩﺭ ﺯﺑﺎﻥ ‪ SystemC‬ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﻛﻨﻴﺪ‪.‬‬
‫‪U‬‬
‫‪U‬‬
‫ﺍﻳﻦ ‪ ALU‬ﺷﺎﻣﻞ ﻋﻠﻤﻴﺎﺕ ﻣﻨﻄﻘﻲ ﻭ ﺣﺴﺎﺑﻲ ﺑﻪ ﻃﻮﺭ ﺟﺪﺍﮔﺎﻧﻪ ﺍﺳﺖ ﻭ ﺗﻤﺎﻳﺰ ﺑﻴﻦ ﺍﻳﻦ ﺩﻭ ﺩﺳﺘﻪ ﻋﻤﻠﻴﺎﺕ ﺑﺎ ﻭﺭﻭﺩﻱ ﻫﺎﻱ‬
‫‪ M, Cn‬ﻣﺸﺨﺺ ﻣﻲ ﺷﻮﺩ‪ .‬ﺑﺮﺍﻱ ﺁﮔﺎﻫﻲ ﺍﺯ ﺟﺰﺋﻴﺎﺕ ﺑﻴﺸﺘﺮ ﻣﻲ ﺗﻮﺍﻧﻴﺪ ﺑﻪ ﺟﺪﻭﻝ ﺯﻳﺮ ﻳﺎ‬
‫‪ Datasheet‬ﺍﻳﻦ ‪ IC‬ﻣﺮﺍﺟﻌﻪ‬
‫‪U‬‬
‫‪U‬‬
‫ﻛﻨﻴﺪ‪.‬‬
‫ﭘﺲ ﺍﺯ ﻧﻮﺷﺘﻦ ﻛﺪ ﻣﺮﺑﻮﻃﻪ‪ ،‬ﻻﺯﻡ ﺍﺳﺖ‪ ،‬ﺁﺯﻣﻮﻧﻲ )‪ (TestBench‬ﺑﺮﺍﻱ ﺍﻳﻦ ﻣﺎژﻭﻝ ﻧﻮﺷﺘﻪ ﻭ ﺻﺤﺖ ﻣﺪﺍﺭ ﻃﺮﺍﺣﻲ ﻛﺮﺩﻩ ﺭﺍ‬
‫ﺑﺴﻨﺠﻴﺪ‪ 60) .‬ﺍﻣﺘﻴﺎﺯ(‬
‫ﺯﺑﺎﻥ ﻫﺎﻱ ﺗﻮﺻﻴﻒ ﺳﺨﺖ ﺍﻓﺰﺍﺭ‬
‫ﭘﺎﻳﻴﺰ ‪90‬‬
‫ﺳﻮﺍﻝ ‪3‬‬
‫‪ .1‬ﺩﺭ ﺍﻳﻦ ﺗﻤﺮﻳﻦ ﺑﺎﻳﺪ ﺑﻪ ﻛﻤﻚ ‪ SystemC‬ﻳﻚ ‪ FIFO‬ﺑﺎ ﻇﺮﻓﻴﺖ ‪ 4‬ﺍﻟﻤﺎﻥ ﺭﺍ ﺑﺮﺍﻱ ﺑﺴﺘﻪ ﻫﺎﻱ ﺷﺒﻜﻪ ﺩﺭ ﻳﻚ‬
‫‪ Router‬ﺩﺭ ﺳﻄﺢ ﺗﺠﺮﻳﺪ ﺩﻟﺨﻮﺍﻩ ﻃﺮﺍﺣﻲ ﻛﻨﻴﺪ‪ .‬ﺩﻳﺎﮔﺮﺍﻡ ﺑﻠﻮﻛﻲ ﺍﻳﻦ ﺳﺎﺧﺘﺎﺭ ﺩﺭ ﺯﻳﺮ ﺁﻭﺭﺩﻩ ﺷﺪﻩ ﺍﺳﺖ‪.‬‬
‫ﺍﻳﻦ ‪ 2 FIFO‬ﻭﺭﻭﺩﻱ ﺩﺍﺭﺩ‪ Packet_in ،‬ﻛﻪ ﺑﺮﺍﻱ ﺍﺭﺳﺎﻝ ﻣﻮﺍﺯﻱ ﺩﺍﺩﻩ ﺑﻪ ﺩﺍﺧﻞ ‪ FIFO‬ﺍﺳﺖ ﻭ ﻳﻚ ﺳﻴﮕﻨﺎﻝ ﻛﻨﺘﺮﻟﻲ‬
‫‪ Read‬ﻛﻪ ﺍﮔﺮ ﺑﺮﺍﺑﺮ ﺑﺎ ‪ 0‬ﺑﺎﺷﻴﺪ ﺧﺮﻭﺟﻲ ‪ Packet_out‬ﺩﺭ ﺣﺎﻟﺖ ‪ (High_Impedence) Z‬ﺍﺳﺖ ﻭ ﺍﮔﺮ ‪ 1‬ﺑﺎﺷﺪ‪،‬‬
‫ﺍﻭﻟﻴﻦ ﺩﺍﺩﻩ ﺩﺭ ‪ FIFO‬ﺑﺮ ﺭﻭﻱ ‪ Packet-out‬ﺍﺭﺳﺎﻝ ﻣﻲ ﺷﻮﺩ‪ .‬ﺳﻴﮕﻨﺎﻝ ﺧﺮﻭﺟﻲ ‪ Ready‬ﻫﺮ ﺯﻣﺎﻧﻲ ﻛﻪ ﺩﺍﺩﻩ ﻣﻌﺘﺒﺮ ﺑﺮ‬
‫ﺭﻭﻱ ﺧﺮﻭﺟﻲ ‪ Packet_out‬ﺍﺭﺳﺎﻝ ﻣﻲ ﺷﻮﺩ‪ ،‬ﺑﻪ ‪ 1‬ﻣﻘﺪﺍﺭ ﺩﻫﻲ ﺧﻮﺍﻫﺪ ﺷﺪ‪ .‬ﺩﺭ ﻛﻞ ﺗﻤﺎﻡ ﻋﻤﻠﻜﺮﺩ ﻣﺪﺍﺭ ﺑﺎ ﻳﻚ‬
‫ﺳﻴﮕﻨﺎﻝ ‪ Clock‬ﺳﻨﻜﺮﻭﻥ ﺳﺎﺯﻱ ﻣﻲ ﺷﻮﺩ‪.‬‬
‫ﺑﺮﺍﻱ ﺍﻳﻦ ﻣﺪﺍﺭ ﻳﻚ ‪ TestBench‬ﺩﺭ ‪ SystemC‬ﺑﻨﻮﻳﺴﻴﺪ ﻭ ﻃﺮﺡ ﺧﻮﺩ ﺭﺍ ﺭﺍﺳﺖ ﺁﺯﻣﺎﻳﻲ ﻛﻨﻴﺪ‪ 30) .‬ﺍﻣﺘﻴﺎﺯ(‬
‫‪ .2‬ﺑﻪ ﻛﻤﻚ ﻣﺎژﻭﻝ ﻃﺮﺍﺣﻲ ﺷﺪﻩ ﺩﺭ ﻗﺴﻤﺖ ﺍﻭﻝ‪ ،‬ﺷﺒﻜﻪ ﺍﻱ ﺭﺍ ﺩﺭ ﻧﻈﺮ ﺑﮕﻴﺮﻳﺪ ﻛﻪ ﻳﻚ‪ FIFO‬ﺑﻪ ﻋﻨﻮﺍﻥ ﻓﺮﺳﺘﻨﺪﻩ ﻭ‬
‫ﻳﻚ‪ FIFO‬ﺑﻪ ﻋﻨﻮﺍﻥ ﮔﻴﺮﻧﺪﻩ ﻋﻤﻞ ﻣﻲ ﻛﻨﺪ‪ .‬ﻛﻞ ﺍﻳﻦ ﻣﺎژﻭﻝ ﺭﺍ ﺑﻪ ﻛﻤﻚ ﻣﺎژﻭﻝ ﻗﺴﻤﺖ ﺍﻭﻝ ﺗﻮﺻﻴﻒ ﻛﻨﻴﺪ ﻭ ﺑﺮﺍﻱ‬
‫ﺭﺍﺳﺖ ﺁﺯﻣﺎﻳﻲ ﺍﻳﻦ ﻣﺪﺍﺭ ‪ TestBench‬ﺑﻨﻮﻳﺴﻴﺪ‪ 50) .‬ﺍﻣﺘﻴﺎﺯ(‬
‫‪) .3‬ﺍﻣﺘﻴﺎﺯﻱ( ﺳﻨﺘﺰ ﻣﺪﺍﺭ ‪ FIFO‬ﺑﻪ ﻛﻤﻚ ﺍﺑﺰﺍﺭ ‪ Celloxica Agility Compiler‬ﻭ ﺍﺳﺘﺨﺮﺍﺝ ﻛﺪ ‪HDL‬‬
‫ﻣﺘﻨﺎﺳﺐ ﺑﺎ ﺍﻳﻦ ﻃﺮﺡ‪.‬‬
‫ﺍﻟﻒ( ﺩﺭ ﺍﻳﻦ ﻗﺴﻤﺖ ﺑﺎﻳﺪ ﺑﻪ ﻛﻤﻚ ﺍﺑﺰﺍﺭ ﻣﺬﻛﻮﺭ ﻭ ﺭﺍﻫﻨﻤﺎﻳﻲ ﺑﺎﺭﮔﺬﺍﺭﻱ ﺷﺪﻩ ﺩﺭ ﻗﺴﻤﺖ ﻣﻨﺎﺑﻊ ﺩﺭ ﺳﺎﻳﺖ ﺩﺭﺱ‪ ،‬ﻛﺪ‬
‫‪ HDL‬ﻣﺘﻨﺎﺳﺐ ﺑﺎ ﺁﻥ ﺭﺍ ﺍﺳﺘﺨﺮﺍﺝ ﻛﻨﻴﺪ‪ 20) .‬ﺍﻣﺘﻴﺎﺯ(‬
‫ﺏ( ﺑﻌﺪ ﺍﺯ ﺁﻥ ﻓﺎﻳﻞ ﻫﺎ ﻱ ‪ .v‬ﻳﺎ ‪ .vhd‬ﺍﺳﺘﺨﺮﺍﺝ ﺷﺪﻩ ﺭﺍ ﺑﻪ ﻛﻤﻚ ﻳﻚ ﺷﺒﻴﻪ ﺳﺎﺯ )‪ (ModelSim‬ﺷﺒﻴﻪ ﺳﺎﺯﻱ‬
‫ﻛﻨﻴﺪ ﻭ ﺍﺯ ﺻﺤﺖ ﻋﻤﻠﻜﺮﺩ ﺁﻥ ﺍﻃﻤﻴﻨﺎﻥ ﺣﺎﺻﻞ ﻛﻨﻴﺪ‪ 5) .‬ﺍﻣﺘﻴﺎﺯ(‬
‫ﺯﺑﺎﻥ ﻫﺎﻱ ﺗﻮﺻﻴﻒ ﺳﺨﺖ ﺍﻓﺰﺍﺭ‬
‫ﭘﺎﻳﻴﺰ ‪90‬‬
‫‪) .4‬ﺍﻣﺘﻴﺎﺯﻱ( ﺳﻨﺘﺰ ﻣﺪﺍﺭ ﻓﺮﺳﺘﻨﺪﻩ‪-‬ﮔﻴﺮﻧﺪﻩ ﺑﻪ ﻛﻤﻚ ﺍﺑﺰﺍﺭ ‪ Celloxica Agility Compiler‬ﻭ ﺍﺳﺘﺨﺮﺍﺝ ﻛﺪ‬
‫‪ HDL‬ﻣﺘﻨﺎﺳﺐ ﺑﺎ ﺍﻳﻦ ﻃﺮﺡ‪.‬‬
‫ﺍﻟﻒ( ﺩﺭ ﺍﻳﻦ ﻗﺴﻤﺖ ﺑﺎﻳﺪ ﺑﻪ ﻛﻤﻚ ﺍﺑﺰﺍﺭ ﻣﺬﻛﻮﺭ ﻭ ﺭﺍﻫﻨﻤﺎﻳﻲ ﺑﺎﺭﮔﺬﺍﺭﻱ ﺷﺪﻩ ﺩﺭ ﻗﺴﻤﺖ ﻣﻨﺎﺑﻊ ﺩﺭ ﺳﺎﻳﺖ ﺩﺭﺱ‪ ،‬ﻛﺪ‬
‫‪ HDL‬ﻣﺘﻨﺎﺳﺐ ﺑﺎ ﺁﻥ ﺭﺍ ﺍﺳﺘﺨﺮﺍﺝ ﻛﻨﻴﺪ‪ 50) .‬ﺍﻣﺘﻴﺎﺯ(‬
‫ﺏ( ﺑﻌﺪ ﺍﺯ ﺁﻥ ﻓﺎﻳﻞ ﻫﺎ ﻱ ‪ .v‬ﻳﺎ ‪ .vhd‬ﺍﺳﺘﺨﺮﺍﺝ ﺷﺪﻩ ﺭﺍ ﺑﻪ ﻛﻤﻚ ﻳﻚ ﺷﺒﻴﻪ ﺳﺎﺯ )‪ (ModelSim‬ﺷﺒﻴﻪ ﺳﺎﺯﻱ‬
‫ﻛﻨﻴﺪ ﻭ ﺍﺯ ﺻﺤﺖ ﻋﻤﻠﻜﺮﺩ ﺁﻥ ﺍﻃﻤﻴﻨﺎﻥ ﺣﺎﺻﻞ ﻛﻨﻴﺪ‪ 10) .‬ﺍﻣﺘﻴﺎﺯ(‬
‫ﺳﻮﺍﻝ ‪4‬‬
‫ﺩﺭ ﺍﻳﻦ ﺗﻤﺮﻳﻦ ﺑﺎﻳﺪ ﻭﺍﺣﺪﻱ ﺭﺍ ﻃﺮﺍﺣﻲ ﻛﻨﻴﺪ ﻛﻪ ﻓﺎﻛﺘﻮﺭﻳﻞ ﻋﺪﺩ ﻭﺭﻭﺩﻱ ) !‪ (in_data‬ﺭﺍ ﺣﺴﺎﺏ ﻛﻨﺪ ﻭ ﺧﺮﻭﺟﻲ ﺭﺍ ﺣﺴﺎﺏ‬
‫ﻛﻨﺪ‪ .‬ﺧﺮﻭﺟﻲ ﺑﺎﻳﺪ ﺑﻪ ﺻﻮﺭﺕ ‪ fac_out, exp_out‬ﻛﻪ ﺑﻪ ﺗﺮﺗﻴﺐ ﻗﺴﻤﺖ ﺍﻋﺸﺎﺭﻱ) ‪ (mantissa‬ﻭ ﺗﻮﺍﻥ ) ‪(exponent‬‬
‫ﻧﻤﺎﻳﺶ ﺩﺍﺩﻩ ﺷﻮﺩ‪ .‬ﻗﺴﻤﺖ ﺗﻮﺍﻥ )‪ (exponent‬ﺩﺭ ﻣﺒﻨﺎﻱ ‪ 2‬ﺍﺳﺖ‪ .‬ﺳﻴﮕﻨﺎﻝ ‪ reset‬ﻛﻞ ﻣﺪﺍﺭ ﺭﺍ ‪ reset‬ﻣﻲ ﻛﻨﺪ‪.‬‬
‫ﭘﺲ ﺍﺯ ﻧﻮﺷﺘﻦ ﻛﺪ ﻣﺮﺑﻮﻃﻪ‪ ،‬ﻻﺯﻡ ﺍﺳﺖ‪ ،‬ﺁﺯﻣﻮﻧﻲ )‪ (TestBench‬ﺑﺮﺍﻱ ﺍﻳﻦ ﻣﺎژﻭﻝ ﻧﻮﺷﺘﻪ ﻭ ﺻﺤﺖ ﻣﺪﺍﺭ ﻃﺮﺍﺣﻲ ﻛﺮﺩﻩ ﺭﺍ‬
‫ﺑﺴﻨﺠﻴﺪ‪ 70) .‬ﺍﻣﺘﻴﺎﺯ(‬
‫ﺗﻮﺟﻪ!‪ :‬ﻓﺮﻣﺖ ﻧﻤﺎﻳﺶ ﺧﻮﺍﺳﺘﻪ ﺷﺪﻩ ﺑﻪ ﺻﻮﺭﺕ 𝑒𝑒‪ 0.m × 2‬ﺍﺳﺖ )‪ exponent‬ﻭ ‪.(mantissa‬‬
‫ﺳﻮﺍﻝ ‪5‬‬
‫ﺳﻮﺍﻝ ﺍﻣﺘﻴﺎﺯﻱ‬
‫ﻃﺮﺍﺣﻲ ﻳﻚ ﮔﺬﺭﮔﺎﻩ ﻣﺸﺘﺮﻙ ﺑﺎ ﺩﺳﺘﺮﺳﻲ ﺑﺮ ﺍﺳﺎﺱ ﺩﺍﻭﺭﻱ ) ‪Common Data Bus with‬‬
‫‪(Arbiter‬‬
‫ﮔﺬﺭﮔﺎﻩ ﻫﺎﻱ ﻣﺸﺘﺮﻙ ﺗﻘﺮﻳﺒﺎ ﺩﺭ ﺗﻤﺎﻣﻲ ﺳﻴﺴﺘﻢ ﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻝ ﻭﺟﻮﺩ ﺩﺍﺭﻧﺪ‪ .‬ﻳﻚ ﺭﺍﻩ ﺳﺎﺩﻩ ﺍﺳﺘﻔﺎﺩﻩ ﻱ ﻣﺸﺘﺮﻙ ﺍﺯ ﺍﻳﻦ ﻣﻨﺒﻊ‪،‬‬
‫ﺭﺟﻮﻉ ﺑﻪ ﻳﻚ ﺩﺍﻭﺭ ﻭ ﻛﺴﺐ ﺍﺟﺎﺯﻩ ﺍﺯ ﻭﻱ ﭘﻴﺶ ﺍﺯ ﺩﺳﺘﺮﺳﻲ ﺑﻪ ﮔﺬﺭﮔﺎﻩ ﺍﺳﺖ‪ .‬ﺑﺎ ﺍﻳﻦ ﺭﻭﺵ‪ ،‬ﺩﺍﻭﺭ ﺩﺭ ﻫﺮ ﻟﺤﻈﻪ ﻣﻲ ﺩﺍﻧﺪ ﻛﻪ ﺁﻳﺎ‬
‫ﮔﺬﺭﮔﺎﻩ ﺁﺯﺍﺩ ﺍﺳﺖ ﻳﺎ ﺧﻴﺮ ‪ ،‬ﻭ ﺍﮔﺮ ﺍﺷﻐﺎﻝ ﺍﺳﺖ ﺩﺭ ﺍﺧﺘﻴﺎﺭ ﻛﺪﺍﻡ ﻣﺎژﻭﻝ ﺍﺳﺖ‪ .‬ﻫﻤﭽﻨﻴﻦ ﺍﺯ‬
‫ﺕﺍﺭﻳﺨﭽﻪ ﻱ ﺍﺳﺘﻔﺎﺩﻩ ﻣﺘﻘﺎﺿﻴﺎﻥ‬
‫ﻣﺨﺘﻠﻒ ﺁﮔﺎﻩ ﺍﺳﺖ ﻭ ﻣﻲ ﺗﻮﺍﻧﺪ ﺑﺮ ﺍﻳﻦ ﺍﺳﺎﺱ ﺍﻭﻟﻮﻳﺖ ﺑﻨﺪﻱ ﻛﻨﺪ‪.‬‬
‫ﺩﺭ ﺍﻳﻦ ﺗﻤﺮﻳﻦ ﻳﻚ ﺩﺍﻭﺭ ﮔﺬﺭ ﮔﺎﻩ ﻃﺮﺍﺣﻲ ﺧﻮﺍﻫﻴﺪ ﻛﺮﺩ ﻛﻪ ﺑﺎ ﺩﻭ ﻣﺘﻘﺎﺿﻲ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﮔﺬﺭﮔﺎﻩ؛ ﻛﻪ ﺁﻥ ﺭﺍ ﻫﻢ ﺑﺎﻳﺪ ﺧﻮﺩ‬
‫ﻃﺮﺍﺣﻲ ﻛﻨﻴﺪ‪ ،‬ﺗﻤﺎﺱ ﺑﺮ ﻗﺮﺍﺭ ﻣﻲ ﻛﻨﺪ‪ .‬ﻫﺮ ﻣﺘﻘﺎﺿﻲ ﺑﺎ ﻳﻚ ﺧﻂ ) ‪ (Request‬ﺗﻘﺎﺿﺎﻱ ﺧﻮﺩ ﺭﺍ ﺑﻪ ﺩﺍﻭﺭ ﺍﺭﺍﺋﻪ ﻛﺮﺩﻩ ﻭ ﺑﺎ ﻳﻚ‬
‫ﺧﻂ ﺩﻳﮕﺮ ) ‪ (Grant‬ﻧﺘﻴﺠﻪ ﺭﺍ ﺩﺭﻳﺎﻓﺖ ﻣﻲ ﻛﻨﺪ‪ .‬ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ﺑﻪ ﻳﻚ ‪ Request‬ﺍﺟﺎﺯﻩ ﻱ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﮔﺬﺭﮔﺎﻩ ﺩﺍﺩﻩ ﺷﺪﻩ‬
‫ﺯﺑﺎﻥ ﻫﺎﻱ ﺗﻮﺻﻴﻒ ﺳﺨﺖ ﺍﻓﺰﺍﺭ‬
‫ﭘﺎﻳﻴﺰ ‪90‬‬
‫ﺑﺎﺷﺪ‪ ID ،‬ﻳﻜﺘﺎﻱ ﺧﻮﺩ ﺭﺍ ﺭﻭﻱ ﮔﺬﺭ ﮔﺎﻩ ﻗﺮﺍﺭ ﺩﺍﺩﻩ ﻣﻲ ﺷﻮﺩ‪ .‬ﺩﺭ ﺻﻮﺭﺕ ﻭﺟﻮﺩ ﺗﻘﺎﺿﺎﻱ ﻣﺸﺘﺮﻙ ) ‪(Common Request‬‬
‫ﺩﺍﻭﺭ )‪ (Arbiter‬ﺩﺭ ﻫﺮ ‪ 2‬ﺳﻴﻜﻞ ﻛﻼﻙ ﻣﺘﻮﺍﻟﻲ ﺻﺎﺣﺐ ‪ Bus‬ﺭﺍ ﻋﻮﺽ ﻣﻲ ﻛﻨﺪ‪.‬‬
‫ﺩﺭ ﺻﻮﺭﺕ ﻭﺟﻮﺩ ﺗﻘﺎﺿﺎﻱ ﻣﺸﺘﺮﻙ‪ ،‬ﻣﻘﺎﺩﻳﺮ ﺭﻭﻱ ﮔﺬﺭ ﮔﺎﻩ ﺭﺍ ﻧﺸﺎﻥ ﺩﻫﻴﺪ‪ .‬ﭘﻬﻨﺎﻱ ﮔﺬﺭﮔﺎﻩ ﻣﺸﺘﺮﻙ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ‬
‫‪ Parameter‬ﺩﺭ ﻧﻈﺮ ﺑﮕﻴﺮﻳﺪ‪.‬‬
‫‪ 3‬ﻭﺍﺣﺪ ﺫﻛﺮ ﺷﺪﻩ ﺭﺍ ﻃﺮﺍﺣﻲ ﻛﻨﻴﺪ ﻭ ﺑﺮﺍﻱ ﺁﻥ ‪ TestBench‬ﺑﻨﻮﻳﺴﻴﺪ‪ 70) .‬ﺍﻣﺘﻴﺎﺯ(‬
‫‪U‬‬
‫ﻣﻬﻠﺖ ﺗﺤﻮﻳﻞ‬
‫ﺷﻨﺒﻪ ‪ 14‬ﺑﻬﻤﻦ ‪ 90‬ﺳﺎﻋﺖ ‪23:55‬‬
‫ﻟﻄﻔﺎ ﺗﻮﺟﻪ ﺩﺍﺷﺘﻪ ﺑﺎﺷﻴﺪ ﻛﻪ ﺍﻳﻦ ﻣﻬﻠﺖ ﻏﻴﺮ ﻗﺎﺑﻞ ﺗﻐﻴﻴﺮ ﺍﺳﺖ‪.‬‬
‫‪U‬‬
‫‪U‬‬
‫ﻧﻜﺎﺕ ﻋﻤﻮﻣﻲ‬
‫‪ .1‬ﺗﻤﺮﻳﻦ ﻫﺎﻱ ﺧﻮﺩ ﺭﺍ ﺗﺎ ﻗﺒﻞ ﺍﺯ ﻣﻬﻠﺖ ﺁﻥ ﺑﻪ ﺁﺩﺭﺱ‬
‫‪) [email protected]‬ﺑﺎ ﻋﻨﻮﺍﻧﻲ ﻣﺮﺗﺒﻂ ﻭ ﻧﺎﻡ ﻭ ﺷﻤﺎﺭﻩ ﺩﺍﻧﺸﺠﻮﻳﻲ(‬
‫‪U‬‬
‫‪U‬‬
‫ﺍﺭﺳﺎﻝ‬
‫ﻛﻨﻴﺪ‪.‬‬
‫‪ .2‬ﻣﻨﺎﺑﻊ ﻭ ﺭﺍﻫﻨﻤﺎﻳﻲ ﻫﺎﻱ ﻣﺮﺑﻮﻁ ﺑﻪ ﺍﺑﺰﺍﺭ ‪ Celoxica Agility Compiler‬ﺭﺍ ﻣﻲ ﺗﻮﺍﻧﻴﺪ ﺩﺭ ﻗﺴﻤﺖ ﻣﻨﺎﺑﻊ ﺩﺭ‬
‫ﺳﺎﻳﺖ ﺩﺭﺱ ﭘﻴﺪﺍ ﻛﻨﻴﺪ ﻳﺎ ﺑﻪ ﺭﺍﻫﻨﻤﺎﻱ ﻛﺎﺭﺑﺮ ﺍﻳﻦ ﺍﺑﺰﺍﺭ ﻣﺮﺍﺟﻌﻪ ﻛﻨﻴﺪ ) ‪Celoxica Agility Compiler‬‬
‫‪U‬‬
‫‪U‬‬
‫‪.(User Manual‬‬
‫‪ .3‬ﺟﻤﻊ ﻧﻤﺮﺍﺕ ﺍﻳﻦ ﭘﺮﻭژﻩ ‪ 450‬ﺍﺯ ‪ 300‬ﺍﺳﺖ ﻭ ﻣﻲ ﺗﻮﺍﻧﻴﺪ ‪ %50‬ﺗﺸﻮﻳﻘﻲ ﺑﮕﻴﺮﻳﺪ‪.‬‬
‫‪ .4‬ﺑﺎ ﺗﻮﺟﻪ ﺑﺎ ﻭﻗﺖ ﻣﻮﺟﻮﺩ ﻭ ﻣﺤﺪﻭﺩﻳﺖ ﺩﺭ ﺯﻣﺎﻥ ﺍﺭﺳﺎﻝ ﻧﻤﺮﺍﺕ‪ ،‬ﺗﺤﻮﻳﻞ ﺑﺎ ﺗﺎﺧﻴﺮ ﺑﻪ ﻫﻴﭻ ﻭﺟﻪ ﭘﺬﻳﺮﻓﺘﻪ ﻧﻤﻲ ﺷﻮﺩ‪.‬‬
‫ﭘﻴﺮﻭﺯ ﻭ ﻣﻮﻓﻖ ﺑﺎﺷﻴﺪ‬
‫ﺍﻳﺰﺩﻱ ﺭﺍﺩ‬