128
IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 1, JANUARY 2008
Gate Fringe-Induced Barrier Lowering in Underlap
FinFET Structures and Its Optimization
Angada B. Sachid, C. R. Manoj, Dinesh K. Sharma, Senior Member, IEEE,
and V. Ramgopal Rao, Senior Member, IEEE
Abstract—The difficulty to fabricate and control precisely
defined doping profiles in the source/drain underlap regions of
FinFETs necessitates the use of undoped gate underlap regions as
the technology scales down. We present a phenomenon called the
gate fringe-induced barrier lowering (GFIBL) in FinFETs with
undoped underlap regions. In these FinFETs, we show that the
GFIBL can be effectively used to improve Ion . We propose the use
of high-κ spacers in such FinFETs to enhance the effect of GFIBL
and thereby achieve better device and circuit performance. When
compared with the underlap FinFETs with Si3 N4 spacers, with
κ = 20 spacers, we show that it is possible to achieve an 80%
increase in Ion at iso-Ioff conditions and a 15% decrease in the
inverter delay for a fan-out of four.
Index Terms—CMOS scaling, FinFET, fringe-induced barrier
lowering (GFIBL), high-κ materials, short-channel effects (SCEs).
I. I NTRODUCTION
A
MONG the emerging multiple-gate devices for the sub32-nm technology nodes, FinFETs are the most promising candidates due to their superior scalability and ease of
processing. FinFETs have been demonstrated with both overlap
[1] and underlap regions [2]. FinFETs with graded or abrupt
gate overlaps show a higher Ioff as the technologies are scaled
down [3], which suggests that overlap regions need to be
carefully optimized in these devices. Due to this reason, the
use of underlaps with an optimized graded doping profile has
received considerable interest recently [3], [4]. As we continue
to scale down the FinFETs, the fins need to get thinner in order
to control short-channel effects (SCEs) [4]. Not only that the
doping profiles in such thin fins are difficult to experimentally
realize [5] but also that the process variations lead to a large
variation in the device characteristics. The use of undoped
underlaps with abrupt source/drain junctions seems to be an
attractive technology option for the future technology nodes.
The effect of underlap length (LUN ) on the dc characteristics
of FinFETs with Si3 N4 spacers is shown in Fig. 1, which
clearly establishes the need for underlaps. In this paper, we
report for the first time a phenomenon called the gate fringe-
Manuscript received September 12, 2007. The review of this letter was
arranged by Editor B. Yu.
The authors are with the Center for Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400 076,
India (e-mail: [email protected]; [email protected]; dinesh@ee.
iitb.ac.in; [email protected]).
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2007.911974
Fig. 1. DC characteristics of a pure underlap FinFET with Si3 N4 spacers
(VDD = 1 V) as a function of the underlap length.
induced barrier lowering (GFIBL) in underlap FinFETs. The
conclusions from GFIBL suggest that the use of high-κ spacers
in FinFETs with undoped underlaps could offer an interesting
alternative to improve the device and circuit performance.
II. D EVICE S TRUCTURE
We have used a 2-D FinFET structure [Fig. 2(a)] with a
channel length (LG ) of 20 nm, a fin thickness (TFIN ) of 10 nm,
and an effective oxide thickness of 0.75 nm [6]. LUN is kept at
20 nm, and the gate-electrode thickness (TG ) is kept at twice
the LG value unless stated otherwise. The source/drain and
source/drain extension doping values are kept at 1020 cm−3 ,
whereas the channel and underlap doping values are kept at
1015 cm−3 . The threshold voltage (VT ) of the device is set at
about 0.2 V for all the data presented here. The simulations
are performed using the Sentaurus design suite [7] with the
drift-diffusion mobility, density-gradient quantum correction,
and band-to-band tunneling models being turned on.
III. G ATE F RINGE -I NDUCED B ARRIER
L OWERING (GFIBL)
GFIBL occurs in FinFETs with undoped underlap regions.
The fringing field lines from the gate electrode terminate in
the source/drain underlap regions. Fig. 2(b) (left) shows that
the gate-electrode thickness (TG ) modulates the barrier in this
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SACHID et al.: GFIBL IN UNDERLAP FinFET STRUCTURES AND ITS OPTIMIZATION
129
Fig. 2. (a) The top cross-sectional view of the FinFET structure showing the gate length (LG ), underlap length (LUN ), extension region length (LEXT ), and
physical oxide thickness (TOX ). (b) Variation of conduction band energy as a function of X at various gate-electrode thicknesses (left) and at VG = 0 and
VG = VDD (= 1 V) (right).
region. Fig. 2(b) (right) shows that the barrier does not lower
completely when VGS = VDD (= 1 V). This barrier lowering in
the underlap regions allows more carriers from the source to
enter into the channel region, resulting in higher Ion [Fig. 3(a)],
which eventually saturates for TG > 25 nm.
GFIBL is indeed quite different from the FIBL which is
observed in high-κ gate dielectrics [8]–[11]. In the FIBL, the
additional coupling through the high-κ gate dielectric degrades
the SCEs in FinFETs [12]. However, the GFIBL does not
degrade VT or subthreshold slope or Ioff [Fig. 3(a)] since it is
confined to the undoped underlap regions and does not affect
the barrier under the gate. Fig. 3(b) shows that, as the underlap
length is decreased, the effect of GFIBL and, hence, the difference in Ion with different TG values decrease, vanishing when
the S/D regions touch the gate edge.
spacers with κ = 20. Ioff degrades significantly for κ > 20 as
the increase in the electric field on the drain side causes a higher
band-to-band tunneling. The Ion /Ioff ratio peaks at κ ≈ 18. As
shown in Fig. 5, the use of high-κ spacers linearly increases
the fringe capacitance component of the total gate capacitance
CGG . When compared to Si3 N4 spacers, CGG increases by
about 50% for spacers with κ = 20. The circuit delay which
is a function of the load capacitance and the drive current
now depends on their relative rate of change with κ. Fig. 5
shows a considerable change in the propagation delay (tP )
for 1 < κ < 20 after which tP saturates. When compared with
underlap FinFETs with Si3 N4 spacers, with κ = 20 spacers,
there is a 15% decrease in the delay of an inverter with a fanout of four. However, in order to offset the capacitance increase
in scaling, the high-κ regions in underlap FinFETs need to be
carefully optimized.
IV. U NDERLAP F IN FET S W ITH H IGH -κ S PACERS
We propose the use of high-κ (κ > 7.5) spacers to increase
the electric-field coupling between the gate electrode and the
underlap regions to further lower the barrier in the source
underlap region. Fig. 4 shows that the Ion increases with an
increasing κ due to the enhanced GFIBL. When compared
to Si3 N4 (κ = 7.5) spacers, Ion increases by about 80% for
V. C ONCLUSION
We present a new phenomenon called the GFIBL in FinFETs
with undoped underlap regions. We further show that the use of
high-κ spacers in FinFETs enhances GFIBL, which considerably increases Ion . Using an optimal value of κ for the spacers,
it is possible to improve the device drive currents by about 80%
130
IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 1, JANUARY 2008
Fig. 5. Total gate capacitance of an underlap FinFET with high-κ spacers and
the transient characteristics of an inverter with a fan-out = 4 as a function of
spacer κ.
and the transient performance of FinFET circuits by about 15%
in aggressively scaled FinFET technologies.
ACKNOWLEDGMENT
The authors would like to thank the Microelectronics Group,
Department of Electrical Engineering, Indian Institute of Technology Bombay, for the stimulating discussions. They would
also like to thank Synopsys, Inc. for providing the advanced
simulation tools to make this simulation study possible.
R EFERENCES
Fig. 3. (a) DC characteristics of a pure underlap FinFET as a function of TG .
(LG = 20 nm, TFIN = 10 nm, TOX = 0.75 nm, LUN = 20 nm, VT = 0.2 V,
and κ = 7.5). (b) Ion of a pure underlap FinFET for gate-electrode thickness,
TG = 2 nm, and TG = 40 nm as a function of LUN (κ = 7.5).
Fig. 4. DC characteristics of an underlap FinFET with high-κ spacer as a
function of spacer κ.
[1] H.-S. P. Wong, K. K. Chan, and Y. Taur, “Self-aligned (top and bottom)
double-gate MOSFET with a 25 nm thick silicon channel,” in IEDM Tech.
Dig., Dec. 1997, pp. 427–430.
[2] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski,
E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian,
T.-J. King, J. Bokor, and C. Hu, “Sub-50 nm p-channel FinFET,” IEEE
Trans. Electron Devices, vol. 48, no. 5, pp. 880–886, May 2001.
[3] V. Trivedi, J. G. Fossum, and M. M. Chowdhury, “Nanoscale FinFETs
with gate–source/drain underlaps,” IEEE Trans. Electron Devices, vol. 52,
no. 1, pp. 56–62, Jan. 2005.
[4] J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy,
D. Boyd, D. Fried, and H.-S. P. Wong, “Extension and source/drain design
for high-performance FinFET devices,” IEEE Trans. Electron Devices,
vol. 50, no. 4, pp. 952–958, Apr. 2003.
[5] D. Pham, L. Larson, and J.-W. Yang, “FinFET device junction formation challenges,” in Proc. Int. Workshop Junction Technol., May 2006,
pp. 73–77.
[6] International Technology Roadmap for Semiconductors, 2005.
[Online]. Available: http://public.itrs.net
[7] Synopsys Sentaurus Design Suite. [Online]. Available: www.synopsys.
com
[8] G. C.-F. Yeap, S. Krishnan, and M.-R. Lin, “Fringing-induced barrier
lowering (FIBL) in sub-100 nm MOSFETs with high-κ gate dielectrics,”
Electron. Lett., vol. 34, no. 11, pp. 1150–1152, May 1998.
[9] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “The
effect of high-κ gate dielectrics on deep sub-micrometer CMOS device
and circuit performance,” IEEE Trans. Electron Devices, vol. 49, no. 5,
pp. 826–831, May 2002.
[10] Q. Chen, L. Wang, and J. D. Meindl, “Fringe-induced barrier lowering
(FIBL) induced threshold voltage model for double-gate MOSFETs,”
Solid State Electron., vol. 49, no. 2, pp. 271–274, Feb. 2005.
[11] B.-Y. Tsui and L.-F. Chin, “A comprehensive study of the FIBL of
nanoscale MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 10,
pp. 1733–1735, Oct. 2004.
[12] C. R. Manoj and V. R. Rao, “Impact of high-κ gate dielectrics on the
device and circuit performance of nanoscale FinFETs,” IEEE Electron
Device Lett., vol. 28, no. 4, pp. 295–297, Apr. 2007.