1st Edition
Fall 2001
Very High-Capacity
FPGA Devices
Programmable Logic Design
Fall 2001
By: Maziar Gudarzi
Altera FLEX10K
Overall Architecture
Figure
FPGA-2
Notes
Flex10k = Flex8000 + Embedded Array Blocks (EAB)
The EAB is a flexible block of RAM with registers on the input and output ports, and is used
to implement common gate array megafunctions. When used as RAM, each EAB can be
configured in any of the following sizes: 256 × 8, 512 × 4, 1,024 × 2, or 2,048 × 1.
Combination of EABs is possible to provide wider or larger blocks of RAM.
Flex10k devices offer from 10,000 up to 250,000 typical gates (or 31,000 up to 310,000
maximum system gates, according to Altera)
Flex10kA and Flex10kV devices work with 3.3 volt supply voltage.
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Sharif University of Technology
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Programmable Logic Design
Fall 2001
By: Maziar Gudarzi
Altera FLEX10K
EAB Structure
Figure
FPGA-3
Notes
Flex10k Logic Elements (LE) and Logic Array Blocks (LABs) are almost identical to
Flex8000 devices.
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Sharif University of Technology
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Programmable Logic Design
Fall 2001
By: Maziar Gudarzi
Altera APEX20K,20KE
Figure
FPGA-4
Device Block Diagram
- Provides from 30,000 upto 1.5 million typical gates (from 113,000 up to 2.4 million
maximum system gates, according to Altera)
- Provides up to 440K bit of RAM
- APEX20KxxxE devices operate internally in 1.8 volt, other in 2.5 volt.
Notes
Contains:
• LUT-based Logic-Array Block (LABs) more suitable for data-flow applications.
• Product-term modules more suitable for control applications
• Memory for data storage
Hence, can integrate complete systems.
Contains:
• Local interconnect between adjacent LEs in a row to allow higher performance.
• Device-wide MegaLAB interconnect to facilitate faster interconnection in longer paths
Provides
• SignalTap embedded logic analyzer to allow easier debug of hardware
• MultiVoltIO to allow connection to standard TTL devices
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Programmable Logic Design
Fall 2001
By: Maziar Gudarzi
Altera APEX20K
Logic Element Digram
Figure
FPGA-5
Notes
Contains:
• Carry and Cascade chains as in FLEX8000 and FLEX10k
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Sharif University of Technology
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Programmable Logic Design
Fall 2001
By: Maziar Gudarzi
Altera APEX20K
Figure
FPGA-6
Embedded System Block (ESB)
Notes
Allow implementation of various types of memory structures, including dual-port RAM,
single port RAM, Content-Addressable Memory (CAM), etc.
APEX II FPGAs provide from 600,000 up to 3M typical gates, or 1.9M up to 5.25M
maximum system gates (according to Altera).
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Sharif University of Technology
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Programmable Logic Design
Fall 2001
By: Maziar Gudarzi
Xilinx Virtex FPGAs
Overall Architecture
Figure
FPGA-7
- Densities from 50K up to 1 million gates.
- From 24K up to 390K bit of RAM
Notes
Contains two major programmable parts:
• Configurable Logic Blocks (CLBs)
• Input/Output Blocks (IOBs)
CLBs interconnect through a general routing matrix (GRM). The GRM comprises an array of
routing switches located at the intersections of horizontal and vertical routing channels. Each
CLB nests into a VersaBlock™ that also provides local routing resources to connect the CLB
to the GRM.
VersaRing provides additional routing resources.
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Sharif University of Technology
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Programmable Logic Design
Fall 2001
By: Maziar Gudarzi
Xilinx Virtex FPGAs
Figure
FPGA-8
2-Slice Virtex CLB
Notes
CLBs can also be configured as various memory structures.
Virtex II devices provide from 40K up to 8M (according to Xilinx) system gates, and up to
3M bit of RAM.
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Sharif University of Technology
Page FPGA-8