‫‪١٣٨٠/٩/١‬‬
‫ﺣﻞ اﻣﺘﺤﺎن ﻣﻴﺎن ﺗﺮم درس ﻣﻌﻤﺎری ﮐﺎﻣﭙﻴﻮﺗﺮ )‪(۴٠٣٢٣‬‬
‫ﺟﻮﺍﺏ ‪:۱‬‬
‫‪1011100‬‬
‫‪10111‬‬
‫‪00000100100‬‬
‫‪11011100000‬‬
‫‪01001000000‬‬
‫‪00101000100‬‬
‫‪Sub‬‬
‫‪3 Shifts + Add‬‬
‫‪Shift + Sub‬‬
‫‪Add All Partial Products‬‬
‫*‬
‫‪-36‬‬
‫‪-9‬‬
‫*‬
‫‪+‬‬
‫‪324‬‬
‫ﻳﺎ‬
‫‪10111‬‬
‫‪1011100‬‬
‫‪00000100100‬‬
‫‪11011100000‬‬
‫‪01001000000‬‬
‫‪00101000100‬‬
‫‪2 Shift + Sub‬‬
‫‪3 Shifts + Add‬‬
‫‪Shift + Sub‬‬
‫‪Add All Partial Products‬‬
‫*‬
‫‪-9‬‬
‫‪-36‬‬
‫*‬
‫‪+‬‬
‫‪324‬‬
‫ﺟﻮﺍﺏ ‪:۲‬‬
‫ﺍﻟﻒ‪ -‬ﺷﮑﻞ ﺟﻤﻊ ﮐﻨﻨﺪﻩ ‪ ۱۶‬ﺑﻴﺘﯽ ‪ Carry Lookahead‬ﺩﺭ ﺻﻔﺤﻪ ‪ ۴۲۶‬ﮐﺘﺎﺏ ﺁﻣﺪﻩ ﺍﺳﺖ‪ .‬ﺗﻨﻬﺎ ﺑﺎﻳﺪ ﺑﺮﺍﯼ ﮐﻨﺘﺮﻝ‬
‫ﺁﻥ ﻳﮏ ﺑﻴﺖ ﺍﺧﺘﺼﺎﺹ ﺩﺍﺩ ﮐﻪ ﻋﻤﻞ ﺟﻤﻊ ﻳﺎ ﺗﻔﺮﻳﻖ ﺍﻧﺠﺎﻡ ﺩﻫﺪ ﻭ ﺁﻥ ﺑﻴﺖ ﺭﺍ ﺑﻪ ‪ Carry‬ﻭﺭﻭﺩﯼ ﻭﺻﻞ ﮐﺮﺩ ﻭ ﺑﺎ‬
‫ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺁﻥ ﺑﺎ ﻳﮏ ‪ MUX‬ﻭ ﻳﺎ ‪ XOR‬ﮐﻨﺘﺮﻝ ﮐﺮﺩ ﮐﻪ ‪ B‬ﻳﺎ ‪ NOT B‬ﺑﻪ ﻭﺭﻭﺩﯼ ﺟﻤﻊ ﮐﻨﻨﺪﻩ ﺑﻴﺎﻳﺪ‪.‬‬
‫ﺳﻴﮕﻨﺎﻝ ‪ S‬ﻫﻤﺎﻥ ‪ S15‬ﺍﺳﺖ ﻭ ‪ C‬ﻧﻴﺰ ﻫﻤﺎﻥ ‪ Cout‬ﺟﻤﻊ ﮐﻨﻨﺪﻩ ﻣﯽ ﺑﺎﺷﺪ‪ V = Cn-1 XOR Cout .‬ﻭ ‪ Z‬ﺧﺮﻭﺟﯽ ﻳﮏ‬
‫‪ ۱۶ NOR‬ﻭﺭﻭﺩﯼ ﮐﻪ ﻭﺭﻭﺩﻳﻬﺎﯼ ﺁﻥ ‪ S0‬ﺗﺎ ‪ S15‬ﺍﺳﺖ ﻣﯽ ﺑﺎﺷﺪ‪.‬‬
‫ﺏ‪ -‬ﺣﺪﺍﻗﻞ ﺍﻧﺪﺍﺯﻩ ‪ ۲۴ * ۱۰ ROM‬ﻣﯽ ﺑﺎﺷﺪ‪ .‬ﻳﻌﻨﯽ ﺗﺎﺑﻌﯽ ﺑﺎ ‪ ۴‬ﻭﺭﻭﺩﯼ ﻭ ‪ ۱۰‬ﺧﺮﻭﺟﯽ ﮐﻪ ﻭﺭﻭﺩﻳﻬﺎ ﻫﻤﺎﻥ‬
‫ﺳﻴﮕﻨﺎﻟﻬﺎﯼ ‪ S, C, V, Z‬ﻫﺴﺘﻨﺪ‪ .‬ﺧﺮﻭﺟﻴﻬﺎ ‪ ۴‬ﺗﺎﺑﻊ ≤ ‪ >, ≥, <,‬ﺑﺮﺍﯼ ﺩﻭ ﺣﺎﻟﺖ ﺑﺎﻋﻼﻣﺖ ﻭ ﺑﻲ ﻋﻼﻣﺖ )ﺩﺭ‬
‫ﻣﺠﻤﻮﻉ ‪ ۸‬ﺗﺎﺑﻊ( ﻭ ﺩﻭ ﺣﺎﻟﺖ ≠ ‪ =,‬ﺑﺮﺍﯼ ﺍﻋﺪﺍﺩ ﺑﺎﻋﻼﻣﺖ ﻭ ﺑﯽ ﻋﻼﻣﺖ ﮐﻪ ﻳﮑﺴﺎﻥ ﺍﺳﺖ‪.‬‬
‫ﺑﺮﻧﺎﻣﻪ ﺭﻳﺰﯼ ‪ ROM‬ﻧﻴﺰ ﺑﺴﺘﮕﯽ ﺑﻪ ﭼﮕﻮﻧﻪ ﻗﺮﺍﺭﺩﺍﺩﻥ ﺑﻴﺘﻬﺎﯼ ﻭﺭﻭﺩﯼ ﻭ ﺧﺮﻭﺟﯽ ﺩﺍﺭﺩ‪ .‬ﻣﺜﻼ ﻳﮏ ﺣﺎﻟﺖ ﻣﯽ ﺗﻮﺍﻧﺪ‬
‫ﺑﺼﻮﺭﺕ ﺯﻳﺮ ﺑﺎﺷﺪ‪:‬‬
‫‪Both‬‬
‫≠‬
‫‪1‬‬
‫‪0‬‬
‫‪1‬‬
‫‪0‬‬
‫‪.‬‬
‫=‬
‫‪0‬‬
‫‪1‬‬
‫‪0‬‬
‫‪1‬‬
‫‪.‬‬
‫ﺻﻔﺤﻪ ‪١‬‬
‫≤‬
‫‪0‬‬
‫‪1‬‬
‫‪0‬‬
‫‪1‬‬
‫‪.‬‬
‫‪Unsigned‬‬
‫≥‬
‫<‬
‫‪1‬‬
‫‪0‬‬
‫‪1‬‬
‫‪0‬‬
‫‪1‬‬
‫‪0‬‬
‫‪1‬‬
‫‪0‬‬
‫‪.‬‬
‫‪.‬‬
‫‪Signed‬‬
‫>‬
‫‪1‬‬
‫‪0‬‬
‫‪1‬‬
‫‪0‬‬
‫‪.‬‬
‫≤‬
‫‪0‬‬
‫‪1‬‬
‫‪1‬‬
‫‪1‬‬
‫‪.‬‬
‫<‬
‫‪0‬‬
‫‪0‬‬
‫‪1‬‬
‫‪1‬‬
‫‪.‬‬
‫‪SCVZ‬‬
‫≥‬
‫‪1‬‬
‫‪1‬‬
‫‪0‬‬
‫‪0‬‬
‫‪.‬‬
‫>‬
‫‪1‬‬
‫‪0‬‬
‫‪0‬‬
‫‪0‬‬
‫‪.‬‬
‫‪0000‬‬
‫‪0001‬‬
‫‪0010‬‬
‫‪0011‬‬
‫‪...‬‬
١٣٨٠/٩/١
(۴٠٣٢٣) ‫ﺣﻞ اﻣﺘﺤﺎن ﻣﻴﺎن ﺗﺮم درس ﻣﻌﻤﺎری ﮐﺎﻣﭙﻴﻮﺗﺮ‬
:۳ ‫ﺟﻮﺍﺏ‬
M0
‫ﻣﺎﺷﻴﻦ‬
‫ ﺑﺮﻧﺎﻣﻪ ﻣﻮﺭﺩ ﻧﻈﺮ‬Push D
Push E
Sub
Push F
Add
Push B
Push C
Add
Push A
Mul
Div
Pop X
M1
Load D
Sub E
Add F
Store temp
Load B
Add C
Mul A
Div temp
Store X
M2
Load R1, B
Add R1, C
Mul R1, A
Load R2, D
Sub R2, E
Add R2, F
Store temp, R2
Div R1, temp
Store X, R1
M3
Load R1, A
Load R2, B
Load R3, C
Add R4, R2, R3
Mul R4, R4, R1
Load R1, D
Load R2, E
Load R3, F
Sub R5, R1, R2
Add R5, R5, R3
Div R6, R4, R5
Store X, R6
:۴ ‫ﺟﻮﺍﺏ‬
۱۰ ‫ ﺭﺍ ﺩﺭ‬SWAP ‫ ﺑﺪﻭﻥ ﻫﻴﭻ ﺗﻐﻴﻴﺮ ﺩﻳﮕﺮﯼ ﻣﯽ ﺗﻮﺍﻥ ﺩﺳﺘﻮﺭ‬،‫ ﺍﺿﺎﻓﻪ ﺷﻮﺩ‬XOR ‫ ﺗﺎﺑﻊ‬ALU ‫ ﺍﮔﺮ ﺑﻪ‬-‫ﺍﻟﻒ‬
‫ ﮐﻪ ﺩﺭ ﺁﻥ ﺩﺭ‬.‫ ﺗﻌﺮﻳﻒ ﻣﯽ ﺷﻮﺩ‬R ‫ ﺍﺯ ﻧﻮﻉ‬SWAP ‫ ﺩﺭ ﺍﻳﻦ ﺣﺎﻟﺖ ﺩﺳﺘﻮﺭ‬.‫ﺳﻴﮑﻞ ﺑﺼﻮﺭﺕ ﺯﻳﺮ ﺍﺟﺮﺍ ﮐﺮﺩ‬
.‫ ﺑﺮﺍﺑﺮ ﺁﺩﺯﺱ ﺛﺒﺎﺕ ﺩﻳﮕﺮ ﻗﺮﺍﺭ ﻣﯽ ﮔﻴﺮﺩ‬rt ‫ ﺑﺮﺍﺑﺮ ﻳﮑﺪﻳﮕﺮ ﻭ ﺑﺮﺍﺑﺮ ﺁﺩﺭﺱ ﻳﮑﯽ ﺍﺯ ﺛﺒﺎﺗﻬﺎ ﻭ‬rs, rd ‫ﻓﻴﻠﺪﻫﺎﯼ‬
Fetch:
Decode:
EXE1:
WB1:
Decode2:
EXE2:
WB2:
Decode3:
EXE3:
WB3:
IR<- MEM[PC] ; PC<- PC+4
A<- R[rs] ; B <- R[rt] ; PC <- PC+sign_extend(imm16)
ALUout <- A xor B
R[rt] <- ALUout
A<- R[rs] ; B <- R[rt]
ALUout <- A xor B
R[rd] <- ALUout
A<- R[rs] ; B <- R[rt]
ALUout <- A xor B
R[rt] <- ALUout
‫ ﺁﺩﺭﺱ‬rs, rt ‫ ﺗﻌﺮﻳﻒ ﻣﯽ ﺷﻮﺩ ﮐﻪ ﺩﺭ‬I ‫ ﺳﻴﮑﻞ ﻣﯽ ﺑﺎﺷﺪ ﮐﻪ ﺩﺳﺘﻮﺭ ﺍﺯ ﻧﻮﻉ‬۴ ‫ ﺳﺮﻳﻌﺘﺮﻳِﻦ ﺣﺎﻟﺖ ﻣﻤﮑﻦ ﺩﺭ‬-‫ﺏ‬
‫ ﺩﺭ ﺍﻳﻦ ﺣﺎﻟﺖ‬.‫ ﺁﻥ ﺑﺮﺍﺑﺮ ﺻﻔﺮ ﺍﺳﺖ‬imm16 ‫ ﺷﻮﻧﺪ ﻗﺮﺍﺭ ﻣﯽ ﮔﻴﺮﺩ ﻭ ﻓﻴﻠﺪ‬SWAP ‫ﺛﺒﺎﺗﻬﺎﻳﯽ ﮐﻪ ﺑﺎﻳﺪ ﺑﺎ ﻳﮑﺪﻳﮕﺮ‬
ALUout
MDR
B
0
busW
1
2
MemtoReg
rt rd rs
0 1 2
:‫ﺗﻐﻴﻴﺮﺍﺕ ﺯﻳﺮ ﺩﺭ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺍﻳﺠﺎﺩ ﻣﯽ ﺷﻮﺩ‬
RegDst
W
٢ ‫ﺻﻔﺤﻪ‬
١٣٨٠/٩/١
(۴٠٣٢٣) ‫ﺣﻞ اﻣﺘﺤﺎن ﻣﻴﺎن ﺗﺮم درس ﻣﻌﻤﺎری ﮐﺎﻣﭙﻴﻮﺗﺮ‬
:‫ﺩﺭ ﺍﻳﻦ ﺣﺎﻟﺖ ﺳﻴﮑﻠﻬﺎﯼ ﺯﻳﺮ ﺟﻬﺖ ﺍﺟﺮﺍﯼ ﺍﻳﻦ ﺩﺳﺘﻮﺭ ﻃﯽ ﻣﯽ ﺷﻮﺩ‬
Fetch:
Decode:
EXE1:
EXE2:
IR<- MEM[PC] ; PC<- PC+4
A<- R[rs] ; B <- R[rt] ; PC <- PC+sign_extend(imm16)
R[rs] <- B ; ALUout <- A+zero_extend(imm16)
R[rt] <- ALUout
:۵ ‫ﺟﻮﺍﺏ‬
:‫( ﺁﻥ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﻣﯽ ﺑﺎﺷﺪ‬FSM) ‫ ﻣﺎﺷﻴﻦ ﺣﺎﻟﺖ ﻣﺤﺪﻭﺩ‬-‫ﺍﻟﻒ‬
Fetch
Decode
Op = Load or
Op = Branch
OP = Store
Op = AL
ExeWB
Address
Branch
Op = Store
Op = Load
SMem
RMem
WB
Fetch:
Decode:
ExeWB:
Address:
SMem:
RMem:
WB:
Branch:
IR<- Imem[PC] ; PC<- PC+2
A<- R[rs] ; B <- R[rd]
R[rt] <- sh( A func B) ; also save flags!
MAR <- A+sign_extend(imm8)
DMem[MAR] <- B
MDR <- DMem[MAR]
R[rd] <- MDR
if (condition) then PC<- PC+sign_extend(imm6) << 1
٣ ‫ﺻﻔﺤﻪ‬
١٣٨٠/٩/١
(۴٠٣٢٣) ‫ﺣﻞ اﻣﺘﺤﺎن ﻣﻴﺎن ﺗﺮم درس ﻣﻌﻤﺎری ﮐﺎﻣﭙﻴﻮﺗﺮ‬
:‫ﺳﻴﮕﻨﺎﻟﻬﺎﯼ ﮐﻨﺘﺮﻟﯽ ﺑﺮﺍﯼ ﻫﺮ ﺣﺎﻟﺖ ﺑﺼﻮﺭﺕ ﺯﻳﺮ ﻓﻌﺎﻝ ﻣﯽ ﺷﻮﻧﺪ‬
Fetch:
Decode:
ExeWB:
Address:
SMem:
RMem:
WB:
Branch:
IRWr =1, PCWr=1, ALUsrcA=0, ALUsrcB=01, ImemRd=1, ALUctrl=010,
SHUctrl = 00
Nothing!
RegWr=1, MemtoReg=0, RegDst=0, ALUsrcA=1, ALUsrcB=00,
ALUctrl=func, SHUctrl=sh
ALUsrcA=1, ALUsrcB=10, ALUctrl=010, SHUctrl=00, immSel=0
DmemWr=1
DMemRd=1
RegWr=1, MemtoReg=1, RegDst=1
ALUsrcA=0, ALUsrcB=11, ALUctrl=010, SHUctrl=00, immSel=1, PCWr =
condition
:‫ ﻓﻴﻠﺪﻫﺎﯼ ﻭﺍﺣﺪ ﮐﻨﺘﺮﻝ ﺭﺍ ﺑﺮﺍﺳﺎﺱ ﺩﺳﺘﻪ ﺑﻨﺪﯼ ﺳﻴﮕﻨﺎﻟﻬﺎﯼ ﮐﻨﺘﺮﻟﯽ ﺑﺼﻮﺭﺕ ﺯﻳﺮ ﺗﺸﮑﻴﻞ ﻣﯽ ﺩﻫﻴﻢ‬-‫ﺏ‬
Fields
Register
Values
SrcA
SrcB
ALU
SHU
Read
PC
B
Add
Pass
WriteRt
WriteRd
A
2
Imm8
Func
Sh
ALUctr
l
SHUctr
l
PC
WriteP
C
IRIMe
m
WriteIR
DMem
Read
Fetch
Write
Seq
Dispatch
1
Dispatch
2
Nothing!
Imm6
Signal
s
RegDst
ALUsrc
A
ALUsrc
B
immSel
RegWr
PCWr
IRWr
IMemR
d
Seq
DMemR
d
DMemW
r
MemtoRe
g
:‫ ﺑﺼﻮﺭﺕ ﺯﻳﺮ ﺍﺳﺖ‬AL ‫ ﺭﻳﺰ ﺩﺳﺘﻮﺭﺍﻟﻌﻤﻠﻬﺎﯼ ﻭﺍﺣﺪ ﮐﻨﺘﺮﻝ ﺑﺮﺍﯼ ﺩﺳﺘﻮﺭﺍﺕ ﻧﻮﻉ‬-‫ﺝ‬
Label
Fetch
Decode
ExeWB
...
Register
Read
WriteRt
SrcA
PC
2
SrcB
ALU
Add
SHU
Pass
A
B
Func
Sh
PC
WritePC
IRIMem
WriteIR
DMem
Seq
Seq
Dispatch1
Fetch
۴ ‫ﺻﻔﺤﻪ‬